Pressure testing method, apparatus, electronic device, and computer-readable storage medium
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2025-12-16
- Publication Date
- 2026-06-02
Smart Images
Figure CN121364990B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure relate to a method, apparatus, electronic device, and computer-readable storage medium for stress testing a processing device. Background Technology
[0002] Stress testing of processors such as GPUs (Graphics Processing Units) is a method of evaluating their performance, stability, and heat dissipation capabilities by continuously running the processor under extremely high loads. This testing aims to simulate extreme use cases (such as intensive gaming, 3D rendering, or AI computing) to examine the processor's performance under extreme conditions, helping users discover potential hardware problems or system bottlenecks. Summary of the Invention
[0003] At least one embodiment of this disclosure provides a method for stress testing a processing device, comprising: extracting N test code segments from a set of test code segments, wherein the set of test code segments includes M test code segments for testing multiple characteristics of the processing device, each test code segment being used to test at least one of the multiple characteristics, the multiple characteristics being used to reflect one or more aspects of the performance of the processing device, the processing device including at least access performance, computing performance, and storage performance; combining the N test code segments and filling in information to form test code; and using the test code to stress test the processing device; wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to N.
[0004] For example, in at least one example of the method provided in the above embodiments of this disclosure, extracting N test code fragments from a set of test code fragments includes: randomly extracting N test code fragments from the set of test code fragments.
[0005] For example, in at least one example of the method provided in the above embodiments of this disclosure, extracting N test code snippets from a set of test code snippets includes: determining multiple features to be tested according to custom test requirements; and extracting N test code snippets corresponding to the multiple features to be tested from the set of test code snippets.
[0006] For example, in at least one example of the method provided in the above embodiments of this disclosure, combining and filling information of the N test code segments includes: combining the N test code segments in a random order.
[0007] For example, in at least one example of the method provided in the above embodiments of this disclosure, combining and filling information of the N test code fragments includes: combining the N test code fragments in a custom order.
[0008] For example, in at least one example of the method provided in the above embodiments of this disclosure, the N test code segments are combined and information is filled in to form test code; the processing device is tested using the test code, including: performing multiple rounds of test operations, wherein each round of test operations includes: combining the N test code segments and filling in information to form test code for the current round, wherein the combination order of the N test code segments in the current round is different from the combination order of the previous round, and the information filled in the current round is different from the information filled in the previous round; and the processing device is tested multiple times using the test code of the current round.
[0009] For example, in at least one example of the method provided in the above embodiments of this disclosure, combining and filling information into the N test code segments includes: filling parameter information and hardware resource information into each of the N test code segments, wherein the N test code segments each use different hardware resource groups, and the base address of the hardware resources of the later test code segment is determined based on the number of hardware resources of the previous test code segment; or, the N test code segments share the same group of hardware resources.
[0010] For example, in at least one example of the method provided in the above embodiments of this disclosure, the parameter information filled for each test code fragment is a random parameter.
[0011] For example, in the method provided in at least one example of the above embodiments of this disclosure, the plurality of features include: a plurality of access features for a plurality of access objects, a plurality of computation features for a plurality of computation operations, a plurality of storage features for a plurality of types of data, synchronization features, and atomic operation features.
[0012] For example, in a method provided in at least one example of the above embodiments of this disclosure, stress testing the processing device using the test code includes: randomly matching the respective running units for the N test code fragments from the available running units.
[0013] For example, in at least one example of the method provided in the above embodiments of this disclosure, stress testing the processing device using the test code includes: configuring each of the N test code fragments into a running unit from the available running units according to a custom configuration strategy.
[0014] For example, in at least one example of the method provided in the above embodiments of this disclosure, the method further includes: obtaining test results, wherein the test results include sub-test results corresponding to each of the N test code segments.
[0015] At least one embodiment of this disclosure provides an apparatus for stress testing a processing device, comprising: an extraction module, a combination module, and a testing module. The extraction module is configured to extract N test code fragments from a set of test code fragments, wherein the set of test code fragments includes M test code fragments for testing multiple characteristics of the processing device, each test code fragment testing at least one of the multiple characteristics, the multiple characteristics reflecting one or more aspects of the performance of the processing device, the processing device including at least access performance, computing performance, and storage performance; the combination module is configured to combine the N test code fragments and populate them with information to form test code; the testing module is configured to perform stress testing on the processing device using the test code; wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to N.
[0016] At least one embodiment of this disclosure provides an electronic device, including a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement a method for stress testing a processing device provided in any embodiment of this disclosure.
[0017] At least one embodiment of this disclosure provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, can implement the method for stress testing a processing device provided in any embodiment of this disclosure. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.
[0019] Figure 1 A flowchart is shown illustrating a method for stress testing a processing device according to at least one embodiment of this disclosure;
[0020] Figure 2 A schematic block diagram of a pressure testing apparatus for a processing device provided in at least one embodiment of the present disclosure is shown;
[0021] Figure 3 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown;
[0022] Figure 4 A schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure is shown; and
[0023] Figure 5 A schematic diagram of a computer-readable storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0026] For GPUs, stress testing can assess various features that reflect their performance. For example, access characteristics to objects like HBM (High Bandwidth Memory) and shared memory reflect the GPU's access performance, while operational characteristics such as matrix multiplication and floating-point arithmetic reflect its computational performance. Furthermore, depending on the types of functions or tasks the GPU can perform, even more features can be included; a specific function, task, or operation can be considered a feature.
[0027] For example, in the pre-silicon verification stage, specific features can be verified by writing assembly code by hand. However, this approach suffers from repetitive development. For instance, when testing feature 1 or feature 2 individually, a set of test code can be developed for each feature. If it's necessary to test the combination of feature 1 and feature 2, another set of test code for this combination needs to be developed. Each feature combination requires a separate set of test code covering that combination, which takes developers a long time to complete independently, resulting in low development efficiency. Furthermore, with separate code developed for each feature combination, the number of feature combinations that can be tested is limited, making it difficult to cover all possible combinations. Also, the order of features in a pre-developed set of test code is fixed; changing the order requires developing a new set of test code. Therefore, this approach struggles to achieve randomness and cover a wide range of scenarios.
[0028] At least one embodiment of this disclosure provides a method for stress testing a processing device, an apparatus for stress testing a processing device, an electronic device, and a computer-readable storage medium. The method for stress testing a processing device includes: extracting N test code segments from a set of test code segments, wherein the set of test code segments includes M test code segments for testing multiple characteristics of the processing device, each test code segment testing at least one of the multiple characteristics, the multiple characteristics reflecting one or more aspects of the performance of the processing device, the processing device including at least access performance, computing performance, and storage performance; combining the N test code segments and populating them with information to form test code; and stress testing the processing device using the test code; wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to N.
[0029] In this method for stress testing the processing device, corresponding test code snippets are pre-developed for each required characteristic. During testing, these test code snippets are extracted, combined, and populated with information to form complete test code. This allows for the acquisition of test code for various characteristic combinations through simple extraction and combination operations, eliminating the need to develop separate test code for each combination. The developed test code snippets can be reused, improving efficiency. Furthermore, this approach can cover many possible scenarios, such as multiple different characteristic combinations, enhancing the diversity and comprehensiveness of the testing.
[0030] Figure 1 A flowchart is shown of a method for stress testing a processing device according to at least one embodiment of the present disclosure.
[0031] like Figure 1 As shown, the method may include steps S110 to S130.
[0032] Step S110: Extract N test code snippets from the test code snippet set. The test code snippet set includes M test code snippets used to test multiple characteristics of the processing device. Each test code snippet is used to test at least one of the multiple characteristics, which reflect one or more aspects of the performance of the processing device. For example, the processing device includes at least access performance, computing performance, and storage performance.
[0033] Step S120: Combine the N test code snippets and populate them with information to form test code.
[0034] Step S130: Perform a stress test on the processing device using test code.
[0035] For example, N is an integer greater than or equal to 1, and M is an integer greater than or equal to N. For example, M can be an integer greater than or equal to 2, meaning that the set of test code snippets can include two or more test code snippets.
[0036] For example, in this embodiment, the processing device may be a GPU, but this disclosure is not limited thereto. In other embodiments, the processing device may also be a CPU (Central Processing Unit), an NPU (Neural Processing Unit), or other processing devices.
[0037] For example, GPUs have various functions and can perform various tasks, such as accessing HBM, accessing shared memory, performing matrix multiplication operations, and storing matrix data. Any function of a GPU or any task or operation it can perform can be considered a characteristic. Each characteristic reflects the GPU's performance in at least one aspect. For example, the characteristics of accessing HBM and accessing shared memory both reflect the GPU's performance in access, while the characteristics of matrix multiplication and floating-point arithmetic both reflect the GPU's performance in data computation.
[0038] For example, in this embodiment of the disclosure, corresponding test code snippets can be pre-developed for each required feature. Each test code snippet can be used to test one or more features. That is, each test code snippet can correspond to one feature or two or more features, and each test code snippet is independent of the others.
[0039] For example, each test code snippet may include code for the operations involved in implementing the feature, but may not include specific parameters, hardware resources used, or other information. In other words, each test code snippet may not be a directly executable, complete test code; rather, this specific information can be filled in at the time of use to form complete executable code. For instance, for a feature that accesses a class, the corresponding test code snippet may include access statements and access objects, but may not include specific access addresses or other parameter information.
[0040] For example, multiple developers can collaboratively develop multiple test code snippets. Since each test code snippet is independent, each developer can be responsible for a portion of the test code snippets. Each developer uses a unified interface to jointly implement the development of the multiple required test code snippets, which together form a test code snippet set. In this way, multiple people can develop different test code snippets simultaneously and easily combine them, improving development efficiency.
[0041] For example, the multiple characteristics involved in this set of test code snippets may include: multiple access characteristics for multiple access objects (e.g., HBM, shared memory, etc.), multiple computational characteristics for multiple computational operations (e.g., matrix multiplication, floating-point arithmetic, etc.), multiple storage characteristics for multiple data types (e.g., matrix data, floating-point numbers, etc.), synchronization characteristics, and atomic operation characteristics. For instance, accessing HBM can be considered a characteristic, accessing shared memory can be considered a characteristic, performing matrix multiplication can be considered a characteristic, performing matrix data storage can be considered a characteristic, performing data synchronization can be considered a characteristic, performing atomic operations can be considered a characteristic, and so on. It should be noted that the characteristics given here are merely illustrative and not restrictive; other characteristics may be involved in other embodiments.
[0042] For example, after obtaining the set of test code snippets, when stress testing the processing device is required, steps S110 to S130 can be executed. In step S110, multiple test code snippets can be extracted from the set of test code snippets, each of which corresponds to at least one feature. These multiple test code snippets can be randomly selected or selected as needed. In step S120, the extracted multiple test code snippets can be combined, which can refer to concatenating multiple test code snippets. Step S120 can also fill each test code snippet with the required information, such as parameter information, hardware resource allocation information, etc., to make it executable code. In step S130, the processing device can execute the test code formed in step S120 to perform stress testing on the processing device using the test code.
[0043] For example, in addition to extracting multiple test code snippets, some embodiments may also include extracting a single test code snippet. In this case, the single test code snippet can be populated with information to form executable test code, which can enable testing of a single feature.
[0044] According to embodiments of this disclosure, corresponding test code snippets are pre-developed for each required feature. During testing, these test code snippets are extracted, combined, and populated with information to form complete test code. In this way, test code for various feature combinations can be obtained through simple extraction and combination operations, eliminating the need to develop separate test code for each feature combination. The developed test code snippets can be reused, improving efficiency. Furthermore, this approach can cover many possible scenarios, such as multiple different feature combinations, enhancing the diversity and comprehensiveness of testing.
[0045] For example, in some embodiments, step S110, extracting N test code fragments from the test code fragment set, includes: randomly extracting N test code fragments from the test code fragment set.
[0046] For example, you can set the extraction quantity and then randomly extract the corresponding number of test code snippets from the test code snippet set; or, the value of N can be random, that is, the number of snippets extracted each time can be random, and a random number of test code snippets can be extracted from the test code snippet set.
[0047] For example, during stress testing of a processing device, multiple rounds of testing can be performed. After each round or every few rounds of testing, several test code snippets can be randomly extracted again, and the number of snippets extracted each time can be different.
[0048] According to embodiments of this disclosure, by randomly extracting test code snippets, the randomness of the test can be improved, enabling the test to cover more possible situations and the test results to be more comprehensive.
[0049] For example, in some other embodiments, step S110, extracting N test code snippets from the test code snippet set, includes: determining multiple features to be tested according to custom test requirements; and extracting N test code snippets corresponding to the multiple features to be tested from the test code snippet set.
[0050] For example, when a user wants to test a combination of features, they can input multiple features to be tested, and the system can extract the corresponding test code snippets from the test code snippet set. For instance, if a user wants to test a combination of feature1 and feature2, the system can extract the test code snippets corresponding to feature1 and feature2 from the test code snippet set.
[0051] According to embodiments of this disclosure, by customizing test requirements, the required combination of features can be tested according to the user's needs, enabling the test to meet the user's customized requirements. Alternatively, individual features can also be tested according to user needs.
[0052] For example, extracting test code snippets from a collection of test code snippets can be achieved by calling a function. For instance, a function `genCode` can be predefined to extract test code snippets from the collection. When a test code snippet needs to be extracted, this function can be called.
[0053] For example, in some embodiments, step S120, combining N test code segments and filling in information, includes: combining N test code segments in a random order.
[0054] For example, the order in which the extracted test code snippets are combined can be random. For instance, in step S110, the first test code snippet S1 corresponding to feature1, the second test code snippet S2 corresponding to feature2, and the third test code snippet S3 corresponding to feature3 are extracted. When combining them, the order of the first, second, and third test code snippets can be random.
[0055] According to embodiments of this disclosure, by combining multiple test code snippets in a random order, the randomness of the test can be further improved, enabling the test to cover more possible situations and the test results to be more comprehensive.
[0056] For example, in other embodiments, step S120, combining and filling information into N test code snippets, includes: combining the N test code snippets in a custom order.
[0057] For example, the order of multiple extracted test code snippets can be customized by the user according to their needs. For instance, the user can define the order of features, and the order of features can serve as the order of the test code snippets corresponding to those features.
[0058] For example, in some embodiments, users can define a specific order of multiple features. When the extracted test code snippet involves two or more of these features, they can be combined according to the set order. For example, if the user sets the order of feature1, feature2, and feature3 as feature1-feature2-feature3 (from first to last), and if the features extracted in step S110 include feature1 and feature3, then during the combination, they will be combined in the order of feature1 first and feature3 last.
[0059] For example, in other embodiments, the user can define the order of multiple feature categories. Some features may belong to the same category. The category may include, for example, storage category, access category, computing category, etc. Taking access category and storage category as an example, if the user specifies that access category precedes storage category, then when the features extracted in step S110 include access category features and storage category features, they are combined in the order of access category features first and storage category features last.
[0060] According to embodiments of this disclosure, by user-defined combination order, the required combination of orders can be tested according to the user's needs, so that the test can meet the user's needs.
[0061] For example, when executing steps S120 and S130, multiple rounds of testing operations can be performed. Each round of testing operations includes: combining N test code segments and filling them with information to form the test code for the current round. The combination order of the N test code segments in the current round is different from the combination order in the previous round, and the information filled in the current round is different from the information filled in the previous round. The processing device is then tested multiple times using the test code for the current round.
[0062] For example, stress testing can be performed in multiple rounds. Each round generates test code for that round, which is then used for testing. For instance, the same N test code snippets can be used in consecutive rounds, but the order in which these N snippets are combined in the later round can differ from the order in the earlier round. This allows testing of the same feature combinations with different orders, resulting in a more comprehensive testing scope.
[0063] For example, in each round of testing, the generated test code can be executed multiple times in a loop. The generated test code can include initialization code and main code, where the main code consists of code formed by combining multiple test code snippets and filling in information. This main code can be executed repeatedly. Each time it is executed, it is determined whether the number of executions or the execution time has reached the expected value. If not, it is executed again until the number of executions or the execution time reaches the expected value.
[0064] For example, in step S120, the N test code segments are combined and information is filled in, including filling parameter information and hardware resource information for each of the N test code segments. The N test code segments use different hardware resource groups, and the base address of the hardware resource of the later test code segment is determined based on the number of hardware resources of the previous test code segment; or, the N test code segments share the same group of hardware resources.
[0065] For example, when allocating hardware resources for the N test code snippets, if the number of available hardware resources is greater than or equal to a certain threshold, it indicates that hardware resources are relatively abundant. In this case, different sets of hardware resources can be allocated to the N test code snippets, with each snippet's hardware resources being independent. In this scenario, the N test code snippets can be executed in parallel, improving testing efficiency. Conversely, if the number of available hardware resources is less than a certain threshold, it indicates that hardware resources are insufficient. In this case, the N test code snippets can be allocated the same set of hardware resources. In this scenario, the N test code snippets share the same set of hardware resources and are executed serially. For example, hardware resources can include register resources, shared memory resources, etc.
[0066] For example, the parameter information filled for each test code snippet can be random parameters. In some embodiments, the parameter information filled for each test code snippet can be randomly generated parameters. The category of parameter information may also differ depending on the type of characteristic. Therefore, the category of random parameters can be pre-set for different types of characteristics. For example, for access-related characteristics, the parameter category can be access address; for computation-related characteristics, the parameter category can be numerical value. In other embodiments, a parameter set can be pre-stored, and when filling parameters, parameters of the corresponding category can be randomly selected from the parameter set. By randomly setting parameters, the randomness of the test is further increased.
[0067] For example, the operation of filling information into test code snippets can be implemented by calling functions. For instance, functions genInput and getResource can be predefined. The genInput function can be used to fill parameters and other information into test code snippets, and the getResource function can be used to allocate hardware resources to test code snippets.
[0068] For example, in some embodiments, stress testing the processing device using test code may include: randomly matching each of the N test code snippets to a respective execution unit from the available execution units.
[0069] For example, the execution unit can be a Warp. A Warp is the basic scheduling and execution unit of threads in a GPU. When running the test code formed by these N test code snippets, a random Warp can be set to run random test code snippets, which increases the randomness of the runtime and allows the test process to cover more possibilities.
[0070] For example, in other embodiments, stress testing the processing device using test code may include configuring execution units for N test code snippets from available execution units according to a custom configuration strategy. For instance, the execution unit may be a Warp, and it can be configured to run which test code snippet or type of test code snippet using which Warp, based on requirements. This allows the execution units of test code snippets to be matched according to user needs, ensuring the test meets those needs.
[0071] For example, the testing method may also include: obtaining test results, wherein the test results include sub-test results corresponding to each of the N test code snippets.
[0072] For example, after the test is completed, you can check whether the execution results for each test code snippet meet expectations, so that you can find the problem in time and solve it specifically if an issue arises. Obtaining test results can also be achieved by calling predefined functions.
[0073] Figure 2 A schematic block diagram of an apparatus 200 for stress testing a processing device, provided in at least one embodiment of the present disclosure, is shown.
[0074] For example, such as Figure 2 As shown, the device 200 includes an extraction module 210, a combination module 220, and a test module 230. These components are interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, these modules can be implemented as hardware (e.g., circuit) modules, software modules, or any combination of both, as is the case in the following embodiments, and will not be repeated here. For example, these units can be implemented using a central processing unit (CPU), a graphics processing unit (GPU), a tensor processor (TPU), a field-programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, along with corresponding computer instructions. It should be noted that... Figure 2The components and structure of the device 200 shown are merely exemplary and not limiting; the device 200 may also have other components and structures as needed.
[0075] Extraction module 210 is configured to extract N test code snippets from a set of test code snippets, wherein the set of test code snippets includes M test code snippets for testing multiple characteristics of the processing device, each test code snippet testing at least one of the multiple characteristics, which reflect one or more aspects of the performance of the processing device, including at least access performance, computational performance, and storage performance. Extraction module 210 may, for example, execute... Figure 1 Step S110 is described.
[0076] The combination module 220 is configured to combine the N test code fragments and populate them with information to form test code. For example, the combination module 220 can execute... Figure 1 Step S120 is described.
[0077] Test module 230 is configured to perform stress tests on the processing device using the test code. Test module 230 may, for example, execute... Figure 1 Step S130 is described.
[0078] For example, N is an integer greater than or equal to 1, and M is an integer greater than or equal to N.
[0079] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the extraction module 210 is further configured to randomly extract N test code segments from the test code segment set.
[0080] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the extraction module 210 is further configured to: determine multiple features to be tested according to customized test requirements; and extract N test code segments corresponding to the multiple features to be tested from the set of test code segments.
[0081] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the combination module 220 is further configured to combine the N test code fragments in a random order.
[0082] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the combination module 220 is further configured to combine the N test code fragments in a custom order.
[0083] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the combination module 220 and the testing module 230 are further configured to: perform multiple rounds of testing operations, wherein each round of testing operations includes: combining the N test code segments and filling them with information to form the test code for the current round, wherein the combination order of the N test code segments in the current round is different from the combination order of the previous round, and the information filled in the current round is different from the information filled in the previous round; and performing multiple tests on the processing apparatus using the test code for the current round.
[0084] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the combination module 220 is further configured to: fill parameter information and hardware resource information for each of the N test code segments, wherein the N test code segments adopt different hardware resource groups respectively, and the base address of the hardware resource of the later test code segment is determined based on the number of hardware resources of the previous test code segment; or, the N test code segments share the same group of hardware resources.
[0085] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the parameter information filled for each test code fragment is a random parameter.
[0086] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the plurality of features include: a plurality of access features for a plurality of access objects, a plurality of computation features for a plurality of computation operations, a plurality of storage features for a plurality of types of data, synchronization features, and atomic operation features.
[0087] For example, in an apparatus provided in at least one example of the embodiments described above, the test module 230 is further configured to randomly match the respective running units for the N test code segments from the available running units.
[0088] For example, in the apparatus provided in at least one example of the above embodiments of this disclosure, the test module 230 is further configured to: configure the respective running units for the N test code fragments from the available running units according to a custom configuration strategy.
[0089] For example, in at least one example of the apparatus provided in the above embodiments of this disclosure, a result module is further included, configured to obtain test results, wherein the test results include sub-test results corresponding to each of the N test code segments.
[0090] For example, the extraction module 210, the combination module 220, and the testing module 230 can be hardware, software, firmware, or any feasible combination thereof. For example, the extraction module 210, the combination module 220, and the testing module 230 can be dedicated or general-purpose circuits, chips, or devices, or a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the above-mentioned units.
[0091] For example, the extraction module 210, the combination module 220, and the testing module 230 may include code and programs stored in memory; the processor may execute the code and programs to implement some or all of the functions of the image extraction module 210, the combination module 220, and the testing module 230 as described above. For example, the extraction module 210, the combination module 220, and the testing module 230 may be dedicated hardware devices used to implement some or all of the functions of the extraction module 210, the combination module 220, and the testing module 230 as described above. For example, the extraction module 210, the combination module 220, and the testing module 230 may be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In embodiments of this disclosure, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) processor-executable firmware stored in memory.
[0092] It should be noted that, in the embodiments of this disclosure, each unit of the apparatus 200 for stress testing the processing device corresponds to each step of the aforementioned method for stress testing the processing device. For the specific functions of the apparatus 200 for stress testing the processing device, please refer to the relevant description of the method for stress testing the processing device, which will not be repeated here. Figure 2 The components and structure of the stress testing apparatus 200 shown are exemplary and not limiting. The stress testing apparatus 200 may include other components and structures as needed. The stress testing apparatus 200 may include more or fewer circuits or units, and the connection relationships between the circuits or units are not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited; it may be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.
[0093] At least one embodiment of this disclosure also provides an electronic device including a processor and a memory storing one or more computer program modules. The one or more computer program modules are configured to be executed by the processor to implement the method described above for stress testing a processing device.
[0094] Figure 3 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. For example... Figure 3 As shown, the electronic device 300 includes a processor 310 and a memory 320. The memory 320 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 310 executes the non-transitory computer-readable instructions, which, when executed by the processor 310, perform one or more steps of the stress testing method for the processing device described above. The memory 320 and the processor 310 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For specific implementations and explanations of the various steps of the stress testing method for the processing device, please refer to the embodiments of the stress testing method for the processing device described above; repetitions will not be repeated here.
[0095] It should be noted that Figure 3 The components of the electronic device 300 shown are merely exemplary and not limiting. The electronic device 300 may have other components as needed for the actual application.
[0096] For example, the processor 310 and the memory 320 can communicate with each other directly or indirectly.
[0097] For example, processor 310 and memory 320 can communicate via a network. The network can include wireless networks, wired networks, and / or any combination of wireless and wired networks. Processor 310 and memory 320 can also communicate with each other via a system bus, and this disclosure is not limiting in this regard.
[0098] For example, processor 310 can control other components in electronic device 300 to perform desired functions. For example, processor 310 can be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be an x86 or ARM architecture. Processor 310 can be a general-purpose processor or a special-purpose processor, and can control other components in electronic device 300 to perform desired functions.
[0099] For example, memory 320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 310 may run one or more computer program modules to implement various functions of electronic device 300. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.
[0100] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 300 can be referred to the description of the method for stress testing the processing device above, and will not be repeated here.
[0101] Figure 4 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 400 is, for example, suitable for implementing the method for stress testing a processing device provided in embodiments of the present disclosure. The electronic device 400 may be a terminal device, etc. It should be noted that... Figure 4 The illustrated electronic device 400 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments of this disclosure.
[0102] like Figure 4 As shown, electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 410, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 420 or a program loaded from storage device 480 into random access memory (RAM) 430. RAM 430 also stores various programs and data required for the operation of electronic device 400. The processing device 410, ROM 420, and RAM 430 are interconnected via bus 440. Input / output (I / O) interface 450 is also connected to bus 440.
[0103] Typically, the following devices can be connected to I / O interface 450: input devices 460 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 470 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 480 including, for example, magnetic tapes, hard disks, etc.; and communication devices 490. Communication device 490 allows electronic device 400 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 4 An electronic device 400 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 400 may alternatively implement or have more or fewer devices.
[0104] For example, according to embodiments of this disclosure, the method for stress testing a processing device described above can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for executing the method for stress testing a processing device described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 490, or installed from a storage device 480, or installed from a ROM 420. When the computer program is executed by the processing device 410, the functions defined in the method for stress testing a processing device provided by embodiments of this disclosure can be implemented.
[0105] At least one embodiment of this disclosure also provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, can implement the above-described method for stress testing a processing device.
[0106] Figure 5 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 5 As shown, the storage medium 500 stores non-transitory computer-readable instructions 510. For example, when the non-transitory computer-readable instructions 510 are executed by a computer, one or more steps of the method for stress testing the processing device as described above are performed.
[0107] For example, the storage medium 500 can be used in the aforementioned electronic device 300. For example, the storage medium 500 can be... Figure 3 The memory 320 in the illustrated electronic device 300. For example, a description of the storage medium 500 can be found here. Figure 3 The corresponding description of the memory 320 in the illustrated electronic device 300 will not be repeated here.
[0108] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.
[0109] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.
[0110] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.
[0111] The following points should be noted regarding this disclosure:
[0112] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.
[0113] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0114] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.
Claims
1. A pressure testing method for pressure testing a processing device, characterized by, The method includes: N test code snippets are extracted from the test code snippet set, wherein the test code snippet set includes M test code snippets for testing multiple characteristics of the processing device, each of the test code snippets is used to test at least one of the multiple characteristics, the multiple characteristics being used to reflect one or more aspects of the performance of the processing device; The N test code snippets are combined and populated with information to form test code; The processing device is subjected to a stress test using the test code. The process includes combining the N test code fragments and filling them with information to form test code, and then using the test code to test the processing device, including: Perform multiple rounds of testing operations, wherein each round of testing operations includes: combining the N test code fragments and filling in information to form the test code for the current round, wherein the combination order of the N test code fragments is random, and the combination order of the N test code fragments in the current round is different from the combination order in the previous round; and using the test code of the current round to perform multiple tests on the processing device; Where N is an integer greater than or equal to 1, and M is an integer greater than or equal to N.
2. The method of claim 1, wherein, Extract N test code snippets from the set of test code snippets, including: Randomly extract N test code snippets from the set of test code snippets.
3. The method of claim 1, wherein, Extract N test code snippets from the set of test code snippets, including: Based on the customized testing requirements, identify multiple features to be tested; Extract N test code snippets corresponding to the plurality of features to be tested from the set of test code snippets.
4. The method according to any one of claims 1 to 3, characterized in that, The information filled in the current round is different from the information filled in the previous round.
5. The method according to any one of claims 1-3, characterized in that, The N test code snippets are combined and populated with information, including: For each of the N test code snippets, fill in the parameter information and hardware resource information. The N test code segments each use different hardware resource groups, and the base address of the hardware resources of the later test code segment is determined based on the number of hardware resources of the previous test code segment; or, the N test code segments share the same group of hardware resources.
6. The method of claim 5, wherein, The parameter information filled for each test code snippet is random.
7. The method according to any one of claims 1-3, characterized in that, The multiple characteristics include: multiple access characteristics for multiple access objects, multiple computation characteristics for multiple computational operations, multiple storage characteristics for multiple types of data, synchronization characteristics, and atomic operation characteristics.
8. The method of any one of claims 1-3, wherein, The processing device is subjected to stress testing using the test code, including: From the available execution units, randomly match the respective execution units for the N test code snippets.
9. The method of any one of claims 1-3, wherein, The processing device is subjected to stress testing using the test code, including: According to the custom configuration strategy, configure the respective running units for the N test code snippets from the available running units.
10. The method of any one of claims 1-3, wherein, Also includes: Obtain test results, wherein the test results include sub-test results corresponding to each of the N test code snippets.
11. A pressure testing device for pressure testing a processing device, characterized by The device includes: The extraction module is configured to extract N test code snippets from a set of test code snippets, wherein the set of test code snippets includes M test code snippets for testing multiple characteristics of the processing device, each of the test code snippets being used to test at least one of the multiple characteristics, the multiple characteristics being used to reflect one or more aspects of the performance of the processing device; The combination module is configured to combine the N test code fragments and populate them with information to form test code; and The testing module is configured to perform stress tests on the processing device using the test code; The combination module is further configured to perform multiple rounds of testing operations, wherein each round of testing operations includes: combining the N test code segments and filling in information to form the test code for the current round, wherein the combination order of the N test code segments is random, and the combination order of the N test code segments in the current round is different from the combination order in the previous round; The testing module is further configured to perform multiple tests on the processing device using the test code of the current round in each round of testing operations; Where N is an integer greater than or equal to 1, and M is an integer greater than or equal to N.
12. An electronic device, comprising: include: processor; Memory, which stores one or more computer program modules; The one or more computer program modules are configured to be executed by the processor to implement the stress testing method according to any one of claims 1-10.
13. A computer-readable storage medium, characterized in that, It stores non-transitory computer-readable instructions that, when executed by a computer, can implement the stress testing method according to any one of claims 1-10.