DDR adapter plate and life detection method thereof, storage medium
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KINGTIGER TESTING TECH (SZ) LTD
- Filing Date
- 2025-10-27
- Publication Date
- 2026-07-03
Smart Images
Figure CN121365022B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of testing technology, and in particular to a DDR adapter board and its lifespan testing method, and a storage medium. Background Technology
[0002] Currently, DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory) UDIMM (Unbuffered Dual In-Line Memory Module) and SODIMM (Small Outline Dual In-line Memory Module) signals are compatible. However, to adapt to different application scenarios, the gold fingers and shape of DDR4 UDIMMs differ from those of SODIMMs. In SODIMM memory testing and screening, adapter boards are typically used to test SODIMMs on UDIMM testing machines, thus saving development and testing costs. General-purpose DDR4 adapter boards include gold fingers, slots, and SPD (Serial Presence Detect) devices. Since DDR4 adapter boards can only accommodate (DDR4) SODIMMs,...
[0003] Because the gold fingers and slots of the DDR4 adapter board wear down during insertion and removal, a certain number of insertions and removals can significantly affect the high-speed signal quality of DDR and may even cause test failure. Since the DDR4 adapter board cannot count the number of insertions and removals, when a SODIMM test fails, it is impossible to determine whether the failure is due to a problem with the DRAM chip or the lifespan of the gold fingers and slots of the DDR4 adapter board. This requires time and manpower to locate the problem, affecting test efficiency and quality.
[0004] Therefore, how to detect and record the lifespan of DDR adapter boards and improve the testing efficiency and quality of SODIMM is an urgent problem to be solved.
[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention
[0006] The main purpose of this application is to provide a DDR adapter board and its lifespan testing method and storage medium, aiming to solve the technical problem of how to test and record the lifespan of DDR4 adapter boards and improve the testing efficiency and quality of SODIMM.
[0007] To achieve the above objectives, this application proposes a DDR adapter board, which includes gold fingers, EEPROM, slots, and IIC address conversion circuitry.
[0008] The EEPROM is electrically connected to the IIC address conversion circuit, the IIC address conversion circuit is electrically connected to the address bus in the IIC bus, one end of the address bus is electrically connected to the IIC address interface of the gold finger, and the other end is electrically connected to the IIC address interface of the slot.
[0009] The IIC address conversion circuit is used to convert the IIC address of the address bus to obtain the target IIC address and write the target IIC address into the EEPROM;
[0010] The EEPROM is used to store the number of times the adapter board has been plugged in and out, as well as the remaining number of plugging in and out.
[0011] In one embodiment, the IIC address conversion circuit includes an inverter, and the address interface of the EEPROM is electrically connected to a preset address bus of the address bus through the inverter.
[0012] In one embodiment, at least one address interface of the EEPROM is electrically connected to a corresponding preset address bus via the inverter, and the other address interfaces are electrically connected to their respective preset address buses.
[0013] In one embodiment, the IIC address translation circuit includes a resistor;
[0014] In the address interface of the EEPROM, at least one address interface corresponding to a high-level preset address bus is grounded through a resistor, and / or at least one address interface corresponding to a low-level preset address bus is electrically connected to the power supply through a resistor.
[0015] In one embodiment, the processor updates the number of insertions / removals and the remaining number of insertions / removals in the EEPROM based on the target IIC address corresponding to the EEPROM.
[0016] Furthermore, to achieve the above objectives, this application also proposes a lifespan testing method for an adapter board, applied to the aforementioned DDR adapter board, wherein the lifespan testing method for the adapter board includes:
[0017] Upon receiving a plug-in / plug-out count update command, based on the target IIC address corresponding to the EEPROM, the number of plug-in / plug-out cycles and the remaining number of plug-in / plug-out cycles corresponding to the DDR adapter board are read from the EEPROM.
[0018] Update the number of plug-in / plug-out operations and the remaining number of plug-in / plug-out operations, and obtain the updated number of plug-in / plug-out operations and the updated number of remaining plug-in / plug-out operations;
[0019] Write the updated number of plug-in / plug-out cycles and the updated number of remaining plug-in / plug-out cycles into the EEPROM.
[0020] In one embodiment, when the insertion / removal count update instruction is received, the step of reading the inserted / removed count and remaining insertion / removal count corresponding to the DDR adapter board from the EEPROM based on the target IIC address corresponding to the EEPROM includes:
[0021] Two IIC addresses are obtained through the IIC bus, including the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be tested.
[0022] Obtain the slave IIC address corresponding to the motherboard IIC bus, and determine the target IIC address in the EEPROM based on the slave IIC address among the two IIC addresses;
[0023] Based on the target IIC address, the number of times the DDR adapter board has been plugged in and out and the number of times it remains plugged in and out are read from the EEPROM.
[0024] In one embodiment, the step of writing the updated number of insertions / removals and the updated number of remaining insertions / removals into the EEPROM includes:
[0025] Determine whether the remaining number of plug-in / plug-out cycles after the update is greater than the preset value;
[0026] If the updated remaining number of plug-in / plug-out cycles is greater than or equal to the preset value, then the updated number of plug-in / plug-out cycles and the updated remaining number of plug-in / plug-out cycles are written to the EEPROM.
[0027] In one embodiment, after the step of determining whether the updated remaining number of plug-in / plug-out cycles is greater than or equal to a preset value, the lifespan detection method for the adapter board further includes:
[0028] If the remaining number of plug-in / plug-out cycles after the update is less than the preset value, a message will be output indicating that the DDR adapter board has reached the maximum number of tests.
[0029] In addition, to achieve the above objectives, this application also proposes a storage medium, characterized in that the storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium, wherein when the computer program is executed by a processor, the steps of the aforementioned adapter board life detection method are implemented.
[0030] One or more technical solutions proposed in this application have at least the following technical effects:
[0031] The IIC address of the address bus is converted by the IIC address conversion circuit, so that the IIC interface address of the EEPROM device is different from the IIC address stored in the SPD of the corresponding SODIMM to be tested, so as to distinguish between EEPROM and SPD. Then, the insertion and removal count and remaining insertion and removal count of the corresponding adapter board can be accurately read and updated by the IIC address stored in EEPROM. The lifespan of DDR adapter board is determined based on the updated insertion and removal count or the updated remaining insertion and removal count, thus realizing accurate detection of the lifespan of DDR adapter board and improving the testing efficiency and quality of SODIMM. Attached Figure Description
[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the DDR adapter board provided in this application;
[0035] Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the DDR adapter board of this application;
[0036] Figure 3 A simplified flowchart illustrating a life testing method for an adapter board provided in an embodiment of this application;
[0037] Figure 4 This is a schematic diagram of the hardware operating environment involved in the life detection method of the adapter board in the embodiments of this application.
[0038] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0039] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.
[0040] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.
[0041] The main solution of this application embodiment is as follows: the DDR adapter board includes gold fingers, EEPROM, slots, and IIC address conversion circuit; the EEPROM is electrically connected to the IIC address conversion circuit, the IIC address conversion circuit is electrically connected to the address bus in the IIC bus, one end of the address bus is electrically connected to the IIC address interface of the gold fingers, and the other end is electrically connected to the IIC address interface of the slot; the IIC address conversion circuit is used to convert the IIC address of the address bus to obtain the target IIC address, and write the target IIC address into the EEPROM; the EEPROM is used to store the number of insertions and removals and the remaining number of insertions and removals corresponding to the adapter board.
[0042] Currently, DDR4 (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory) UDIMM (Unbuffered Dual In-Line Memory Module) and SODIMM (Small Outline Dual In-line Memory Module) signals are compatible. However, to adapt to different application scenarios, the gold fingers and shape of DDR4 UDIMMs differ from those of SODIMMs. In SODIMM memory testing and screening, adapter boards are typically used to test SODIMMs on UDIMM testing machines, thus saving development and testing costs. General-purpose DDR4 adapter boards include gold fingers, slots, and SPD (Serial Presence Detect) devices. Since DDR4 adapter boards can only accommodate (DDR4) SODIMMs,...
[0043] Because the gold fingers and slots of the DDR4 adapter board wear down during insertion and removal, a certain number of insertions and removals can significantly affect the high-speed signal quality of DDR and may even cause test failure. Since the DDR4 adapter board cannot count the number of insertions and removals, when a SODIMM test fails, it is impossible to determine whether the failure is due to a problem with the DRAM chip or the lifespan of the gold fingers and slots of the DDR4 adapter board. This requires time and manpower to locate the problem, affecting test efficiency and quality.
[0044] Therefore, how to detect and record the lifespan of DDR4 adapter boards and improve the testing efficiency and quality of SODIMM is an urgent problem to be solved.
[0045] This application provides a solution that uses an IIC address conversion circuit to convert the IIC address of the address bus, ensuring that the IIC interface address of the EEPROM device is different from the IIC address stored in the SPD of the corresponding SODIMM under test. This distinguishes between the EEPROM and the SPD. Furthermore, the IIC address stored in the EEPROM can be used to accurately read and update the number of insertion / removal cycles and the remaining number of insertion / removal cycles corresponding to the adapter board stored in the EEPROM. The lifespan of the DDR adapter board can be determined based on the updated number of insertion / removal cycles or the updated number of remaining insertion / removal cycles, thus achieving accurate detection of the lifespan of the DDR adapter board and improving the testing efficiency and quality of SODIMMs.
[0046] Based on this, embodiments of this application provide a DDR adapter board, referring to... Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the DDR adapter board of this application.
[0047] In this embodiment of the application, the DDR adapter board includes gold fingers, EEPROM, slots, and IIC address conversion circuit 100. The DDR adapter board can be a DDR4 adapter board.
[0048] Please refer to Figure 1 The gold fingers of the DDR adapter board are inserted into the corresponding slots of the motherboard, so that the DDR adapter board is electrically connected to the motherboard through the gold fingers and the slots; the gold fingers of the SODIMM to be tested are inserted into the slots of the DDR adapter board, so that the DDR adapter board is electrically connected to the SODIMM to be tested through the slots and the gold fingers of the SODIMM to be tested, so as to realize the testing of the SODIMM to be tested on the UDIMM tester through the DDR adapter board.
[0049] The EEPROM is electrically connected to the IIC address translation circuit 100, which is electrically connected to the address bus in the IIC bus. One end of the address bus is electrically connected to the IIC address interface of the gold finger, and the other end is electrically connected to the IIC address interface of the slot. Figure 1 as well as Figure 2 As shown, the IIC address conversion circuit 100 is used to convert the IIC address of the address bus to obtain the target IIC address and write the target IIC address into the EEPROM; the EEPROM is used to store the number of times the adapter board has been plugged in and out and the remaining number of times it has been plugged in and out.
[0050] It should be noted that before using the DDR adapter board for the first time, the maximum number of times the DDR adapter board can be used and the number of times it has been plugged in and out should be written into the EEPROM of the DDR adapter board. That is, the remaining number of plugging and unplugging times stored in the EEPROM is the maximum number of times the DDR adapter board can be used. Each time the DDR adapter board is plugged in, the CPU can update the number of plugging and unplugging times and the remaining number of plugging and unplugging times in the EEPROM.
[0051] In addition, in this embodiment, the processor updates the number of insertions / removals and the remaining number of insertions / removals in the EEPROM based on the target IIC address corresponding to the EEPROM.
[0052] To accurately read the number of insertions and removals and the remaining number of insertions and removals in the EEPROM, an IIC address conversion circuit 100 converts the IIC address on the address bus to obtain the target IIC address, which is then written into the EEPROM. This ensures that the IIC address stored in the EEPROM differs from the IIC address stored in the SPD of the corresponding SODIMM being tested. The CPU can distinguish between the SPD and the EEPROM by reading the IIC address in the SPD and the IIC address in the EEPROM, thus accurately reading the number of insertions and removals and the remaining number of insertions and removals based on the target IIC address. The number of insertions and removals and the remaining number of insertions and removals are updated by incrementing the number of insertions and removals by 1 and decrementing the number of remaining insertions and removals by 1. The updated number of insertions and removals and the updated number of remaining insertions and removals are then written to the EEPROM. In other words, the number of insertions and removals and the number of remaining insertions and removals stored in the EEPROM are replaced with the updated number of insertions and removals and the updated number of remaining insertions and removals. At the same time, the lifespan of the DDR adapter board can be accurately determined based on the updated number of insertions and removals or the updated number of remaining insertions and removals, which realizes accurate detection of the lifespan of the DDR adapter board and improves the testing efficiency and quality of SODIMM.
[0053] It should be noted that after the processor reads the number of insertions and removals and the remaining number of insertions and removals from the EEPROM, it can verify the number of insertions and removals and the remaining number of insertions and removals based on the maximum number of insertions and removals of the DDR adapter board. If the maximum number of insertions and removals = the number of insertions and removals + the remaining number of insertions and removals, then the number of insertions and removals and the remaining number of insertions and removals are both normal. Otherwise, there is an error in the number of insertions and removals or the remaining number of insertions and removals. In this case, the corresponding number of insertions and removals can be calculated using the remaining number of insertions and removals, i.e., the maximum number of insertions and removals - the remaining number of insertions and removals. The maximum value between the number of insertions and removals and the maximum number of insertions and removals - the remaining number of insertions and removals is written to the EEPROM, and the remaining number of insertions and removals is updated at the same time.
[0054] In one feasible implementation, the IIC address translation circuit 100 includes an inverter, and the IIC address translation circuit 100 is electrically connected to a preset address bus of the address bus through the inverter.
[0055] It should be noted that the preset address bus in the IIC bus address bus can be appropriately selected based on the motherboard's IIC address interface. For example, the address bus corresponding to the lower 3 bits of the IIC address can be selected as the preset address bus. Figure 1 as well as Figure 2 As shown, the IIC address interfaces of the EEPROM corresponding to the preset address bus are A2, A1, and A0, and the IIC address interfaces of the motherboard are A2, A1, and A0. The IIC address interfaces of the gold fingers, slots, gold fingers of the SODIMM to be tested, and SPD of the SODIMM to be tested in the DDR adapter board are all A2, A1, and A0.
[0056] In this embodiment, the IIC address conversion circuit 100 includes an inverter. Alternatively, the inverter can be replaced with a NOT gate. The IIC address conversion circuit 100 is electrically connected to a preset address bus of the address bus via the inverter. For example... Figure 2 As shown, when the preset address bus is A2, A1, and A0 of the EEPROM's IIC address interface, one or two address buses corresponding to A2, A1, and A0 are connected to inverters. The EEPROM's address interface is electrically connected to the preset address bus of the address bus through the inverter. That is, any one address interface of the EEPROM is electrically connected to the preset address bus of the address bus through an inverter, or any two address interfaces of the EEPROM are electrically connected to the preset address bus of the address bus through inverters respectively. For example, when the motherboard sets A2, A1, and A0 to 000, the address interface corresponding to A1 is electrically connected to the corresponding preset address bus through an inverter, and the address interfaces corresponding to A2 and A0 are directly electrically connected to the corresponding preset address bus. At this time, the lower 3 bits of the EEPROM's IIC address on the DDR adapter board are 010, thus making the IIC address of the EEPROM different from that in the SPD.
[0057] It is understandable that, such as Figure 2 As shown, the three address interfaces in the EEPROM's IIC address interface can also be electrically connected to the preset address bus of the address bus through inverters. For example, the lower 3 bits of the EEPROM's IIC address interface can all be electrically connected to the preset address bus of the address bus through inverters.
[0058] In one feasible implementation, at least one address interface of the EEPROM is electrically connected to a corresponding preset address bus via the inverter, and the other address interfaces are respectively electrically connected to their respective preset address buses.
[0059] In the embodiments of this application, such as Figure 2 As shown, an inverter can be set between the EEPROM and the preset address bus. For example, when the IIC address interfaces of the EEPROM corresponding to the preset address bus are A2, A1, and A0, one address interface of the EEPROM is electrically connected to the corresponding preset address bus through an inverter, two address interfaces are electrically connected to the corresponding preset address bus through inverters respectively, or three address interfaces are electrically connected to the corresponding preset address bus through inverters respectively, and the address interfaces not connected to inverters are directly electrically connected to the corresponding preset address bus. Thus, the corresponding bit in the IIC address can be inverted through the inverter, so that the IIC address in the EEPROM is different from that in the SPD.
[0060] In one feasible implementation, the IIC address conversion circuit 100 includes a resistor; at least one address interface corresponding to a high-level preset address bus in the EEPROM's address interface is grounded through a resistor, and / or at least one address interface corresponding to a low-level preset address bus is electrically connected to a power supply through a resistor.
[0061] It should be noted that the level of the corresponding EEPROM address interface can be made different from the level of the motherboard by pulling up or pulling down the resistor. The preset address bus level includes high level and / or low level. For a high-level preset address bus, the address interface of its corresponding EEPROM can be grounded through a resistor. For a low-level preset address bus, the address interface of its corresponding EEPROM can be electrically connected to the power supply through a resistor.
[0062] In this embodiment, the address interface corresponding to a high-level preset address bus in the EEPROM's address interface is grounded through a resistor, and / or the address interface corresponding to a low-level preset address bus is electrically connected to the power supply through a resistor, while the other address interfaces are directly electrically connected to their corresponding preset address buses.
[0063] Alternatively, the address interfaces corresponding to the two high-level preset address buses in the EEPROM's address interface are grounded through resistors, or the address interfaces corresponding to the two low-level preset address buses are electrically connected to the power supply through resistors, and the other address interfaces are directly electrically connected to the corresponding preset address buses.
[0064] Alternatively, all address interfaces corresponding to the high-level preset address bus can be grounded through resistors, or all address interfaces corresponding to the low-level preset address bus can be electrically connected to the power supply through resistors.
[0065] It should be noted that, since the motherboard has multiple card slots, the IIC address conversion circuit 100 in each DDR adapter board is different in order to distinguish the EEPROM of the DDR adapter board inserted in each slot, so that the IIC address in each EEPROM is different.
[0066] Additionally, it should be noted that, as Figure 1 As shown, for different motherboards, when the IIC addresses corresponding to the preset address buses are different, a corresponding switch, such as a DIP switch, can be set for each preset address bus, along with a pull-up resistor and a pull-down resistor. Simultaneously, a selection switch can be set for each address interface of the EEPROM corresponding to the preset address bus. The selection switch can have an off state, a pull-up state, and a pull-down state. In the pull-up state, the address interface of the EEPROM corresponding to the selection switch is electrically connected to the pull-up resistor; in the pull-down state, the address interface of the EEPROM corresponding to the selection switch is electrically connected to the pull-down resistor. Therefore, for each preset address bus, the DIP switch can be turned on or off to select whether the preset address bus is directly connected to the address interface of the corresponding EEPROM. If the DIP switch is off, the level of the preset address bus can control the selection switch, so that the EEPROM address interface is electrically connected to the pull-up resistor (when the preset address bus level is high) and the EEPROM address interface is electrically connected to the pull-down resistor (when the preset address bus level is low).
[0067] like Figure 1 As shown, Figure 1 In the IIC address conversion circuit 100, the switches are DIP switches. A DIP switch on the right is in the open state, and on the left is in the closed state. The light-colored resistors in the IIC address conversion circuit 100 indicate the open state. For example, if the DIP switch corresponding to A2 is in the open state, the EEPROM's A2 address interface is electrically connected to the power supply VDDSPD through a resistor, and its ground terminal is in the open state. If the DIP switch corresponding to A1 is in the open state, the EEPROM's A2 address interface is electrically connected to the corresponding address bus through a DIP switch, and is in the open state between it and both the power supply VDDSPD and the ground terminal. If the DIP switch corresponding to A1 is in the open state, and is in the open state between it and the power supply VDDSPD, the EEPROM's A2 address interface is connected to the ground terminal through a resistor.
[0068] It is understood that the IIC address conversion circuit 100 may include an inverter and a resistor. At least one address interface of the EEPROM is electrically connected to the corresponding preset address bus through the inverter. At least one address interface of the EEPROM corresponding to the high-level preset address bus is grounded through the resistor, and / or at least one address interface corresponding to the low-level preset address bus is electrically connected to the power supply through the resistor. The other address interfaces are directly electrically connected to the corresponding preset address bus.
[0069] In this application, the IIC address of the address bus is converted by the IIC address conversion circuit 100, so that the IIC interface address of the EEPROM device is different from the IIC address stored in the SPD of the corresponding SODIMM to be tested, so as to distinguish between EEPROM and SPD. Then, the insertion and removal count and remaining insertion and removal count of the corresponding adapter board stored in EEPROM can be accurately read and updated by the IIC address stored in EEPROM. The service life of DDR adapter board is determined according to the updated insertion and removal count or the updated remaining insertion and removal count, thus realizing accurate detection of the service life of DDR adapter board and improving the testing efficiency and quality of SODIMM.
[0070] Furthermore, this application also provides a method for testing the lifespan of an adapter board, referring to... Figure 3 , Figure 3 This is a flowchart illustrating the first embodiment of the life testing method for the adapter board of this application.
[0071] In this embodiment, the lifespan detection method for the adapter board is applied to a DDR adapter board, and the lifespan detection method for the adapter board includes steps S110~S130:
[0072] Step S110: When the insertion / removal count update instruction is received, the insertion / removal count and remaining insertion / removal count corresponding to the DDR adapter board are read from the EEPROM based on the target IIC address corresponding to the EEPROM.
[0073] Step S120: Update the number of plug-in / plug-out operations and the number of remaining plug-in / plug-out operations to obtain the updated number of plug-in / plug-out operations and the updated number of remaining plug-in / plug-out operations.
[0074] Step S130: Write the updated number of plug-in / plug-out cycles and the updated number of remaining plug-in / plug-out cycles into the EEPROM.
[0075] In this embodiment, when inserting or removing the DDR adapter board, the tester can trigger an insertion / removal count update command via a corresponding button, etc. Upon receiving the insertion / removal count update command, the CPU determines the target IIC address corresponding to the EEPROM, and reads the inserted / removed count and remaining insertion / removal count corresponding to the DDR adapter board from the EEPROM based on the target IIC address. In a feasible implementation, step S110 may include steps S111~S113:
[0076] Step S111: Obtain two IIC addresses through the IIC bus, including the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be detected.
[0077] Step S112: Obtain the slave IIC address corresponding to the motherboard IIC bus, and determine the target IIC address in the EEPROM based on the slave IIC address among the two IIC addresses;
[0078] Step S113: Based on the target IIC address, read the number of times the DDR adapter board has been inserted / removed and the remaining number of times it has been inserted / removed from the EEPROM.
[0079] In this embodiment, the CPU obtains two IIC addresses through the IIC bus. The two IIC addresses include the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be detected. At the same time, it obtains the slave IIC address corresponding to the motherboard IIC bus. The slave IIC address includes the address set by the motherboard's IIC address interfaces A2, A1, and A0.
[0080] Next, the CPU compares the slave IIC address with the two IIC addresses. The IIC address that matches the slave IIC address is the one in the SPD, while the one that differs is the target IIC address in the EEPROM. This allows the CPU to accurately determine the target IIC address stored in the EEPROM. Based on this target IIC address, the CPU reads the number of insertions / removals and the remaining number of insertions / removals corresponding to the DDR adapter board from the EPROM. This enables the CPU to accurately read the EEPROM and obtain the number of insertions / removals and the remaining number of insertions / removals.
[0081] After obtaining the number of plug-in / plug-out operations and the remaining number of plug-in / plug-out operations, update the number of plug-in / plug-out operations and the remaining number of plug-in / plug-out operations to obtain the updated number of plug-in / plug-out operations and the updated number of remaining number of plug-in / plug-out operations. That is, the number of plug-in / plug-out operations is increased by 1 and the remaining number of plug-in / plug-out operations is decreased by 1.
[0082] After obtaining the updated number of insertions and removals and the updated number of remaining insertions and removals, the CPU writes the updated number of insertions and removals and the updated number of remaining insertions and removals into the EEPROM, thereby updating the number of insertions and removals and the number of remaining insertions and removals in the EEPROM. In one feasible implementation, step S130 may include steps S131~S132:
[0083] Step S131: Determine whether the updated remaining number of plug-in / plug-out cycles is greater than or equal to a preset value;
[0084] Step S132: If the updated remaining number of insertions and removals is greater than or equal to the preset value, then the updated number of insertions and removals and the updated remaining number of insertions and removals are written to the EEPROM.
[0085] In this embodiment, after obtaining the updated number of plug-in / plug-out operations and the updated number of remaining plug-in / plug-out operations, it is determined whether the updated number of remaining plug-in / plug-out operations is greater than or equal to a preset value. The preset value can be set to 1, that is, it is determined whether the updated number of remaining plug-in / plug-out operations is greater than or equal to 1.
[0086] If the updated remaining number of insertions and removals is greater than or equal to the preset value, the updated number of insertions and removals and the updated remaining number of insertions and removals are written to the EEPROM. That is, the updated number of insertions and removals and the updated remaining number of insertions and removals are written to the EEPROM through the target IIC address, so as to update the number of insertions and removals and the remaining number of insertions and removals in the EEPROM, which is to update the lifespan of the DDR adapter board.
[0087] In one feasible implementation, after step S131, the lifespan detection method for the adapter board further includes:
[0088] Step S133: If the remaining number of plug-in / plug-out cycles after the update is less than the preset value, output a prompt message indicating that the DDR adapter board has reached the maximum number of tests.
[0089] In this embodiment, if the remaining number of insertions and removals after the update is less than the preset value, that is, the remaining number of insertions and removals after the update is 0, the CPU outputs a prompt message that the DDR adapter board has reached the maximum number of tests, indicating that the lifespan of the gold fingers in the DDR adapter board has been exhausted and the DDR adapter board should be replaced as soon as possible.
[0090] The adapter board lifespan detection method provided in this embodiment reads the number of insertions / removals and the remaining number of insertions / removals corresponding to the DDR adapter board from the EEPROM based on the target IIC address corresponding to the EEPROM when a insertion / removal count update command is received. Then, it updates the number of insertions / removals and the remaining number of insertions / removals to obtain the updated number of insertions / removals and the updated number of insertions / removals. Finally, it writes the updated number of insertions / removals and the updated number of insertions / removals to the EEPROM. By reading the number of insertions / removals and the remaining number of insertions / removals in the EEPROM, the current lifespan of the DDR adapter board can be accurately determined, realizing accurate detection of the lifespan of the DDR adapter board and improving the testing efficiency and quality of SODIMM.
[0091] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the life testing method of the adapter board of this application. Any simple modifications based on this technical concept are within the protection scope of this application.
[0092] This application also provides a life testing device for an adapter board, the adapter board life testing device comprising:
[0093] The reading module is used to read the number of insertions and removals and the remaining number of insertions and removals corresponding to the DDR adapter board from the EEPROM based on the target IIC address corresponding to the EEPROM when it receives the insertion and removal count update command.
[0094] The update module is used to update the number of plug-in / plug-out operations and the remaining number of plug-in / plug-out operations, and obtain the updated number of plug-in / plug-out operations and the updated number of remaining plug-in / plug-out operations.
[0095] The write module is used to write the updated number of insertions and removals and the updated number of remaining insertions and removals into the EEPROM.
[0096] The adapter board life testing device provided in this application, employing the adapter board life testing method described in the above embodiments, can solve the technical problem of how to detect and record the lifespan of DDR4 adapter boards, thereby improving the testing efficiency and quality of SODIMMs. Compared with the prior art, the beneficial effects of the adapter board life testing device provided in this application are the same as those of the adapter board life testing method provided in the above embodiments, and other technical features in the adapter board life testing device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.
[0097] This application provides a life testing device for an adapter board. The adapter board life testing device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the adapter board life testing method in the first embodiment described above.
[0098] The following is for reference. Figure 4 This document illustrates a structural schematic diagram of a life testing device suitable for implementing the life testing of an adapter board in the embodiments of this application. The life testing device for the adapter board in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 4 The life testing device for the adapter board shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.
[0099] like Figure 4As shown, the life detection device of the adapter board may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the life detection device of the adapter board. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the life testing equipment of the adapter board to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows an adapter board life testing equipment with various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.
[0100] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.
[0101] The adapter board life testing device provided in this application, employing the adapter board life testing method described in the above embodiments, can solve the technical problem of how to detect and record the lifespan of DDR4 adapter boards, thereby improving the testing efficiency and quality of SODIMMs. Compared with the prior art, the beneficial effects of the adapter board life testing device provided in this application are the same as those of the adapter board life testing method provided in the above embodiments, and other technical features of this adapter board life testing device are the same as those disclosed in the previous embodiment method, and will not be repeated here.
[0102] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.
[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0104] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the adapter board lifetime detection method in the above embodiments.
[0105] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.
[0106] The aforementioned computer-readable storage medium may be included in the life testing equipment of the adapter board; or it may exist independently and not be assembled into the life testing equipment of the adapter board.
[0107] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the life detection device of the adapter board, the life detection device of the adapter board: upon receiving a plug-in / plug-out count update instruction, reads the plug-in / plug-out count and remaining plug-in / plug-out count corresponding to the DDR adapter board from the EEPROM based on the target IIC address corresponding to the EEPROM; updates the plug-in / plug-out count and remaining plug-in / plug-out count to obtain the updated plug-in / plug-out count and updated remaining plug-in / plug-out count; and writes the updated plug-in / plug-out count and updated remaining plug-in / plug-out count into the EEPROM.
[0108] Computer program code for performing the operations of this application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, and conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0109] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0110] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.
[0111] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described adapter board lifespan detection method. This solves the technical problem of how to detect and record the lifespan of DDR4 adapter boards, thereby improving the testing efficiency and quality of SODIMMs. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the adapter board lifespan detection method provided in the above embodiments, and will not be repeated here.
[0112] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the adapter board life detection method as described above.
[0113] The computer program product provided in this application can solve the technical problem of how to detect and record the lifespan of DDR4 adapter boards, thereby improving the testing efficiency and quality of SODIMMs. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the adapter board lifespan detection method provided in the above embodiments, and will not be repeated here.
[0114] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.
Claims
1. A DDR adapter, characterized by, The DDR adapter board includes gold fingers, EEPROM, slots, and IIC address conversion circuitry; The EEPROM is electrically connected to the IIC address conversion circuit, the IIC address conversion circuit is electrically connected to the address bus in the IIC bus, one end of the address bus is electrically connected to the IIC address interface of the gold finger, and the other end is electrically connected to the IIC address interface of the slot. The IIC address conversion circuit is used to convert the IIC address of the address bus to obtain the target IIC address and write the target IIC address into the EEPROM; The EEPROM is used to store the number of times the adapter board has been plugged in and out, as well as the remaining number of times it has been plugged in and out. The IIC address conversion circuit includes an inverter, and the address interface of the EEPROM is electrically connected to a preset address bus of the address bus through the inverter. At least one address interface of the EEPROM is electrically connected to the corresponding preset address bus through the inverter, and the other address interfaces are electrically connected to the corresponding preset address bus respectively. The processor updates the number of insertions / removals and the remaining number of insertions / removals in the EEPROM based on the target IIC address corresponding to the EEPROM.
2. The DDR adapter of claim 1, wherein, The IIC address translation circuit includes resistors; In the address interface of the EEPROM, at least one address interface corresponding to a high-level preset address bus is grounded through a resistor, and / or at least one address interface corresponding to a low-level preset address bus is electrically connected to the power supply through a resistor.
3. A method of detecting the life of an adapter plate, characterized by, The lifespan testing method for the DDR adapter board according to any one of claims 1 to 2 includes: Upon receiving a plug-in / plug-out count update command, based on the target IIC address corresponding to the EEPROM, the number of plug-in / plug-out cycles and the remaining number of plug-in / plug-out cycles corresponding to the DDR adapter board are read from the EEPROM. Update the number of plug-in / plug-out operations and the remaining number of plug-in / plug-out operations, and obtain the updated number of plug-in / plug-out operations and the updated number of remaining plug-in / plug-out operations; Write the updated number of plug-in / plug-out cycles and the updated number of remaining plug-in / plug-out cycles into the EEPROM.
4. The lifespan testing method for the adapter board as described in claim 3, characterized in that, When a plug-in / plug-out count update command is received, the step of reading the number of plug-in / plug-out operations and the remaining number of plug-in / plug-out operations corresponding to the DDR adapter board from the EEPROM based on the target IIC address corresponding to the EEPROM includes: Two IIC addresses are obtained through the IIC bus, including the target IIC address in the EEPROM and the IIC address in the SPD of the SODIMM to be tested. Obtain the slave IIC address corresponding to the motherboard IIC bus, and determine the target IIC address in the EEPROM based on the slave IIC address among the two IIC addresses; Based on the target IIC address, the number of times the DDR adapter board has been plugged in and out, as well as the remaining number of times it has been plugged in and out, are read from the EEPROM.
5. The method of claim 3 or 4, wherein The step of writing the updated number of insertions / removals and the updated number of remaining insertions / removals into the EEPROM includes: Determine whether the remaining number of plug-in / plug-out cycles after the update is greater than or equal to the preset value; If the updated remaining number of plug-in / plug-out cycles is greater than or equal to the preset value, then the updated number of plug-in / plug-out cycles and the updated remaining number of plug-in / plug-out cycles are written to the EEPROM.
6. The method of claim 5, wherein After the step of determining whether the updated remaining plug-in times is greater than or equal to the preset value, the adapter plate life detection method further comprises: If the updated remaining plug-in times is equal to the preset value, a prompt information that the DDR adapter plate has reached the maximum test times is output.
7. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program. When the computer program is executed by the processor, the steps of the adapter plate life detection method according to any one of claims 3 to 6 are implemented.