An aHB bus matrix and system on chip

Abstract

The application provides an AHB bus matrix and a system on chip, the AHB bus matrix comprising: a plurality of master modules, each master module being connected with a master device, and being used for receiving and selecting a corresponding slave module according to a target address of an access request from the corresponding master device; a plurality of slave modules, each slave module being connected with a slave device, and each master module being connected with each slave module through an on-chip interconnection network; the slave module being used for forwarding the access request to the corresponding slave device, and detecting a response time length of the corresponding slave device performing the access request; the slave module being further used for feeding back an error response to the master device initiating the access request when the response time length exceeds a preset threshold. The AHB bus matrix and the system on chip provided by the application solve the technical problem that the master device cannot perform subsequent operations when the slave device responds abnormally.

Description

Technical Field

[0001] This invention relates to the field of chips, and more particularly to an AHB bus matrix and a system-on-a-chip. Background Technology

[0002] AHB (Advanced High-performance Bus) is a high-performance bus widely used in on-chip systems to connect devices such as the CPU, memory controller, DMA controller, and various peripheral controllers. In systems with multiple masters and multiple slaves, an AHB bus matrix is ​​typically used to achieve interconnection and communication between the master and slave devices.

[0003] The existing AHB bus matrix has a significant drawback when slave devices respond abnormally. When a master device accesses a slave device with a long response time, the master device will remain in a waiting state for an extended period, leading to reduced bus efficiency. Furthermore, if a slave device malfunctions and cannot respond, the master device will continue to wait, unable to perform subsequent operations, severely impacting system reliability and real-time performance. Therefore, improvements are needed. Summary of the Invention

[0004] This invention provides an AHB bus matrix and a system-on-a-chip to solve the technical problem that the master device cannot perform subsequent operations when the slave device responds abnormally.

[0005] This invention provides an AHB bus matrix, connecting multiple master devices and multiple slave devices in an on-chip system. The AHB bus matrix includes: Multiple master control modules, each connected to a corresponding master device, are used to receive and select the corresponding slave control module according to the target address of the access request from the corresponding master device; Multiple slave control modules are provided, each connected to a corresponding slave device, and each master control module is connected to each slave control module via an on-chip interconnect network. The slave control module is used to forward the access request to the corresponding slave device and detect the response time of the corresponding slave device in executing the access request. The slave control module is also used to send an error response to the master device that initiated the access request when the response time exceeds a preset threshold.

[0006] In one embodiment of the present invention, the main control module includes: The cache unit, connected to the master device, is used to receive and cache access requests from the master device; The master control unit, connected to the cache unit, is used to select the corresponding slave control module based on the target address of the access request in the cache unit.

[0007] In one embodiment of the present invention, the slave control module includes: The slave control unit is connected to the master control unit through the on-chip interconnect network and is used to forward the access request to the corresponding slave device; wherein, when multiple master control units access the slave control unit simultaneously through the on-chip interconnect network, the slave control unit is also used to process the access requests of the corresponding master control units in sequence according to the preset master device priority; The timeout detection unit is connected between the slave control unit and the slave device. It is used to detect the response time of the corresponding slave device in executing the access request, and when the response time exceeds a preset threshold, it sends an error response to the master device that initiated the access request.

[0008] In one embodiment of the present invention, when the access request is a write request, the caching unit is used to receive and cache the write request and write data from the master device in sequence, and synchronously feed back the corresponding write response to the master device after caching each piece of write data; The cache unit is also used to pause receiving new write requests and corresponding write data from the master device when the free storage space is less than a preset threshold. The cache unit is also used to release the corresponding storage space after the main control unit has finished processing the current write request and the corresponding write data; The cache unit is also used to receive the next write request and corresponding write data from the master device after the corresponding storage space is released.

[0009] In one embodiment of the present invention, the master control unit is used to process write requests in the cache unit in sequence, and select the corresponding slave control unit according to the target address of the write request, so as to forward the write request and the corresponding write data to the selected slave control unit; The slave control unit is used to process the next write request forwarded by the master control unit after receiving a successful response from the current write request. The slave control unit is further configured to, upon receiving an error response from the current write request, suspend processing the next write request forwarded by the master control unit and send an error response back to the master device that initiated the access request.

[0010] In one embodiment of the present invention, the timeout detection unit is used to detect the response time of the slave device in executing the write request when the slave control unit forwards the received write request and the corresponding write data to the corresponding slave device; The timeout detection unit is also used to send a corresponding error response to the slave control unit when the response time exceeds a preset time. The timeout detection unit is also used to send a corresponding success response to the slave control unit when the response time does not exceed the preset time.

[0011] In one embodiment of the present invention, when the access request is a read request, the cache unit is used to receive the read request from the master device; The cache unit is also used to receive read data read by the master control unit according to the read request, read the read data to the master device that initiated the access request, and receive the next read request from the master device.

[0012] In one embodiment of the present invention, the master control unit is used to select a corresponding slave control unit according to the target address of the read request in the cache unit, so as to forward the read request to the selected slave control unit; The master control unit is also used to read the read data into the cache unit after receiving the successful response and corresponding read data from the slave control unit after processing the read request; The master control unit is also used to send an error response back to the master device that initiated the access request after receiving an error response from the slave control unit after processing the read request.

[0013] In one embodiment of the present invention, the timeout detection unit is used to detect the response time of the slave device in executing the read request when the slave control unit forwards the received read request to the corresponding slave device; The timeout detection unit is also used to send a corresponding error response to the slave control unit when the response time exceeds a preset time. The timeout detection unit is also used to send a corresponding success response to the slave control unit when the response time does not exceed the preset time, and to read the read data read from the slave device to the slave control unit.

[0014] The present invention also provides a system-on-a-chip, including an AHB bus matrix, multiple master devices, and multiple slave devices, wherein the AHB bus matrix is ​​connected between the multiple master devices and the multiple slave devices.

[0015] The beneficial effects of this invention are as follows: By introducing a response time detection and error response mechanism, the problem of master device blocking caused by abnormal response from slave devices in existing technologies is effectively solved. When the response time of a slave device executing an access request exceeds a preset threshold, the slave control module immediately sends an error response to the master device, enabling the master device to terminate waiting in a timely manner and perform error handling or subsequent operations. This avoids long-term occupation of bus resources and significantly improves bus utilization efficiency and system throughput. Simultaneously, this mechanism ensures that the master device will not be trapped in indefinite waiting when a slave device fails or responds too slowly, enhancing system reliability and real-time performance, and guaranteeing stable operation in a multi-master environment. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a schematic diagram of a system-on-a-chip provided in an embodiment of the present invention.

[0018] The reference numerals in the attached diagram are as follows: 100, Master device; 210, Buffer unit; 220, Master control unit; 230, Slave control unit; 240, Timeout detection unit; 300, Slave device. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0022] Please see Figure 1This invention discloses a system-on-a-chip (SoC) comprising an AHB bus matrix, multiple master devices 100, and multiple slave devices 300, wherein the AHB bus matrix connects the master devices 100 and the slave devices 300. The multiple devices included in the SoC may specifically be a CPU, a memory controller, a DMA controller, and various peripheral controllers. When these devices need to communicate with each other, the device initiating the access request acts as the master device 100 during the communication process, and the accessed device acts as the slave device 300. The AHB bus matrix can manage and forward all access transactions between these master devices 100 and slave devices 300, ensuring orderly communication.

[0023] Please see Figure 1 In some embodiments, the AHB bus matrix may include multiple master control modules and multiple slave control modules. Each master control module is connected to a corresponding master device 100 and is used to receive and select the corresponding slave control module according to the target address of the access request from the corresponding master device 100. Each slave control module is connected to a corresponding slave device 300, and each master control module is connected to each slave control module through an on-chip interconnect network. The slave control module is used to forward the access request to the corresponding slave device and detect the response time of the corresponding slave device 300 in executing the access request. The slave control module is also used to send an error response to the master device 100 that initiated the access request when the response time exceeds a preset threshold.

[0024] In some embodiments, the on-chip interconnect network is the core interconnect component of the AHB bus matrix, forming a global communication infrastructure that connects multiple master control modules and multiple slave control modules together. Each master control module has an independent communication path to all slave control modules. This fully connected topology ensures that any master control module, after gaining access, can directly and non-blockingly communicate with any slave control module, thus providing a physical foundation for high-concurrency, low-latency data transmission.

[0025] Please see Figure 1 In some embodiments, the master control module includes a cache unit 210 and a master control unit 220. The cache unit 210 is connected to the master device 100 and is used to receive and cache access requests from the master device 100. The master control unit 220 is correspondingly connected to the cache unit 210 and is used to select the corresponding slave control module according to the target address of the access request in the cache unit 210.

[0026] In some embodiments, the cache unit 210 serves as the front-end interface of the main control module, directly connected to the master device 100, and is responsible for receiving access requests initiated by the master device 100 and managing the cache. The main control unit 220 serves as the back-end processing core of the main control module, directly connected to the cache unit 210, and is responsible for processing requests in the cache unit 210 and forwarding them to the slave control modules.

[0027] In some embodiments, the core function of the caching unit 210 is to achieve efficient caching and flow control of access requests. When the master device 100 initiates an access request, whether it is a read request or a write request, the request is first sent to the caching unit 210.

[0028] In some embodiments, the main control unit 220 is the scheduling and routing hub of the main control module, responsible for extracting accepted access requests sequentially from the cache unit 210 and processing them.

[0029] Please see Figure 1 In some embodiments, the slave control module includes a slave control unit 230 and a timeout detection unit 240. The slave control unit 230 is connected to the master control unit 220 via an on-chip interconnect network and is used to forward access requests to the corresponding slave device 300. When multiple master control units 220 simultaneously access the slave control unit 230 via the on-chip interconnect network, the slave control unit 230 is also used to process the access requests of the corresponding master control unit 220 sequentially according to a preset master device priority. The timeout detection unit 240 is connected between the slave control unit 230 and the slave device 300 and is used to detect the response time of the corresponding slave device 300 in executing the access request. When the response time exceeds a preset threshold, it sends an error response to the master device 100 that initiated the access request.

[0030] In some embodiments, the slave control unit 230 serves as the request processing and arbitration center of the slave control module. One end of the slave control unit 230 is connected to the master control unit 220, which may access the slave device 300, via an on-chip interconnect network, while the other end connects to the slave device 300. The slave control unit 230 can receive access requests routed via the on-chip interconnect network and forward them to the corresponding slave device 300.

[0031] In some embodiments, when multiple master control units 220 attempt to access the same slave control unit 230 simultaneously via an on-chip interconnect network, access conflicts inevitably occur. To address this issue, the slave control unit 230 integrates an arbitration mechanism. This arbitration mechanism prioritizes all simultaneously arriving access requests based on a pre-defined, fixed master device priority order. The slave control unit 230 selects the access request from the master control unit 220 with the highest current priority, grants it access, and forwards the request to the slave device 300 for execution. Other simultaneously arriving, lower-priority access requests are temporarily blocked until all high-priority access transactions are completed. Only then will the slave control unit 230 re-arbitrate and select the next access request to be served. This arbitration mechanism ensures that bus resources are allocated reasonably and orderly according to a predetermined priority order in scenarios with concurrent access contention, avoiding data corruption and guaranteeing the access performance of the master device 100.

[0032] In some embodiments, the timeout detection unit 240 is a component that ensures robustness and implements error isolation. The timeout detection unit 240 is connected between the slave control unit 230 and the slave device 300, and continuously monitors the communication signals between them. The timeout detection unit 240 can accurately measure the response time of the slave device 300 in processing a single access request.

[0033] In some embodiments, when the access request is a write request, the caching unit 210 is used to receive and cache the write request and write data from the master device 100 in sequence, and synchronously send back the corresponding write response to the master device 100 after caching each piece of write data.

[0034] In some embodiments, the cache unit 210 receives and caches write requests and write data from the master device 100 in a first-in, first-out (FIFO) order. When the master device 100 initiates a write operation, the write request and the corresponding write data are transmitted to the cache unit 210. The cache unit 210 internally includes a buffer area consisting of multiple storage entries, capable of temporarily storing multiple write data simultaneously. When receiving write data, the cache unit 210 stores it in the buffer area in the order in which the write data arrives, ensuring that the order of write requests is strictly maintained.

[0035] In some embodiments, after successfully storing each piece of write data, the cache unit 210 immediately sends a corresponding write response to the master device 100. Specifically, when write data is successfully written to the cache unit 210's cache area, the cache unit 210 immediately generates and sends a write response to the master device 100, without waiting for the write data to be processed by the subsequent master control unit 220 and finally written to the target slave device 300. This immediate response mechanism allows the master device 100 to quickly escape from a single write transaction, greatly reducing the access latency of the master device 100 and improving bus utilization efficiency.

[0036] In some embodiments, the cache unit 210 is further configured to suspend receiving new write requests and corresponding write data from the master device 100 when the free storage space is less than a preset threshold.

[0037] In some embodiments, the cache unit 210 continuously monitors the free storage space of its internal cache. The cache unit 210 has a preset space threshold; when the detected free storage space is less than this preset threshold, it indicates that the cache is about to become full. At this time, the cache unit 210 sends a backpressure signal to the master device 100. This backpressure signal notifies the master device 100 to temporarily stop sending new write requests and corresponding write data, effectively preventing data loss or errors due to cache overflow and ensuring the reliability of data transmission.

[0038] In some embodiments, the cache unit 210 is further configured to release the corresponding storage space after the main control unit 220 has finished processing the current write request and the corresponding write data.

[0039] In some embodiments, the cache unit 210 releases the storage space occupied by the write request after the master control unit 220 has finished processing the current write request and the corresponding write data. When the master control unit 220 successfully forwards a write request and its data to the slave control module and finally receives a success response or timeout error response from the slave device 300, it indicates that the write transaction has been completed in the subsequent process of the cache unit 210. At this time, the cache unit 210 will mark the corresponding storage entry as free and reclaim the storage space for subsequent write operations.

[0040] In some embodiments, the cache unit 210 is further configured to receive the next write request and corresponding write data from the master device 100 after the corresponding storage space is released.

[0041] In some embodiments, after the corresponding storage space is released, that is, when there is new free space in the cache area, the cache unit 210 will actively release the backpressure state on the master device 100. Once the backpressure state is released, the cache unit 210 immediately resumes receiving the next write request and corresponding write data sent by the master device 100, thereby continuing to execute a new round of caching, response and forwarding process, ensuring the continuity of the write operation data stream and the system throughput.

[0042] In some embodiments, the master control unit 220 is used to process write requests in the cache unit 210 in sequence, and select the corresponding slave control unit 230 according to the target address of the write request, so as to forward the write request and the corresponding write data to the selected slave control unit 230.

[0043] In some embodiments, the main control unit 220 continuously monitors the cache status of the cache unit 210. Once it detects that there are received but unprocessed write requests in the cache unit 210, it extracts and processes these write requests one by one according to the order in which they entered the cache unit 210, thereby ensuring that the execution order of the write operations is completely consistent with the order initiated by the main device 100, and avoiding data consistency problems.

[0044] In some embodiments, after extracting a write request, the master control unit 220 can select the corresponding slave control unit 230 based on the target address contained in the write request. The master control unit 220 integrates address decoding logic, which parses the target address of the write request and compares it with the predefined address space range of each slave device 300. Through this address matching operation, the master control unit 220 can uniquely determine the target slave device 300 that the current write request needs to access, and thus determine the slave control unit 230 responsible for managing that slave device 300. After determining the slave control unit 230, the master control unit 220 forwards the currently processed write request and the corresponding write data read from the cache unit 210 to the selected slave control unit 230 via the on-chip interconnect network.

[0045] In some embodiments, the slave control unit 230 is used to process the next write request forwarded by the master control unit 220 after receiving a successful response from the current write request.

[0046] In some embodiments, after issuing a write request, the master control unit 220 enters a waiting-for-response state, and its subsequent operations depend on the state of the slave control unit 230. When the slave control unit 230 receives a successful response from the slave device 300, it indicates that the write request has been correctly received and executed by the slave device 300. At this time, the master control unit 220 performs two subsequent actions: first, it notifies the cache unit 210 that the write transaction has been successfully completed, and the cache unit 210 can safely release the storage space occupied by the write request and its corresponding write data; second, the master control unit 220 itself switches to processing the next sequential write request in the cache unit 210, continuing to advance the write operation pipeline.

[0047] In some embodiments, the slave control unit 230 is further configured to, upon receiving an error response from the current write request, suspend processing the next write request forwarded by the master control unit 220 and send an error response back to the master device 100 that initiated the access request.

[0048] In some embodiments, when the slave control unit 230 receives an error response from the slave device 300, it indicates that the current write request failed to be executed normally by the slave device 300. Upon receiving the error response, the master control unit 220 immediately suspends the processing flow of subsequent write requests in the cache unit 210 to prevent subsequent requests that may depend on this failed operation from continuing to execute. Simultaneously, the slave control unit 230 sends an error response to the master device 100 that initiated the write request, notifying the master device 100 that the write operation failed. This mechanism ensures that the master device 100 can be promptly informed of the fault status, thereby enabling it to take appropriate error recovery measures at the software or hardware level, rather than indefinitely waiting for a success response that will never arrive, greatly enhancing the reliability and controllability of the system.

[0049] In some embodiments, the system-on-a-chip further includes a processing module (not shown in the figure), which can be connected to all master devices 100 and all slave control units 230. When a slave control unit 230 receives an error response from the current write request, it will send the corresponding error response back to the processing module, which will then send the error response back to the corresponding master device 100.

[0050] In some embodiments, the timeout detection unit 240 is used to detect the response time of the slave device 300 in executing the write request when the slave control unit 230 forwards the received write request and the corresponding write data to the corresponding slave device 300.

[0051] In some embodiments, the timeout detection unit 240 immediately activates its monitoring function when the slave control unit 230 forwards the received write request and corresponding write data to the corresponding slave device 300. The trigger condition for the timeout detection unit 240 to operate is the detection that the hreadyout signal, which indicates a transmission ready state, is pulled low from the slave device 300. When the slave control unit 230 initiates an access and hands over control to the slave device 300, if the slave device 300 cannot immediately complete the operation due to internal processing overload, encountering an error, or experiencing a functional failure, it will indicate that it is busy and not yet ready to end the transmission by continuously keeping the hreadyout signal low. Once the timeout detection unit 240 detects that the hreadyout signal has gone low, its internal monitoring mechanism is activated.

[0052] In some embodiments, the timeout detection unit 240 includes a configurable counter for accurately measuring the time the slave device 300 remains busy, i.e., the response time. The counter begins counting from zero after the hreadyout signal goes low. The timeout detection unit 240 continuously compares the current count value with a preset duration, which represents the maximum time limit allowed for the slave device 300 to process a single operation. The counter's counting rhythm is synchronized with the bus clock to ensure the accuracy of the time measurement.

[0053] In some embodiments, the timeout detection unit 240 is further configured to provide a corresponding error response to the slave control unit 230 when the response time exceeds a preset time.

[0054] In some embodiments, when the counter value inside the timeout detection unit 240 exceeds a preset threshold, it is determined that the slave device 300 has timed out. At this time, the timeout detection unit 240 immediately takes over control of the output signal, forcibly pulling the hreadyout signal output to the slave control unit 230 high to simulate a transmission termination timing. Simultaneously, the timeout detection unit 240 drives the response signal hresp high, indicating an error response. This forced action effectively terminates the access transaction that has been stuck in a long wait. At the same time, the timeout detection unit 240 latches and records the target address of the access request that caused the timeout and generates an error response for reporting, providing crucial information for subsequent error diagnosis, logging, and possible recovery operations.

[0055] In some embodiments, the timeout detection unit 240 is further configured to send a corresponding success response to the slave control unit 230 when the response time does not exceed a preset time.

[0056] In some embodiments, if the count value has not reached a preset threshold during the counter increment process, and the slave device 300 completes the operation and pulls its hreadyout signal high again, this indicates that the operation has been completed normally. Upon detecting this situation, the timeout detection unit 240 immediately resets its internal counter to prepare for monitoring the next operation. Simultaneously, the timeout detection unit 240 allows normal signals generated by the slave device 300 (including the high hreadyout and the success hresp) to pass through and be transmitted to the slave control unit 230 without loss, i.e., providing a success response, thereby ensuring that the normal access process can be completed smoothly. Through this mechanism, the timeout detection unit 240 achieves seamless monitoring of the slave device 300's behavior, intervening only when an anomaly occurs, ensuring stable operation under both normal and abnormal conditions.

[0057] In some embodiments, when the access request is a read request, the cache unit 210 is used to receive the read request from the master device 100. The cache unit 210 is also used to receive the read data read by the master control unit 220 according to the read request, read the read data to the master device 100 that initiated the access request, and receive the next read request from the master device 100.

[0058] In some embodiments, when the access request is a read request, the cache unit 210 acts as an interface between the master device 100 and the master control unit 220, and is responsible for coordinating the initiation of the read operation and the data return process. The cache unit 210 first receives the read request from the master device 100. When the master device 100 needs to read data from the slave device 300, it generates a read request containing the target address. This read request is sent to the cache unit 210, which is directly connected to it. The cache unit 210 receives the read request and either temporarily stores it or directly notifies the master control unit 220 that a new read request is pending processing. Unlike write operations, for read requests, the cache unit 210 typically does not immediately return data to the master device 100 during the receiving phase, because valid data needs to be obtained from the target slave device 300 through subsequent stages.

[0059] In some embodiments, the cache unit 210 then enters a data waiting state, ready to receive read data from the master control unit 220 based on the read request. After receiving the read request from the cache unit 210, the master control unit 220 performs address decoding, routes the read request to the slave control unit 230 via the on-chip interconnect network, and ultimately the slave control unit 230 initiates a read operation to the slave device 300. When the slave device 300 returns read data, the data returns along the original path, via the slave control unit 230 and the on-chip interconnect network, finally reaching the master control unit 220. After obtaining the read data, the master control unit 220 transmits it back to the cache unit 210. The cache unit 210 is then responsible for receiving and temporarily holding the read data.

[0060] In some embodiments, after successfully receiving read data returned by the master control unit 220, the cache unit 210 can read the read data to the master device 100 that initiated the access request. The cache unit 210 actively drives the temporarily stored read data onto the data bus with the master device 100, accompanied by a corresponding transmission completion signal, to inform the master device 100 that the requested data is validly available. The master device 100 then samples the data and completes the read transaction. Once the data for the current read request is delivered, the cache unit 210 immediately releases the relevant resources and prepares to receive the next read request from the master device 100, thereby maintaining the continuous operation of the read operation pipeline.

[0061] In some embodiments, the master control unit 220 is configured to select the corresponding slave control unit 230 according to the target address of the read request in the cache unit 210, so as to forward the read request to the selected slave control unit 230.

[0062] In some embodiments, after receiving a read request from the cache unit 210, the master control unit 220 first performs an address resolution operation, that is, selects the corresponding slave control unit 230 based on the target address contained in the read request. After completing address decoding and selecting the slave control unit 230, the master control unit 220 accurately forwards the read request received from the cache unit 210 to the selected slave control unit 230 through the on-chip interconnect network, and starts the subsequent read data acquisition process.

[0063] In some embodiments, the master control unit 220 is further configured to read the read data into the cache unit 210 after receiving the successful response and corresponding read data from the slave control unit 230 in processing the read request.

[0064] In some embodiments, after successfully forwarding a read request, the master control unit 220 continues to wait for a response from the slave control unit 230. When the slave control unit 230 processes the read request and sends back a success response along with the corresponding read data, it indicates that the target slave device 300 has successfully completed the data reading and the data is valid. At this time, the master control unit 220 performs a data relay operation, reading the read data received from the slave control unit 230 and immediately writing or transmitting it to the cache unit 210.

[0065] In some embodiments, the master control unit 220 is further configured to send an error response to the master device 100 that initiated the access request after receiving an error response from the slave control unit 230 after processing the read request.

[0066] In some embodiments, when the master control unit 220 receives an error response from the slave control unit 230 after processing the read request, this error response typically originates from the timeout detection unit 240 in the slave control module determining that the slave device 300's response timed out, or the slave device 300 itself returning an error indication. This indicates that the read request failed to successfully obtain data from the target slave device 300. In this case, the master control unit 220 will not transmit any read data to the cache unit 210, but will directly send an error response to the master device 100 that initiated the read request. Through this operation, the master control unit 220 promptly notifies the master device 100 that the read operation has failed, enabling it to determine the subsequent process based on the error status, thereby avoiding system hangs or performance degradation caused by the master device 100 waiting for a long time without receiving read data.

[0067] In some embodiments, the timeout detection unit 240 is used to detect the response time of the slave device 300 in executing the read request when the slave control unit 230 forwards the received read request to the corresponding slave device 300.

[0068] In some embodiments, the timeout detection unit 240 immediately activates its monitoring function when the slave control unit 230 forwards the received read request to the corresponding slave device 300. Its monitoring triggering conditions and judgment mechanism are similar to those for write operations. When the slave control unit 230 sends a read request to the slave device 300, if the slave device 300 cannot immediately return data due to internal processing delays or faults, and pulls its ready signal hreadyout low to indicate it is busy, the counter inside the timeout detection unit 240 begins to increment from zero, accurately measuring the response time of the slave device 300 to this read request.

[0069] In some embodiments, the timeout detection unit 240 is further configured to provide a corresponding error response to the slave control unit 230 when the response time exceeds a preset time.

[0070] In some embodiments, the timeout detection unit 240 will send a corresponding error response to the slave control unit 230 when the response time exceeds a preset duration. When the count value of the internal counter exceeds the preset duration, the timeout detection unit 240 determines that the read operation has timed out. At this time, it will immediately intervene forcibly: forcibly pull the hreadyout signal output to the slave control unit 230 high, and simultaneously drive the response signal hresp to an error-indicating state. This operation forcibly terminates the waiting process and indicates to the slave control unit 230 that the read transaction has failed. At the same time, the timeout detection unit 240 will record the target address of this timed-out read request and generate an error response.

[0071] In some embodiments, the timeout detection unit 240 is further configured to send a corresponding success response to the slave control unit 230 when the response time does not exceed a preset time, and to read the read data read from the device 300 to the slave control unit 230.

[0072] In some embodiments, if the slave device 300 completes data reading and raises its ready signal hreadyout high before the counter reaches a preset threshold, the read operation is considered successful. The timeout detection unit 240 immediately clears its internal counter and allows all read data generated by the slave device 300 to pass normally.

[0073] In some embodiments, when the timeout detection unit 240 determines that the slave device 300 has responded with a timeout and performs a forced operation (i.e., its internal counter value exceeds a preset duration), it forcibly pulls the hreadyout signal output to the slave control unit 230 high and sets the hresp signal to an error response. The access transaction is then considered complete for the master device 100. However, at the hardware level, the slave device 300 may not immediately stop the current operation due to delays in its internal logic or state machine. Instead, it may only complete the read or write operation and set its own hreadyout signal to active after the timeout determination occurs.

[0074] In some embodiments, in this scenario, the timeout detection unit 240 continuously monitors the actual hreadyout signal status of the slave device 300. When the timeout detection unit 240 detects that the slave device 300 still pulls its hreadyout signal high after a timeout event occurs, it indicates that the slave device 300 has actually completed the original operation. Specifically, the control logic inside the timeout detection unit 240 changes its connection path, no longer forcibly outputting a high-level hreadyout signal, but instead directly transmitting the actual hreadyout signal generated by the slave device 300 to the slave control unit 230.

[0075] In some embodiments, this switch of control ensures that subsequent new access operations sent to the slave device 300 can proceed normally after the current timeout transaction. Once control is returned, the timeout detection unit 240 resumes its normal monitoring mode for subsequent access transactions, that is, it restarts counting from zero from the next access and determines whether to transmit a successful response normally or trigger the timeout protection mechanism again in the new cycle based on the actual hreadyout signal state of the slave device 300. This design ensures the self-recovery capability of the on-chip system. A temporary delay or a single timeout event of a single slave device 300 will not permanently disrupt the normal communication link between the slave device 300 and the AHB bus matrix, thereby maintaining the long-term stability and reliability of the on-chip system. Through this intelligent control management, the timeout detection unit 240 achieves a balance between error isolation and functional recovery.

[0076] As can be seen, the above solution effectively solves the problem of master device blocking caused by abnormal response from slave devices in existing technologies by introducing response time detection and error response mechanisms. When the response time of a slave device executing an access request exceeds a preset threshold, the slave control module immediately sends an error response to the master device, enabling the master device to terminate waiting in a timely manner and perform error handling or subsequent operations. This avoids the long-term occupation of bus resources and significantly improves bus utilization efficiency and system throughput. Simultaneously, this mechanism ensures that the master device will not be trapped in indefinite waiting when a slave device fails or responds too slowly, enhancing system reliability and real-time performance, and guaranteeing stable operation in a multi-master environment.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An AHB bus matrix, characterized in that, The AHB bus matrix connects multiple master devices and multiple slave devices within the system-on-a-chip, and includes: Multiple master control modules, each connected to a corresponding master device, are used to receive and select the corresponding slave control module according to the target address of the access request from the corresponding master device; Multiple slave control modules are provided, each connected to a corresponding slave device, and each master control module is connected to each slave control module via an on-chip interconnect network. The slave control module is used to forward the access request to the corresponding slave device and detect the response time of the corresponding slave device in executing the access request. The slave control module is also used to send an error response to the master device that initiated the access request when the response time exceeds a preset threshold. The main control module includes: a cache unit connected to the main device for receiving and caching access requests from the main device; and a main control unit connected to the cache unit for selecting the corresponding slave control module based on the target address of the access request in the cache unit. The slave control module includes: a slave control unit, connected to the master control unit via the on-chip interconnect network, for forwarding the access request to the corresponding slave device; and a timeout detection unit, connected between the slave control unit and the slave device, for detecting the response time of the corresponding slave device executing the access request, and feeding back an error response to the master device that initiated the access request when the response time exceeds a preset threshold. When the access request is a write request, the caching unit is used to receive and cache the write request and write data from the master device in sequence, and synchronously send back the corresponding write response to the master device after caching each piece of write data; the caching unit is also used to pause receiving new write requests and corresponding write data from the master device when the free storage space is less than a preset threshold; the caching unit is also used to release the corresponding storage space after the master control unit has finished processing the current write request and corresponding write data; the caching unit is also used to receive the next write request and corresponding write data from the master device after the corresponding storage space is released; The timeout detection unit is used to detect the response time of the slave device executing the write request when the slave control unit forwards the received write request and corresponding write data to the corresponding slave device; the timeout detection unit is also used to send a corresponding error response to the slave control unit when the response time exceeds a preset time; the timeout detection unit is also used to send a corresponding success response to the slave control unit when the response time does not exceed the preset time. The timeout detection unit is used to detect the response time of the slave device in executing the read request when the slave control unit forwards the received read request to the corresponding slave device; the timeout detection unit is also used to send a corresponding error response to the slave control unit when the response time exceeds a preset time; the timeout detection unit is also used to send a corresponding success response to the slave control unit when the response time does not exceed the preset time, and to read the read data read from the slave device to the slave control unit.

2. The AHB bus matrix according to claim 1, characterized in that, When multiple master control units simultaneously access slave control units through the on-chip interconnection network, the slave control units are also used to process the access requests of the corresponding master control units in sequence according to the preset master device priority.

3. The AHB bus matrix according to claim 1, characterized in that, The master control unit is used to process the write requests in the cache unit in sequence, and select the corresponding slave control unit according to the target address of the write request, so as to forward the write request and the corresponding write data to the selected slave control unit; The slave control unit is used to process the next write request forwarded by the master control unit after receiving a successful response from the current write request. The slave control unit is also used to, upon receiving an error response from the current write request, suspend the processing of the next write request forwarded by the master control unit and send an error response back to the master device that initiated the access request.

4. The AHB bus matrix according to claim 1, characterized in that, When the access request is a read request, the cache unit is used to receive the read request from the master device; The cache unit is also used to receive read data read by the master control unit according to the read request, read the read data to the master device that initiated the access request, and receive the next read request from the master device.

5. The AHB bus matrix according to claim 4, characterized in that, The master control unit is used to select the corresponding slave control unit according to the target address of the read request in the cache unit, so as to forward the read request to the selected slave control unit; The master control unit is also used to read the read data into the cache unit after receiving the successful response and corresponding read data from the slave control unit after processing the read request; The master control unit is also used to send an error response back to the master device that initiated the access request after receiving an error response from the slave control unit after processing the read request.

6. A system-on-a-chip, characterized in that, It includes an AHB bus matrix as described in any one of claims 1 to 5, a plurality of master devices, and a plurality of slave devices, wherein the AHB bus matrix is ​​connected between the plurality of master devices and the plurality of slave devices.

Images