基于多核加速卡的AI加速系统
By employing NOC connectivity and unidirectional pipelining communication in the multi-core hardware architecture of the large language model, the data transmission and computational division between cores are optimized, solving the problems of low utilization of computing resources and low efficiency of inter-core communication, and improving system performance and support for ultra-long text sequences.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STORAGEX TECH INC
- Filing Date
- 2025-11-03
- Publication Date
- 2026-07-17
AI Technical Summary
Existing large language models suffer from low utilization of multi-core hardware architectures, inefficient inter-core communication, difficulty in supporting computation of ultra-long text sequences, and limited overall system performance.
It adopts an architecture based on a network on-chip (NOC) to connect scalar computing cores, matrix computing cores and high-bandwidth memory, and optimizes data transmission and computing division of labor between cores through unidirectional pipelined cascaded communication and dynamic task scheduling of the computing management core.
It improves the utilization of computing resources, optimizes the efficiency of inter-core communication, enhances the support for ultra-long text sequences, reduces the consumption of wiring resources and the wiring difficulty of EDA tools, and improves the overall system performance.
Smart Images
Figure CN121365040B_ABST