An optical module

Abstract

The application discloses an optical module, and relates to the technical field of optical communication, which comprises a power supply circuit, an electrical interface circuit, a digital signal processing unit, a main control circuit, an optical transmitting assembly, an optical receiving assembly, a laser driver and a bias current driving circuit, the power supply circuit is used for providing power supply for the whole optical module, the optical receiving assembly is connected with the digital signal processing unit, the digital signal processing unit is connected with the electrical interface circuit and the main control circuit, the input end of the laser driver is connected with the digital signal processing unit, the output end of the laser driver is connected with the optical transmitting assembly, the input end of the bias current driving circuit is connected with the main control circuit, and the output end of the bias current driving circuit is connected with the laser driver. The application provides a low-power-consumption, small-package, high-speed 9.8-106.25 Gbps transmission rate optical module adopting a PAM4 modulation technology.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and in particular to an optical module. Background Technology

[0002] For future deployments of ultra-high-channel Massive MIMO, 6-7GHz band, and millimeter-wave base stations, if the number of antennas and air interface bandwidth further increase, operators will need to expand more ports and consume more fiber optic cables to cope. Port density, power consumption, and fiber resources have always been among the most important factors for base stations. Upgrading the single-channel rate from 50Gbps to 100Gbps can save 100% of ports and reduce power consumption by 25%, creating more flexibility for further increases in fronthaul bandwidth. The application of single-channel 100Gbps PAM4 modulation SFP112 small package, low power consumption, high performance, high reliability, and low cost industrial temperature optical modules in mobile fronthaul will be a challenge. Summary of the Invention

[0003] The purpose of this invention is to overcome at least one defect in the prior art and to provide an optical module.

[0004] The objective of this invention is achieved through the following scheme: This invention discloses an optical module, including a power supply circuit, an electrical interface circuit, a digital signal processing unit, a main control circuit, an optical emitting component, an optical receiving component, a laser driver, and a bias current driving circuit. The power supply circuit provides power to the entire optical module. The optical receiving component is connected to the digital signal processing unit, the digital signal processing unit is connected to the electrical interface circuit and the main control circuit, the input terminal of the laser driver is connected to the digital signal processing unit, the output terminal of the laser driver is connected to the optical emitting component, the input terminal of the bias current driving circuit is connected to the main control circuit, and the output terminal of the bias current driving circuit is connected to the optical emitting component.

[0005] In some embodiments, the power supply circuit includes a first power management circuit, a second power management circuit, and a third power management circuit. The input terminals of the first, second, and third power management circuits are connected to the output terminal of a soft-start load switch circuit. The input terminal of the soft-start load switch circuit is connected to an electrical interface circuit. The output terminal of the first power management circuit is connected to the first power input terminal of a digital signal processing unit to provide a first voltage to the digital signal processing unit. The output terminal of the second power management circuit is connected to the second power input terminal of the digital signal processing unit to provide a second voltage to the digital signal processing unit. The output terminal of the third power management circuit is connected to the power input terminal of a laser driver to provide a third voltage to the laser driver. The control terminals of the first, second, and third power management circuits are respectively connected to a main control circuit.

[0006] In some embodiments, the first power management circuit includes a first buck chip, the enable terminal of which is connected to the main control circuit; the second power management circuit includes a second buck chip, the enable terminal of which is connected to the main control circuit; and the third power management circuit includes a third buck chip, the enable terminal of which is connected to the main control circuit.

[0007] In some embodiments, the bias current driving circuit includes an operational amplifier (op-amp) and a transistor. The non-inverting input of the op-amp is connected to the output of the DAC input circuit. The input of the DAC input circuit is connected to the DAC output of the main control circuit. The inverting input of the op-amp is grounded via a first resistor. The inverting input of the op-amp is connected to the output of the op-amp via a first capacitor. The output of the op-amp is connected to the control terminal of the transistor. The first terminal of the transistor is connected to a power supply. The second terminal of the transistor is connected to the inverting input of the op-amp via a third resistor. The second terminal of the transistor is connected to the output of the bias current driving circuit. The output of the bias current driving circuit is electrically connected to the laser driver to provide a D_Bias bias current to the laser driver.

[0008] In some embodiments, a second resistor is connected in series between the second terminal of the transistor and the output terminal of the bias current drive circuit, and the output terminal of the bias current drive circuit is connected to the non-inverting input terminal of the operational amplifier via a fourth resistor.

[0009] It also includes a signal conditioning circuit, the two input terminals of which are respectively connected to the two ends of the second resistor, and the output terminal of which is connected to the main control circuit;

[0010] And / or,

[0011] The DAC input circuit includes a voltage divider network, which includes a fifth resistor and a sixth resistor. One end of the fifth resistor and one end of the sixth resistor are connected to the DAC output terminal of the main control circuit. The other end of the fifth resistor is connected to the non-inverting input terminal of the operational amplifier, and the other end of the sixth resistor is grounded.

[0012] And / or,

[0013] The DAC input circuit also includes a second capacitor, one end of which is connected to the non-inverting input terminal of the operational amplifier, and the other end of which is grounded.

[0014] And / or,

[0015] The bias current drive circuit also includes a third capacitor, one end of which is connected to the power supply and the other end of which is grounded.

[0016] And / or,

[0017] The bias current driving circuit also includes a fourth capacitor, one end of which is connected to the output terminal of the bias current driving circuit, and the other end of which is grounded.

[0018] In some embodiments, the optical module of the present invention further includes a crystal oscillator circuit for providing a reference clock for a digital signal processing unit. The crystal oscillator circuit includes an active crystal oscillator module and a crystal voltage divider circuit. The crystal voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. One end of the first voltage divider resistor is connected to a first output terminal of the active crystal oscillator module, and the other end of the first voltage divider resistor is grounded. One end of the second voltage divider resistor is connected to a second output terminal of the active crystal oscillator module, and the other end of the second voltage divider resistor is grounded. A first attenuation resistor and a first AC coupling capacitor are connected in series between the first output terminal of the active crystal oscillator module and the first reference clock pin of the digital signal processing unit. A second attenuation resistor and a second AC coupling capacitor are connected in series between the second output terminal of the active crystal oscillator module and the second reference clock pin of the digital signal processing unit.

[0019] In some embodiments, the digital signal processing unit includes a receive automatic gain control module, a receive ADC module, a receive clock data recovery circuit, a receive FFE / DFE equalization module, a receive DAC module, and a receive limiting amplifier circuit. The receive automatic gain control module is used to adjust the gain of the electrical signal output by the optical receiving component. The receive ADC module is used to perform ADC conversion on the electrical signal output by the optical receiving component. The receive clock data recovery circuit is used to recover the clock data of the electrical signal output by the optical receiving component. The receive FFE / DEF equalization module is used to perform reflection cancellation and multipath interference compensation on the electrical signal output by the optical receiving component and provide a level-dependent equalizer. The receive DAC module is used to perform DAC conversion on the electrical signal output by the optical receiving component. The receive limiting amplifier circuit is used to amplify the signal amplitude of the electrical signal output by the optical receiving component to a set value and output it to the electrical interface circuit.

[0020] The digital signal processing unit includes a transmit CTLE equalization module, a transmit ADC module, a transmit clock data recovery circuit, a transmit FFE / DFE equalization module, and a transmit DAC module. The transmit CTLE equalization module is used to compensate for the distortion of the electrical signal output by the electrical interface circuit. The transmit ADC module is used to perform ADC conversion on the electrical signal output by the electrical interface circuit. The transmit clock data recovery circuit is used to recover and shape the clock data of the electrical signal output by the electrical interface circuit. The transmit FFE / DFE equalization module is used to perform reflection cancellation and multipath interference compensation on the electrical signal output by the electrical interface circuit and provide a level-dependent equalizer. The transmit DAC module is used to perform DAC conversion on the electrical signal output by the electrical interface circuit and output it to the laser driver.

[0021] In some embodiments, the digital signal processing unit further includes an automatic gain control module for transmitting, which is used to adjust the gain of the electrical signal output by the electrical interface circuit.

[0022] In some embodiments, the transmit link of the digital signal processing unit is further provided with a transmit FIR filter module. The transmit FIR filter module is located between the transmit FFE / DFE equalization module and the transmit DAC module.

[0023] In some embodiments, the receiving link of the digital signal processing unit is further provided with a receiving FIR filtering module. The receiving FIR filtering module is located between the receiving FFE / DEF equalization module and the receiving DAC module.

[0024] In some embodiments, the digital signal processing unit further includes a high-speed transmitter serializer for converting parallel digital signals into high-speed serial signals.

[0025] In some embodiments, the digital signal processing unit further includes a high-speed serializer for converting a high-speed serial signal into a parallel digital signal.

[0026] In some embodiments, the laser driver and the optical emitting component are electrically connected by a single-ended AC coupling drive method;

[0027] And / or,

[0028] The optical receiving component and the digital signal processing unit are electrically connected via a high-speed differential AC coupling capacitor.

[0029] The laser driver and the light emitting component are electrically connected via a first flexible FPC board, and the light receiving component and the digital signal processing unit are electrically connected via a second flexible FPC board.

[0030] In some embodiments, at least one of the electrical interface circuit, digital signal processing unit, main control circuit, and laser driver and bias current drive circuit is disposed on the main PCB board. The light emitting component, light receiving component, and main PCB board are mounted between the module base and the module cover. The module base is detachably fixed with an optical port pressure block for fixing the light emitting component and the light receiving component. The light emitting component is electrically connected to the main PCB board through a first flexible FPC board, and the light receiving component is electrically connected to the main PCB board through a second flexible FPC board.

[0031] In some embodiments, the optical module of the present invention further includes a secondary PCB board, wherein a portion of the electrical interface circuit, digital signal processing unit, main control circuit, laser driver and bias current drive circuit are disposed on the secondary PCB board and another portion is disposed on the main PCB board, and the secondary PCB board and the main PCB board are connected through a third flexible FPC board.

[0032] In some embodiments, a mounting bracket for fixing the main PCB board is fixed on the module base.

[0033] The beneficial effects of this invention are as follows:

[0034] This invention provides a low-power, small-package, high-speed (9.8–106.25 Gbps) optical module using PAM4 modulation technology, which can be used in the fronthaul and midhaul of 100G Ethernet and 6th Generation wireless network base stations. This invention manages the voltage of the DSP clock recovery circuit and the 100G laser driver circuit using first, second, and third power management circuits, respectively. This ensures stable operating voltage for each chip, preventing voltage instability and transmission errors caused by external 3.3V voltage fluctuations. It also achieves low-power driving, ensuring the quality shaping and recovery of clock data signals. The output voltage of the third power management circuit, after stepping down, powers the laser driver, providing sufficient voltage to ensure the circuit operates under good bias voltage while maintaining lower power consumption.

[0035] Meanwhile, this invention adopts a low-cost driver bias current driving circuit, which is implemented by using a dual-channel small package operational amplifier and an NPN transistor. The adjustable IDAC function is achieved through the operational amplifier and high-precision resistors, with a wide output range and high accuracy. The entire circuit is simple, solving the problems of large package size and high power consumption of current IDAC chips, and saving the entire PCB layout space.

[0036] Furthermore, the external crystal oscillator voltage divider circuit used in this invention solves the problem of mismatch between the output levels of different DSPs, enabling the DSP to operate in the optimal input amplitude state, improving the clock accuracy of the entire circuit, achieving 100G signal transmission, and allowing all circuits and optical devices in the entire module to meet the requirements of the SFP112 ultra-small package. Attached Figure Description

[0037] Figure 1 A schematic block diagram of an optical module provided in one embodiment of the present invention;

[0038] Figure 2 A schematic block diagram of a digital signal processing unit provided in one embodiment of the present invention;

[0039] Figure 3A circuit diagram of a first power management circuit provided for one embodiment of the present invention;

[0040] Figure 4 A circuit diagram of a second power management circuit provided in one embodiment of the present invention;

[0041] Figure 5 A circuit diagram of a third power management circuit provided for one embodiment of the present invention;

[0042] Figure 6 A circuit diagram of a bias current driving circuit provided for one embodiment of the present invention;

[0043] Figure 7 A circuit diagram of a crystal oscillator circuit provided for one embodiment of the present invention;

[0044] Figure 8 A schematic diagram of the structure of an optical module provided in one embodiment of the present invention;

[0045] Figure 9 An exploded view of an optical module provided for one embodiment of the present invention;

[0046] Figure 10 A schematic diagram of the structure of a light emitting component provided in one embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram of the structure of an optical receiving component provided in one embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] To meet the R&D needs of next-generation 6G fronthaul wireless access optical networks for low-cost, high-speed, low-power, and small-package 100G SFP112PAM4 LR optical modules, and to address the urgent issue of insufficient transmission link budget, this research and development team has developed the first DSP digital signal processing technology-integrated high-speed, low-loss, enhanced signal integrity PCB design and excellent thermal management technology to achieve low-cost, low-power, high-reliability, small-package, and long-distance transmission. The performance meets the requirements of next-generation 6G fronthaul wireless access optical networks and relevant IEEE standards, and is capable of mass production and industrialization.

[0050] To effectively improve or even completely solve the aforementioned problems in related technologies, this disclosure provides a corresponding solution: developing an optical module that adopts PAM4 modulation, has high bandwidth, low power consumption, small package, high transmission rate of 24.33–106.25 Gbps, low cost, and high reliability, and is suitable for industrial temperature operation in 6G fronthaul.

[0051] The main research focuses on 100G products using SFP112 packaging based on DSP technology and cooled EML (or uncooled) lasers to achieve PAM signal transmission over distances of 2~10km, supporting industrial temperature applications from -40~85℃, with overall power consumption less than 3W.

[0052] This invention discloses a hot-swappable miniaturized packaged optical module for 100G SFP112 LR 10km PAM4 (4Pulse Amplitude Modulation) modulation applied to the 6G fronthaul of next-generation mobile communication. Figure 1 This is a schematic block diagram of an optical module provided in an embodiment of this disclosure. Figure 1 As shown, the optical module includes: a power supply circuit, an electrical interface circuit (gold finger circuit), a digital signal processing unit, a main control circuit, an optical emitting component, an optical receiving component, a laser driver, and a bias current driving circuit. The power supply circuit provides power to the entire optical module. The optical receiving component is connected to the digital signal processing unit, the digital signal processing unit is connected to the electrical interface circuit and the main control circuit, the input terminal of the laser driver is connected to the digital signal processing unit, the output terminal of the laser driver is connected to the optical emitting component, the input terminal of the bias current driving circuit is connected to the main control circuit, and the output terminal of the bias current driving circuit is connected to the optical emitting component.

[0053] In some embodiments, the optical module further includes an analog front-end circuit (AFE), a temperature control circuit, and an electroabsorption modulation (EA) control circuit. The analog front-end circuit (AFE) processes analog signals, while the temperature control circuit and the electroabsorption modulation (EA) control circuit are responsible for the temperature control (TEC) and electroabsorption modulation control (EA) of the EML.

[0054] In some embodiments, the power supply circuit includes a first power management circuit, a second power management circuit, and a third power management circuit. The input terminals of the first, second, and third power management circuits are connected to the output terminal of a soft-start load switch circuit. The input terminal of the soft-start load switch circuit is connected to an electrical interface circuit. The output terminal of the first power management circuit is connected to the first power input terminal of a digital signal processing unit to provide a first voltage to the digital signal processing unit. The output terminal of the second power management circuit is connected to the second power input terminal of the digital signal processing unit to provide a second voltage to the digital signal processing unit. The output terminal of the third power management circuit is connected to the power input terminal of a laser driver to provide a third voltage to the laser driver. The control terminals of the first, second, and third power management circuits are respectively connected to a main control circuit.

[0055] In some embodiments, the first power management circuit includes a first buck chip, the enable terminal of which is connected to the main control circuit; the second power management circuit includes a second buck chip, the enable terminal of which is connected to the main control circuit; and the third power management circuit includes a third buck chip, the enable terminal of which is connected to the main control circuit.

[0056] In some embodiments, the electrical interface circuit receives a 3.3V input voltage. The first power management circuit reduces the input voltage from 3.3V to 0.8V to power the phase-locked loop (PLL) circuit of the DSP clock data recovery circuit, thereby reducing the overall power consumption of the optical module. The second power management circuit reduces the input voltage from 3.3V to 1.8V to power the PLL circuit of the DSP clock data recovery circuit, further reducing the overall module power consumption and heat generation. The third power management circuit reduces the input voltage from 3.3V to 3.0V to power the laser driver, further reducing the overall module power consumption.

[0057] like Figure 3As shown, the first power management circuit includes a DC-DC step-down chip U2 and an inductor L1. The input terminal of the DC-DC step-down chip U2 is connected to one end of capacitor C3 and the first voltage input terminal (e.g., 3V3_Tree). The other end of capacitor C3 is grounded. One end of inductor L1 is connected to the SW pin of the DC-DC step-down chip U2, and the other end is connected to the voltage divider feedback resistor R7 and the filter capacitors C4 and C6, respectively. All of them are connected to the output terminal VDD_OP8 of the first power management circuit. The other end of C6 is connected to GND. The other end of resistor R7 and the other end of filter capacitor C4 are connected to the FB pin of the DC-DC step-down chip U2 and to one end of resistor R8. The other end of resistor R8 is grounded, forming a first series feedback circuit used to adjust the output voltage of the first power management circuit to 0.8V. The enable EN pin of the DC-DC step-down chip U2 is connected to the VDD_OP8_EN output pin of the main controller circuit and to one end of resistor R6. The other end of resistor R6 is grounded. The output terminal VDD_0P8 of the first power management circuit is used to power the phase-locked loop (PLL) circuit of the DSP clock data recovery circuit. The power supply ripple is required to be <5mV under a bandwidth of 100kHz.

[0058] like Figure 4 As shown, the second power management circuit includes a DC-DC step-down chip U3 and an inductor L29. The input terminal of the DC-DC step-down chip U3 is connected to one end of capacitor C7 and the first voltage input terminal (3V3_Tree), respectively. The other end of capacitor C7 is grounded. One end of inductor L29 is connected to the SW pin of the DC-DC step-down chip U3, and the other end is connected to the voltage divider feedback resistor R9 and the filter capacitors C95 and C8, respectively, and all are connected to the output terminal VDD_1P8 of the second power management circuit. The other end of capacitor C8 is connected to GND. The other ends of resistor R9 and capacitor C95 are connected to the FB pin of the DC-DC step-down chip U3, and to one end of resistor R10. The other end of resistor R10 is grounded, forming a second series feedback circuit, used to adjust the output voltage of the second power management circuit to 1.8V. The enable EN pin of the DC-DC step-down chip U3 is connected to the VDD_1P8_EN output pin of the main controller circuit and to one end of resistor R56. The other end of R56 is grounded. The output terminal VDD_1P8 of the second power management circuit is used to power the phase-locked loop (PLL) of the DSP clock data recovery circuit. The power supply ripple is required to be <15mV under a bandwidth of 100kHz.

[0059] like Figure 5As shown, the third power management circuit includes an LDO step-down chip U4. The input terminals of the LDO step-down chip U4 are connected to one end of capacitor C9 and the first voltage input terminal (3V3_Tree), respectively. The other end of capacitor C9 is grounded. The output terminal OUT of the LDO step-down chip is connected to the voltage divider feedback resistor R11 and the filter capacitor C10, both of which are connected to the output terminal VD_3P0 of the third power management circuit. The other end of capacitor C10 is connected to GND. The other end of resistor R11 is connected to the FB pin of the LDO step-down chip U4 and to one end of resistor R12. The other end of resistor R12 is grounded, forming a third series feedback circuit used to adjust the output voltage of the third power management circuit to 3.0V. The enable EN pin of the third LDO step-down chip U4 is connected to the VDD_3P0_EN output pin of the main controller circuit. The third power management circuit outputs a 3.0V voltage to drive the laser driver (LDDriver), reducing the overall heat generation of the optical module and achieving lower power consumption. At a bandwidth of 100kHz, the power supply ripple is required to be <15mV.

[0060] In some embodiments, the main control circuit includes a microcontroller (MCU). The MCU is used for ODSFP microcode control, high-frequency signal algorithm compensation programming for digital and analog circuits, and controlling the operation of the laser integrated driver circuit to implement digital diagnostics, automatic power control (APC), and automatic temperature regulation control of the TEC circuit. The MCU also controls the output amplitude and optical power of the 100Gbps high-bandwidth linear receiver detector assembly PINROSA through real-time ADC sampling and monitoring. The MCU controls the detector TIA output amplitude via a DAC, and also participates in the configuration of the entire optical module's initialization registers, controlling the power-on sequence of the first, second, and third power management circuits. The MCU is also responsible for loading the DSP microcode stored in the FLASHS flash memory into the DSP via SPI at high speed, allowing it to quickly enter normal operation and shortening the overall module startup time. Simultaneously, the MCU adjusts the TEC power chip, bias current modulation current, and laser EA modulation negative voltage control circuit in real time by sampling the module temperature and the internal temperature of the TOSA, ensuring that the entire APC and ATC (Automatic Temperature Control) circuits are in optimal working condition. This also optimizes the module's optical power and eye diagram extinction ratio, guaranteeing stable bit error rate during reception and transmission. Furthermore, it reads and reports current and optical power, as well as various status information such as LOS / LOL and SNR, from the DSP chip, laser driver chip, TOSA, and ROSA in real time and reports them to the corresponding CMIS protocol bits. It also handles real-time processing and feedback of commands issued by the host to the software protocol bits, ensuring the system operates in a highly efficient and normal transmission state.

[0061] In some embodiments, see Figure 6The bias current drive circuit includes an operational amplifier U16 and a transistor U17. The non-inverting input of the operational amplifier U16 is connected to the output of the DAC input circuit. The input of the DAC input circuit is connected to the DAC output of the main control circuit. The inverting input of the operational amplifier U16 is grounded through a resistor R69. The inverting input of the operational amplifier U16 is connected to the output of the operational amplifier U16 through a capacitor C108. The output of the operational amplifier U16 is connected to the control electrode (e.g., base) of the transistor U17 through a resistor R72. The first electrode (e.g., collector) of the transistor U17 is connected to the power supply. The second electrode (e.g., emitter) of the transistor U17 is connected to the inverting input of the operational amplifier U16 through a resistor R71. The second electrode (e.g., emitter) of the transistor U17 is connected to the output of the bias current drive circuit. The output of the bias current drive circuit is electrically connected to the laser driver to provide the laser driver with a D_Bias bias current.

[0062] In some embodiments, a resistor R67 is connected in series between the second terminal of the transistor U17 and the output terminal of the bias current drive circuit, and the output terminal of the bias current drive circuit is connected to the non-inverting input terminal of the operational amplifier U16 via a resistor R70.

[0063] In some embodiments, the optical module of the present invention further includes a signal conditioning circuit. The two input terminals of the signal conditioning circuit are respectively connected to the two ends of resistor R67, and the output terminal of the signal conditioning circuit is connected to the main control circuit. The signal conditioning circuit and resistor R67 form a current sampling circuit. The current sampling circuit is used to collect the current flowing through resistor R67, obtain the bias current output by the bias current drive circuit to the laser driver, and transmit it to the main control circuit.

[0064] The transistor emitter is connected in series with resistor R67 to directly drive the LDDriver, providing the D_Bias bias current so that the Driver operates at its optimal operating point.

[0065] The entire bias current drive circuit is implemented using a dual-channel operational amplifier and an NPN transistor. Adjustable IDAC functionality is achieved through the operational amplifier and high-precision resistors, with a load capacity of 0~320mA, far exceeding the bias voltage range of the LDDriver, enabling high-precision adjustment. The output current is calculated using the formula I = (VLD_Bias+-VLD_Bias-) / R67 = R71 / R68 / R67*VDAC_D_Bias. VDAC_D_Bias is programmable and adjustable from 0~2.5V via the DAC port of the main control circuit. Compared to multi-channel IDAC chips, the entire circuit is simpler, lower in cost, and smaller in size, reducing PCB layout space by 30%. Layout space is even more precious for a single-channel 100G SFP112 module, enabling the transmission of 100G signals in the small SFP112 package.

[0066] In some embodiments, the +VS pin of the operational amplifier U16 is connected to the LD supply voltage (such as VLD_3P3V) and connected to one end of a filter voltage C60, while the other end of the filter voltage C60 is grounded.

[0067] The collector of the transistor is connected to the LD power supply voltage (such as VLD_3P3V), which provides the operating voltage for the transistor to conduct. The collector of the transistor is connected to one end of a filter voltage C62, and the other end of the filter voltage C62 is grounded.

[0068] In some embodiments, the DAC input circuit includes a voltage divider network, which includes resistors R68 and R66. One end of resistor R68 and one end of resistor R66 are connected to the DAC output terminal of the main control circuit, the other end of resistor R68 is connected to the non-inverting input terminal of the operational amplifier, and the other end of resistor R66 is grounded.

[0069] In some embodiments, the DAC input circuit further includes a capacitor C107, one end of which is connected to the non-inverting input of the operational amplifier, and the other end of which is grounded. Capacitor C107 is a filter capacitor.

[0070] In some embodiments, the bias current driving circuit further includes a capacitor C109, one end of which is connected to the output terminal of the bias current driving circuit, and the other end of which is grounded.

[0071] In some embodiments, the optical module of the present invention further includes a crystal oscillator circuit and a FLASH flash memory circuit, which respectively provide a high-precision reference clock and a large flash memory (for fast storage of high-order software algorithms of the DSP to ensure stable and high-speed operation of the entire optical module). As a preferred embodiment, the crystal oscillator and FLASH chip are packaged in the smallest available packages, which are 1.75*2.15mm and 1.28*1.52mm respectively, so that they can be placed inside the SFP structure package. The crystal oscillator rate is 156.25MHz and the flash memory is 4Mbit to meet the high-order algorithms of the DSP.

[0072] In some embodiments, see Figure 7The crystal oscillator circuit includes an active crystal oscillator module and a crystal voltage divider circuit. The crystal voltage divider circuit includes a first voltage divider resistor R73 and a second voltage divider resistor R74. One end of the first voltage divider resistor R73 is connected to the first output terminal of the active crystal oscillator module, and the other end is grounded. One end of the second voltage divider resistor R74 is connected to the second output terminal of the active crystal oscillator module, and the other end is grounded. A first attenuation resistor R71 and a first AC coupling capacitor C32 are connected in series between the first output terminal of the active crystal oscillator module and the first reference clock pin of the digital signal processing unit. A second attenuation resistor R72 and a second AC coupling capacitor C33 are connected in series between the second output terminal of the active crystal oscillator module and the second reference clock pin of the digital signal processing unit. The first and second voltage divider resistors of the crystal voltage divider circuit are connected in parallel to ground. The output level of the crystal oscillator is adjusted by impedance division to match the input amplitude of the DSP. The output impedance of the active crystal oscillator is low (typically <50Ω), while PCB traces and DSP input capacitors can introduce parasitic inductance / capacitance, which can easily lead to signal reflection. The first and second attenuation resistors of this invention simultaneously serve the dual roles of "impedance matching" and "filtering resistors." By matching the transmission line impedance, they suppress reflections, reduce clock edge overshoot and ringing, and indirectly improve clock accuracy. The first attenuation resistor, together with the first AC coupling capacitor and the second attenuation resistor, together with the second AC coupling capacitor, form an RC filter to achieve filtering, ultimately making the clock signal input to the DSP more stable and the edges smoother.

[0073] This invention solves the problem of mismatch between the output level of different DSPs by using an external crystal oscillator voltage divider circuit, so that the DSP can work in the optimal input amplitude working state, improve the clock accuracy of the entire circuit, realize 100G signal transmission, and at the same time, enable all circuits and optical devices of the entire module to meet the SFP112 ultra-small package.

[0074] Specifically, the active crystal oscillator chip in the crystal oscillator circuit has a frequency of 156.25MHz and uses a miniaturized chip. Its pin 6 is connected to the 3.3V power supply VCC_OSC, which provides its normal operating voltage. A bypass filter capacitor C31 is connected to VCC_OSC, and the other end of C31 is connected to the power ground. Pin 1 of the active crystal oscillator enables the external MCU to operate normally and is pulled down to the power ground through a 7510K resistor. Pin 3 of the active crystal oscillator is also connected to the power ground field circuit. Pins 4 and 5 of the active crystal oscillator are connected in series with resistors R71 and R72 to one end of differential AC coupling capacitors C32 and C33, respectively. C32 and C33 are connected to the DSP chip's reference clock pins REFCLKP and REFCLKN, providing a differential reference clock for the DSP as a precise frequency reference, supplying the DSP PLL circuits with normal clock and data processing. In this circuit, to ensure the active crystal oscillator output level is within the optimal operating range of the DSP, series resistors R71 and R72 are reserved to attenuate the LVPECL level of the active crystal oscillator output. One end of R71 and R72 is also connected to pull-down resistors R74 and R73 of the matching network, respectively. The active crystal oscillator outputs a differential clock through the attenuation network, which serves as a reference for the DSP's internal clock frequency synthesizer. The DSP internally uses a differential 100Ω terminating load bias (50Ω single-ended). By adjusting the values ​​of attenuation resistors R71 and R72, the entire circuit's output LVPECL level can be kept within the DSP's required range of 0.8-1.6V. This improves circuit compatibility and suits the optimal operating amplitude required by different DSP reference clocks.

[0075] In some embodiments, see Figure 2 The receiving link of the digital signal processing unit includes a receiving automatic gain control (VGA) module, a receiving ADC module, a receiving clock data recovery (CDR) circuit, a receiving FFE / DFE equalization module, a receiving FIR filter module, a receiving DAC module, and a receiving limiting amplifier circuit. The receiving automatic gain control module includes a variable gain amplifier (VGA) for adjusting the gain of the electrical signal output by the optical receiving component. The VGA fine-tunes the input swing to adapt to the dynamic range of the ADC and achieves the optimal signal-to-noise ratio. The receiving ADC module is used to perform ADC conversion on the electrical signal output by the optical receiving component. The receiving clock data recovery (CDR) circuit includes a PLL circuit for recovering the clock data of the electrical signal output by the optical receiving component. The receiving FFE / DEF equalization module is used to perform reflection cancellation and multipath interference compensation on the electrical signal output by the optical receiving component and provide a level-dependent equalizer. The receiving limiting amplifier circuit is used to amplify the signal amplitude of electrical signals of different amplitudes received by the optical receiving component to a set value and output it to the gold finger circuit.

[0076] The transmit link of the digital signal processing unit includes a transmit CTLE equalization module, a transmit automatic gain control module, a transmit clock data recovery circuit, a transmit FFE / DFE equalization module, a transmit FIR filter module, and a transmit DAC module. The DAC module performs DAC conversion on the electrical signal output from the electrical interface circuit. The transmit CTLE equalization module compensates for distortions by adjusting the signal's frequency response, ensuring a more ideal signal quality before entering the analog-to-digital converter (ADC). The transmit automatic gain control module adjusts the gain of the electrical signal. The transmit ADC module performs ADC conversion on the electrical signal output from the electrical interface circuit. The transmit clock data recovery circuit restores and shapes the clock data of the electrical signal. The transmit FFE / DFE equalization module performs reflection cancellation and multipath interference compensation on the electrical signal output from the electrical interface circuit and provides a level-dependent equalizer. The transmit DAC module performs DAC conversion on the electrical signal output from the electrical interface circuit and outputs it to the laser driver. The PLL phase-locked loop circuit is included within the transmit and receive clock data recovery (CDR) circuits. Frequency equalization (FFE) is a linear equalization technique based on the frequency or time domain that compensates for channel distortion by adjusting the signal's frequency response (or time response). Distributed equalization (DFE) is a nonlinear equalization technique that combines the current input signal with the previous output signal (through a feedback mechanism) to eliminate intersymbol interference (ISI).

[0077] In some embodiments, the digital signal processing unit further includes an automatic gain control module for transmitting, which is used to adjust the gain of the electrical signal output by the electrical interface circuit.

[0078] In some embodiments, a transmit FIR filter module is further provided on the transmit link of the digital signal processing unit. The transmit FIR filter module is located between the transmit FFE / DFE equalization module and the transmit DAC module. In some embodiments, the transmit FIR filter module can implement a static nonlinear transfer function to enhance the signal and calibrate nonlinear effects.

[0079] In some embodiments, the receiving link of the digital signal processing unit is further provided with a receiving FIR filtering module. The receiving FIR filtering module is located between the receiving FFE / DEF equalization module and the receiving DAC module. In some embodiments, the receiving FIR filtering module can implement a static nonlinear transfer function to enhance the signal and calibrate nonlinear effects.

[0080] In some embodiments, the digital signal processing unit further includes a high-speed transmitter serializer for converting parallel digital signals into high-speed serial signals.

[0081] In some embodiments, the digital signal processing unit further includes a high-speed serializer for converting a high-speed serial signal into a parallel digital signal.

[0082] The digital signal processing unit includes a linear equalizer (CTLE), transmit and receive clock recovery (CDR) circuitry, high-speed ADC and DAC sampling circuits, transmit feedforward equalizer (FFE) and decision feedback equalizer (DFE), VGA gain control circuitry, automatic power management circuitry, microprocessor unit interface circuitry, IIC and SPI control circuitry, temperature and LOS, LOL, SNR, CID, reflection compensation detection, eye diagram scan state detection circuitry, limiting amplification circuitry, forward error correction (FEC) circuitry, spontaneous code and decoder PRBS, BER detection circuitry, etc. The CTLE adaptive equalizer has a 15dB compensation capability to compensate for losses between the SerDes and the gold finger and DSP. The transmit FIR has a 7-tap FIR function to compensate for high-speed signal losses from the DSP to the LDDriver and laser. The LDDriver also has 10dB gain adjustment to compensate for link losses or attenuation between the LDDriver and the laser. The output signal of the digital signal processing unit is amplified by the laser driver and drives the 100G miniature BOXEML laser TOSA to emit light. The laser driver and the 100G BOXEML TOSA are connected by a flexible FPC, so that the 100G laser outputs a modulated optical signal, and the optical signal rate of the laser is 9.8 to 106.25 Gbps.

[0083] In some embodiments, the digital signal processing unit employs a DSP chip. The DSP chip is externally connected to an active crystal oscillator reference clock circuit and an external large-scale FLASH memory circuit.

[0084] In some embodiments, see Figure 8 and Figure 9 The optical module of this invention includes a module base 11 and a module cover 12. At least one of the electrical interface circuit, digital signal processing unit, main control circuit, laser driver, and bias current drive circuit is disposed on a main PCB board 16. The optical emitting component 18, the optical receiving component 17, and the main PCB board 16 are mounted between the module base 11 and the module cover 12. An optical port clamping block 13 for fixing the optical emitting component 18 and the optical receiving component 17 is detachably fixed on the module base 11. The optical emitting component 18 is electrically connected to the main PCB board 16 through a first flexible FPC board 19, and the optical receiving component 17 is electrically connected to the main PCB board 16 through a second flexible FPC board 20. The optical port clamping block 13 is inverted inside 11 and 12 and is movable and detachable, allowing for free adaptation of the optical port and releasing insertion and extraction stress. EMI tape is applied inside the optical module to improve EMI performance.

[0085] In some embodiments, the optical module of the present invention further includes a secondary PCB board 15. A portion of the electrical interface circuit, digital signal processing unit, main control circuit, laser driver, and bias current drive circuit are disposed on the secondary PCB board, and another portion is disposed on the main PCB board. The secondary PCB board 15 and the main PCB board 16 are connected via a third flexible FPC board. Because it is an SFP small package, a portion of the circuitry of the present invention is placed on the main PCB board, and another portion is placed on the secondary PCB board 15. In some embodiments, the secondary PCB board is provided with a main control circuit (microprocessor controller MCU), a TEC power control chip, and a three-stage DC-DC power control circuit, etc.

[0086] In some embodiments, a mounting bracket 14 for fixing the main PCB board is fixed on the module base.

[0087] The fixing bracket 14 is snapped into the clip holes of the main PCB board 16 and the module base 11, which fixes the PCB to prevent shaking and increases the stability.

[0088] In some embodiments, the light emitting assembly includes an EML laser, an adapter, and a housing base. The adapter is connected to the housing base via an adjustment ring. The EML laser is disposed inside the housing base, and a lens is also disposed inside the housing base.

[0089] Specifically, the optical emitting component is a miniature high-bandwidth 100G laser emitting component, BOXEMLTOSA, such as... Figure 10 As shown, its internal components include a miniature LC pin connector adapter 181, a built-in small-aperture isolator 182, an adjustment ring 183, a microlens 184, an EML laser COC 185, a TEC 186, a thermistor 187, a miniature BOX housing base 188, and a backlight monitoring diode MPD 189. 186 is bonded to the cavity of the BOX housing base 188 with conductive silver paste. 185 and 187 are attached above 186, and 189 is attached to the right of 185 to monitor the EML laser backlight for real-time optical power monitoring by the MCU. 186 is connected to the PCB power chip via COB wire bonding to the BOX housing pads and then via TXFPC19 to control the laser temperature stability, ensuring the laser and DSP transmission links operate normally within the 9.8–106.25 Gbps rate range.

[0090] Specifically, the optical receiving component is the ROSA miniature high-bandwidth 100G detector receiving component, such as... Figure 11As shown, its internal components include PDTO171, a welded tube body 172, an adjustment ring 173, and a miniature pin assembly 174. PDTO171 further contains a TO cap, a high-speed transimpedance amplifier (TIA), and a high-speed backlight PD diode, all mounted inside the TO base. The PD and TIA are directly connected via gold wire bonding. The length of the gold wire and the placement of the PD directly affect the ROSA responsivity and high-frequency transmission characteristics. Furthermore, the ROSA PDTO internally contains several wire bonding capacitors to filter the TIA power supply VCC and the output amplitude control pin, eliminating power supply noise interference and ensuring excellent transmission performance. The PD is 0±30um relative to the base center, and the cap is 0±50um relative to the base center; bonding uses 25um gold wire and ball bonding technology; signal input line ① and signal output line ② do not exceed the dimensions marked in the diagram above, and the shorter the better; all ground lines should not exceed 0.16mm, and the shorter the better, to ensure that the detector and DSP receiving link operate normally within the 9.8–106.25Gbps rate range.

[0091] In some embodiments, the 100G photodetector receives an optical signal, which is amplified by TIA and then outputs an electrical signal to the DSP via RXFPC. After ADC conversion, RX automatic CTLE equalization, and AGC automatic gain adjustment, the signal is output to the DSP's receive clock recovery circuit CDR to restore the clock of the input signal and perform data shaping. After receiving and limiting amplifier circuit amplifies the signal and performs 3TAPFFE equalization (equalization capability reaches 7dB), an electrical signal of 9.8 to 106.25Gbps is output to the SerDes.

[0092] The laser driver and the optical emitting component are electrically connected via a single-ended AC coupling drive. The laser driver is located externally to the optical emitting component, enhancing heat dissipation and reducing laser power consumption, thus ensuring excellent thermal performance of the optical chip. The optical receiving component and the digital signal processing unit are electrically connected via a high-speed differential AC coupling capacitor. To obtain sufficiently good optical signal output quality, the optical receiving component and the digital signal processing unit are electrically connected via a second flexible FPC board, ensuring good signal integrity during transmission. To ensure good characteristic impedance on the transmission line, the design needs to guarantee impedance continuity at all points on the transmission line, reducing the number of discrete components. In this embodiment, the laser driver and the optical emitting component use a very simple single-ended AC coupling drive for signal driving. This method reduces discrete components on the transmission line, minimizes high-frequency signal loss and external interference, and ensures characteristic impedance continuity on the transmission line. The laser driver and the optical emitting component are electrically connected via a first flexible FPC board, enabling high-speed signal transmission of 9.8–106.25 Gbps while ensuring signal integrity across all components.

[0093] This invention provides a low-power, small-package, high-speed (9.8–106.25 Gbps) optical module using PAM4 modulation technology, which can be used in the fronthaul and midhaul of 100G Ethernet and 6th Generation wireless network base stations. This invention manages the voltage of the DSP clock recovery circuit and the 100G laser driver circuit using first, second, and third power management circuits, respectively. This ensures stable operating voltage for each chip, preventing voltage instability and transmission errors caused by external 3.3V voltage fluctuations. It also achieves low-power driving, ensuring the quality shaping and recovery of clock data signals. The output voltage of the third power management circuit, after stepping down, powers the laser driver, providing sufficient voltage to ensure the circuit operates under good bias voltage while maintaining lower power consumption.

[0094] Meanwhile, the bias current driving circuit of the present invention includes a low-cost driver bias current driving circuit, which is implemented by using a dual-channel small package operational amplifier and an NPN transistor. The adjustable IDAC function is achieved through the operational amplifier and high-precision resistors. It has a wide output range and high accuracy. The whole circuit is simple, solves the problems of large package size and high power consumption of current IDAC chips, and saves the entire PCB layout space.

[0095] Furthermore, the external crystal oscillator voltage divider circuit used in this invention solves the problem of mismatch between the output levels of different DSPs, enabling the DSP to operate in the optimal input amplitude state, improving the clock accuracy of the entire circuit, achieving 100G signal transmission, and allowing all circuits and optical devices in the entire module to meet the requirements of the SFP112 ultra-small package.

[0096] In summary, the circuit of this invention utilizes extremely small packaged chips, a 100G micro-BOX EMLTOSA, and a 100GROSA, reducing the overall PCB layout area by 30% and the overall module power consumption by 20%, while ensuring industrial-grade temperature and high-speed link transmission quality. This development achieves the localization of 6G optical transmission high-speed optical modules. Based on the chips, devices, and modules developed in this project, a comprehensive testing and analysis platform will be built to complete the localization layout of next-generation typical 6G fronthaul optical modules, achieving international leading status.

[0097] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. Applied to 6G next-generation fronthaul and Ethernet 100G SFP112LRPAM4 optical modules, it should be noted that the optical module structural design, 100G laser and 100G detector packaging, and various control circuit diagrams described above all fall within the scope of protection of this invention. The hermetically sealed packaging principle, power management control algorithms and control circuit principles, electromagnetic compatibility simulation, signal integrity simulation technology, and advanced thermal fluid analysis, magnetothermal coupling, and thermal stress management technologies used in the optical module laser and detector are protected by this patent. For those skilled in the art, various modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the scope of protection of this invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An optical module, characterized in that: It includes a power supply circuit, an electrical interface circuit, a digital signal processing unit, a main control circuit, an optical emitting component, an optical receiving component, a laser driver, and a bias current driving circuit. The power supply circuit provides power to the entire optical module. The optical receiving component is connected to the digital signal processing unit, the digital signal processing unit is connected to the electrical interface circuit and the main control circuit, the input terminal of the laser driver is connected to the digital signal processing unit, the output terminal of the laser driver is connected to the optical emitting component, the input terminal of the bias current driving circuit is connected to the main control circuit, and the output terminal of the bias current driving circuit is connected to the laser driver. The bias current drive circuit includes an operational amplifier and a transistor. The non-inverting input of the operational amplifier is connected to the output of the DAC input circuit. The input of the DAC input circuit is connected to the DAC output of the main control circuit. The inverting input of the operational amplifier is grounded through a first resistor. The inverting input of the operational amplifier is connected to the output of the operational amplifier through a first capacitor. The output of the operational amplifier is connected to the control electrode of the transistor. The first electrode of the transistor is connected to the power supply. The second electrode of the transistor is connected to the inverting input of the operational amplifier through a third resistor. The second electrode of the transistor is connected to the output of the bias current drive circuit. The output of the bias current drive circuit is electrically connected to the laser driver to provide the laser driver with a D_Bias bias current. A second resistor is connected in series between the second electrode of the transistor and the output of the bias current drive circuit. The output of the bias current drive circuit is connected to the non-inverting input of the operational amplifier through a fourth resistor. It also includes a crystal oscillator circuit for providing a reference clock for the digital signal processing unit. The crystal oscillator circuit includes an active crystal oscillator module and a crystal oscillator voltage divider circuit. The crystal oscillator voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. One end of the first voltage divider resistor is connected to a first output terminal of the active crystal oscillator module, and the other end of the first voltage divider resistor is grounded. One end of the second voltage divider resistor is connected to a second output terminal of the active crystal oscillator module, and the other end of the second voltage divider resistor is grounded. A first attenuation resistor and a first AC coupling capacitor are connected in series between the first output terminal of the active crystal oscillator module and the first reference clock pin of the digital signal processing unit. A second attenuation resistor and a second AC coupling capacitor are connected in series between the second output terminal of the active crystal oscillator module and the second reference clock pin of the digital signal processing unit.

2. The optical module according to claim 1, characterized in that: The power supply circuit includes a first power management circuit, a second power management circuit, and a third power management circuit. The input terminals of the first, second, and third power management circuits are connected to the output terminal of the soft-start load switch circuit. The input terminal of the soft-start load switch circuit is connected to the electrical interface circuit. The output terminal of the first power management circuit is connected to the first power input terminal of the digital signal processing unit to provide a first voltage to the digital signal processing unit. The output terminal of the second power management circuit is connected to the second power input terminal of the digital signal processing unit to provide a second voltage to the digital signal processing unit. The output terminal of the third power management circuit is connected to the power input terminal of the laser driver to provide a third voltage to the laser driver. The control terminals of the first, second, and third power management circuits are respectively connected to the main control circuit.

3. The optical module according to claim 2, characterized in that: The first power management circuit includes a first buck chip, the enable terminal of which is connected to the main control circuit. The second power management circuit includes a second buck chip, the enable terminal of which is connected to the main control circuit. The third power management circuit includes a third buck chip, the enable terminal of which is connected to the main control circuit.

4. The optical module according to claim 1, characterized in that: It also includes a signal conditioning circuit, the two input terminals of which are respectively connected to the two ends of the second resistor, and the output terminal of which is connected to the main control circuit; And / or, The DAC input circuit includes a voltage divider network, which includes a fifth resistor and a sixth resistor. One end of the fifth resistor and one end of the sixth resistor are connected to the DAC output terminal of the main control circuit. The other end of the fifth resistor is connected to the non-inverting input terminal of the operational amplifier, and the other end of the sixth resistor is grounded. And / or, The DAC input circuit also includes a second capacitor, one end of which is connected to the non-inverting input terminal of the operational amplifier, and the other end of which is grounded. And / or, The bias current drive circuit also includes a third capacitor, one end of which is connected to the power supply and the other end of which is grounded. And / or, The bias current driving circuit also includes a fourth capacitor, one end of which is connected to the output terminal of the bias current driving circuit, and the other end of which is grounded.

5. The optical module according to claim 1, characterized in that: The digital signal processing unit includes a receiver automatic gain control module, a receiver ADC module, a receiver clock data recovery circuit, a receiver FFE / DFE equalization module, a receiver DAC module, and a receiver limiting amplifier circuit. The receiver automatic gain control module is used to adjust the gain of the electrical signal output by the optical receiver component. The receiver ADC module is used to perform ADC conversion on the electrical signal output by the optical receiver component. The receiver clock data recovery circuit is used to recover the clock data of the electrical signal output by the optical receiver component. The receiver FFE / DEF equalization module is used to perform reflection cancellation and multipath interference compensation on the electrical signal output by the optical receiver component and provide a level-dependent equalizer. The receiver DAC module is used to perform DAC conversion on the electrical signal output by the optical receiver component. The receiver limiting amplifier circuit is used to amplify the signal amplitude of the electrical signal output by the optical receiver component to a set value and output it to the electrical interface circuit. The digital signal processing unit includes a transmit CTLE equalization module, a transmit ADC module, a transmit clock data recovery circuit, a transmit FFE / DFE equalization module, and a transmit DAC module. The transmit CTLE equalization module is used to compensate for the distortion of the electrical signal output by the electrical interface circuit. The transmit ADC module is used to perform ADC conversion on the electrical signal output by the electrical interface circuit. The transmit clock data recovery circuit is used to recover and shape the clock data of the electrical signal output by the electrical interface circuit. The transmit FFE / DFE equalization module is used to perform reflection cancellation and multipath interference compensation on the electrical signal output by the electrical interface circuit and provide a level-dependent equalizer. The transmit DAC module is used to perform DAC conversion on the electrical signal output by the electrical interface circuit and output it to the laser driver.

6. The optical module according to claim 1, characterized in that: The laser driver and the optical emitting component are electrically connected by a single-ended AC coupling drive method. And / or, The optical receiving component and the digital signal processing unit are electrically connected via a high-speed differential AC coupling capacitor.

7. The optical module according to claim 1, characterized in that: At least one of the electrical interface circuit, digital signal processing unit, main control circuit, laser driver, and bias current drive circuit is disposed on the main PCB board. The optical emitting component, optical receiving component, and main PCB board are mounted between the module base and the module cover. The module base is detachably fixed with an optical port pressure block for fixing the optical emitting component and the optical receiving component. The optical emitting component is electrically connected to the main PCB board through a first flexible FPC board, and the optical receiving component is electrically connected to the main PCB board through a second flexible FPC board.

8. The optical module according to claim 7, characterized in that: It also includes a secondary PCB board, on which a portion of the electrical interface circuit, digital signal processing unit, main control circuit, laser driver and bias current drive circuit are disposed, and another portion is disposed on the main PCB board. The secondary PCB board and the main PCB board are connected through a third flexible FPC board.

9. The optical module according to claim 7 or 8, characterized in that: The module base is fixed with a mounting bracket for fixing the main PCB board.

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