Frame synchronization method and apparatus, receiver, electronic device, and storage medium

Abstract

The application provides a frame synchronization method and device, a receiver, electronic equipment and a storage medium, and belongs to the technical field of broadband communication, and the method comprises the following steps: determining a frequency domain correlation product based on the point-by-point multiplication result of the frequency domain representation of a to-be-synchronized signal and a frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficient of a low-level synchronization code sequence and the frequency domain coefficient of a matched filter; the length of the low-level synchronization code sequence matches the parallel degree of a digital receiver; performing inverse fast Fourier transform on the frequency domain correlation product to obtain a time domain cyclic convolution sequence; determining the frame synchronization parameter of a data frame based on the time domain cyclic convolution sequence to determine the starting position of the synchronization header section of the data frame. The frequency domain reference sequence is determined by fusing the frequency domain coefficients of the matched filter and the low-level synchronization code sequence, the low-complexity sliding correlation operation is realized by adopting the frequency domain processing technology, and the hardware overhead of the multiplier and the storage resource occupied by the frame synchronization in the receiver is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of broadband communication technology, and in particular to a frame synchronization method, apparatus, receiver, electronic device, and storage medium. Background Technology

[0002] An efficient and reliable frame synchronization scheme is the cornerstone of the overall performance of a communication receiver.

[0003] Currently, in the All-Digital Parallel Receiver (APRX) architecture, a common burst frame synchronization scheme is to directly use a preset long synchronization code (e.g., an m-sequence of length 1024 or 2048) in the frequency domain to detect correlation peaks.

[0004] Specifically, by converting both the preset long synchronization code and the received signal data to the frequency domain using Fast Fourier Transform (FFT), performing point-to-point complex multiplication, and then converting them back to the time domain using Inverse Fast Fourier Transform (IFFT), the start time of the frame synchronization header is determined by searching for relevant peak values.

[0005] However, due to the need to match long synchronization codes, large-scale long-point FFT / IFFT modules and a large number of frequency domain multipliers must be used, which directly leads to huge hardware resource consumption and processing latency, which contradicts the design goal of modern communication systems that pursue low cost and low power consumption. Summary of the Invention

[0006] This invention provides a frame synchronization method, apparatus, receiver, electronic device, and storage medium to solve the defects in the prior art where frame synchronization requires matching long synchronization codes, resulting in the use of large-scale long-point FFT / IFFT modules and a large number of frequency domain multipliers, causing great hardware resource consumption and processing delay.

[0007] This invention provides a frame synchronization method, comprising: Determine the frequency domain representation of the signal to be synchronized; The frequency domain correlation product of the signal to be synchronized is determined based on the point-by-point multiplication result of the frequency domain representation and the frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched with the parallelism of the digital receiver. Perform an inverse fast Fourier transform on the frequency domain correlation product to obtain the time-domain circular convolution sequence of the signal to be synchronized; Based on the time-domain circular convolution sequence of the signal to be synchronized, the frame synchronization parameters of the data frame are determined, thereby determining the starting position of the synchronization header of the data frame.

[0008] According to a frame synchronization method provided by the present invention, the frequency domain reference sequence is determined based on the following method: The low-level synchronization code sequence is subjected to conjugate inversion, trailing zero-padding expansion, and Fast Fourier Transform to obtain its frequency domain coefficients. The time-domain matched filter coefficients of the matched filter are then subjected to trailing zero-padding expansion and Fast Fourier Transform to obtain their frequency domain coefficients. The equivalent frequency domain filter coefficients are determined based on the point-by-point multiplication of the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter. Finally, the frequency domain reference sequence is determined based on these equivalent frequency domain filter coefficients.

[0009] According to a frame synchronization method provided by the present invention, the symbols in the synchronization header of the data frame are determined based on a low-level symbol in the low-level synchronization code sequence and a high-level symbol in the high-level synchronization code sequence; the length of the high-level synchronization code sequence is matched with a preset first consecutive processing cycle number.

[0010] According to a frame synchronization method provided by the present invention, determining the frame synchronization parameters of a data frame based on the temporal circular convolution sequence of the signal to be synchronized includes: determining parallel valid data of the signal to be synchronized without circular aliasing based on the temporal circular convolution sequence; and performing frame synchronization processing on the parallel valid data to obtain the frame synchronization parameters of the data frame.

[0011] According to a frame synchronization method provided by the present invention, the step of performing frame synchronization processing on the parallel valid data to obtain the frame synchronization parameters of the data frame includes: performing coarse synchronization processing on the parallel valid data to obtain a coarse timing clock index and an optimal parallel branch index; determining a target baseband data segment of a target clock processing cycle from the parallel baseband data of the signal to be synchronized based on the coarse timing clock index; determining a target branch data segment of a target branch from the target baseband data segment based on the optimal parallel branch index; and performing fine synchronization processing on the target branch data segment to obtain a fine timing clock index.

[0012] According to a frame synchronization method provided by the present invention, the coarse synchronization processing of the parallel valid data to obtain a coarse timing clock index and an optimal parallel branch index includes: for each valid data path in the parallel valid data, performing square-law detection on each valid data path to obtain the instantaneous power value of each valid data path; for each valid data path, summing and accumulating the latest instantaneous power value of the cumulative length according to a sliding step size to obtain the cumulative power value of each valid data path; the sliding step size is determined based on a first continuous processing cycle number; the cumulative length is determined based on a preset second continuous processing cycle number; the second continuous processing cycle number is greater than or equal to twice the first continuous processing cycle number; performing peak search on the cumulative power value of each valid data path to determine a target peak value exceeding a preset threshold; and determining the coarse timing clock index and the optimal parallel branch index based on the target peak value.

[0013] According to a frame synchronization method provided by the present invention, the step of performing fine synchronization processing on the target branch data segment to obtain a fine timing clock index includes: sending the target branch data segment into multiple frequency slots respectively; for each frequency slot, performing digital mixing on the target branch data segment according to a preset assumed frequency of each frequency slot to obtain the mixing output data of each frequency slot; for each frequency slot, determining the frequency slot decision value of each frequency slot based on the coherent cumulative energy of each data sub-segment of the target branch data segment in each frequency slot; constructing a two-dimensional decision matrix based on the frequency slot decision values ​​of multiple frequency slots within a decision period; the decision period being determined based on the number of second consecutive processing cycles; searching for the maximum peak value in the two-dimensional decision matrix, and determining the fine timing clock index based on the processing clock coordinate value of the coordinates corresponding to the maximum peak value.

[0014] According to a frame synchronization method provided by the present invention, after searching for the maximum peak value in the two-dimensional decision matrix, the method further includes: determining a coarse frequency offset estimate based on the frequency slot index coordinate value of the coordinates corresponding to the maximum peak value.

[0015] According to a frame synchronization method provided by the present invention, determining the frequency domain representation of the signal to be synchronized includes: performing orthogonal downconversion on the signal to be synchronized to obtain a zero-IF analog baseband signal; sampling and quantizing the analog baseband signal according to a preset sampling rate to obtain parallel baseband data; determining overlapping data blocks based on the parallel baseband data of the current period and the retained baseband data of the previous period; and performing a fast Fourier transform on the overlapping data blocks to obtain the frequency domain representation. The step of determining the parallel effective data of the signal to be synchronized without cyclic aliasing based on the time-domain circular convolution sequence includes: extracting the parallel effective data without cyclic aliasing from the time-domain circular convolution sequence according to the parallelism of the digital receiver.

[0016] The present invention also provides a frame synchronization device, comprising: The frequency domain representation acquisition module is used to determine the frequency domain representation of the signal to be synchronized; A matched filtering module is used to determine the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation and the frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched with the parallelism of the digital receiver. The inverse fast Fourier transform module is used to perform an inverse fast Fourier transform on the frequency domain correlation product to obtain the time domain circular convolution sequence of the signal to be synchronized. The frame synchronization parameter acquisition module is used to determine the frame synchronization parameters of the data frame based on the time-domain circular convolution sequence of the signal to be synchronized, so as to determine the starting position of the synchronization header of the data frame.

[0017] The present invention also provides a receiver, comprising: any of the frame synchronization devices described above.

[0018] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement any of the frame synchronization methods described above.

[0019] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the frame synchronization method as described above.

[0020] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the frame synchronization methods described above.

[0021] The frame synchronization method, apparatus, receiver, electronic device, and storage medium provided by this invention determine the frequency domain reference sequence by fusing the frequency domain coefficients of the matched filter and the frequency domain coefficients of the low-level synchronization code sequence. It employs frequency domain processing techniques to achieve low-complexity matched filtering and low-level code sliding correlation operations. Specifically, it determines the frequency domain correlation product of the signal to be synchronized based on the point-by-point multiplication result of the frequency domain representation of the signal to be synchronized and the frequency domain reference sequence. This allows frame synchronization under the APRX architecture to simultaneously complete matched filtering and low-level code cyclic correlation in the frequency domain, significantly reducing the hardware resources occupied by frame synchronization in the receiver, especially significantly reducing multiplier and storage resource overhead. This greatly reduces processing complexity and processing latency, improves the receiver's real-time processing capabilities, and is particularly beneficial for processing high-speed parallel signals. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is one of the flowcharts illustrating the frame synchronization method provided by this invention.

[0024] Figure 2 This is a schematic diagram of the structure of the data frame provided by the present invention.

[0025] Figure 3 This is the second flowchart of the frame synchronization method provided by the present invention.

[0026] Figure 4 This is a diagram showing the effect before and after coarse synchronization incoherent accumulation provided by the present invention.

[0027] Figure 5 This is an example diagram of the two-dimensional decision matrix provided by the present invention.

[0028] Figure 6 This is a simulation result diagram of the frame synchronization method provided by the present invention.

[0029] Figure 7 This is a schematic diagram of the frame synchronization device provided by the present invention.

[0030] Figure 8 This is a schematic diagram of the receiver provided by the present invention.

[0031] Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0033] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0034] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0035] The following is combined Figures 1-9 This invention describes the frame synchronization method, apparatus, receiver, electronic device, and storage medium provided by the present invention.

[0036] With the explosive growth of global communication traffic, the frequency bands and speeds of communication systems are also constantly increasing. In high-speed broadband communication applications such as low-Earth orbit satellite internet and 5G / 6G mobile communication, unprecedented challenges are being placed on the high-speed and efficient signal processing capabilities of communication receivers. To meet the needs of multi-channel parallel demodulation of high-speed broadband signals, the academic and industrial communities have proposed and extensively studied the APRX architecture. The core idea of ​​the APRX architecture is to utilize the equivalence property of time-domain circular convolution and frequency-domain multiplication to replace the large number of complex multiply-accumulate units in the traditional time-domain polyphase filter bank with a set of multipliers in the frequency domain, thereby greatly simplifying the hardware structure and significantly saving logic resource overhead.

[0037] When processing high-speed burst signals, frame synchronization is the primary and crucial step in the receiver's signal processing flow. The receiver must first accurately capture the start position of the synchronization header segment of each burst data frame by detecting a preset synchronization sequence. Only after accurate frame synchronization is achieved can the subsequent carrier synchronization module accurately extract pilot band information, thereby estimating and compensating for Doppler frequency offset and phase deviation, ultimately ensuring that user data can be correctly demodulated. Therefore, an efficient and reliable frame synchronization scheme is the cornerstone of the entire communication receiver's performance.

[0038] Figure 1 This is one of the flowcharts illustrating the frame synchronization method provided by the present invention, such as... Figure 1 As shown, the frame synchronization method includes, but is not limited to, steps 101 to 104.

[0039] It should be noted that the execution subject of the frame synchronization method provided by the present invention is the corresponding frame synchronization device, which can be a receiver, digital receiver, server and computer equipment, such as mobile phones, tablet computers, laptops, handheld computers, vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks or personal digital assistants (PDAs), etc.

[0040] Step 101: Determine the frequency domain representation of the signal to be synchronized.

[0041] The signal to be synchronized is the intermediate frequency analog signal received by the front-end module of the digital receiver.

[0042] Specifically, after receiving the signal to be synchronized, the front-end module of the digital receiver performs operations such as quadrature down-conversion, analog-to-digital conversion, overlap-save, and FFT to obtain the frequency domain representation of the signal to be synchronized. .

[0043] Step 102: Based on the point-by-point multiplication result of the frequency domain representation and the frequency domain reference sequence, determine the frequency domain correlation product of the signal to be synchronized.

[0044] The frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched to the parallelism of the digital receiver.

[0045] The frequency domain reference sequence is a sequence used to perform frequency domain multiplication of the frequency domain representation of the signal to be synchronized. It is pre-calculated and stored in the system, and its length is the same as the number of FFT points in the frequency domain representation during time-frequency conversion.

[0046] The low-level synchronization code sequence has a length that is related to the parallelism of the digital receiver. A matching sequence. Generally, the length of the low-level synchronization code sequence is equal to the parallelism of the digital receiver. The value, the low-level synchronization code sequence includes a number of parallelisms of the digital receiver. The low-level code elements.

[0047] In other words, the low-level synchronization code sequence is mapped to a spatial dimension, and its individual code element Corresponding to parallel processing by the receiver within a single processing cycle One data branch.

[0048] Optionally, the length of the low-level synchronization code sequence Based on its base sequence length and system oversampling factor Determined to precisely match the parallelism of the receiver.

[0049] Optionally, the low-level synchronization code sequence is a sequence with good autocorrelation properties.

[0050] For example, the low-level synchronization code sequence is determined based on the ZC (Zadoff-Chu) sequence, denoted as... .

[0051] Optionally, the parallelism of the receiver The preset sampling rate of the analog-to-digital converter (ADC) and processing clock A joint decision.

[0052] For example, .

[0053] Specifically, before performing frame synchronization of the signal to be synchronized, the parallelism of the receiver is pre-defined. Determine the low-level synchronization code sequence According to the low-level synchronization code sequence Frequency domain coefficients and matched filter The frequency domain coefficients are predetermined by the frequency domain reference sequence. and store frequency domain reference sequences. .

[0054] When performing frame synchronization of the signal to be synchronized, the frequency domain representation of the signal to be synchronized is used. With pre-stored, length is frequency domain reference sequence The pointwise complex multiplication is performed, and the resulting pointwise multiplication is determined as the frequency domain correlation product of the signal to be synchronized. .

[0055] Frequency domain representation With frequency domain reference sequence The pointwise multiplication result is equivalent to a circular convolution in the time domain, and the mathematical expression for this process is as follows: ; in, It is the frequency domain correlation product; Represented in the frequency domain; For frequency domain reference sequence; This is a point-by-point multiplication operation.

[0056] Optionally, the frequency domain reference sequence is determined based on the point-by-point multiplication of the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter.

[0057] Step 103: Perform an inverse fast Fourier transform on the frequency domain correlation product to obtain the time domain circular convolution sequence of the signal to be synchronized.

[0058] Specifically, frequency domain correlation product Sent to a The point IFFT processing module performs Fast Inverse Fourier Transform (IFFT) processing, converting the frequency domain correlation product... Transforming back to the time domain yields the time-domain circular convolution sequence of the signal to be synchronized. .

[0059] Step 104: Based on the time-domain circular convolution sequence of the signal to be synchronized, determine the frame synchronization parameters of the data frame, so as to determine the starting position of the synchronization header of the data frame.

[0060] Figure 2 This is a schematic diagram of the structure of the data frame provided by the present invention, as shown below. Figure 2 As shown, in general, the physical layer data frame consists of a synchronization header, a modulation and coding mode indicator, and a data symbol segment in sequence. Frame synchronization mainly involves processing the synchronization header of the data frame.

[0061] Specifically, after obtaining the time-domain circular convolution sequence of the signal to be synchronized, coarse synchronization and fine synchronization operations are performed on the time-domain circular convolution sequence to obtain the frame synchronization parameters of the data frame. Then, the starting position of the synchronization header of the data frame is determined based on the frame synchronization parameters of the data frame.

[0062] For example, based on the frame synchronization parameters, the starting sampling point index of the pseudo-noise code (PN code) in the synchronization header can be determined.

[0063] In the field of high-speed broadband communication, the FPGA clock used in hardware implementation can only be stabilized at 100MHz~200MHz. When processing high-speed, high-bandwidth signals (such as 800MHz), multiple data streams need to be processed in parallel within a single clock cycle.

[0064] At this point, if the algorithm is not designed properly, for example, if the same approach as low-speed communication is adopted, and matched filtering and sliding correlation operations of low-level synchronization codes are performed in the time domain, it will involve double convolution operations of parallel signals, namely one matched filtering and one low-level code correlation operation, resulting in high computational complexity and huge hardware resource consumption of FPGA.

[0065] The frame synchronization method provided by this invention determines the frequency domain reference sequence by fusing the frequency domain coefficients of the matched filter and the frequency domain coefficients of the low-level synchronization code sequence. It then employs frequency domain processing techniques to achieve low-complexity matched filtering and low-level code sliding correlation operations. Specifically, it determines the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation of the signal to be synchronized and the frequency domain reference sequence. This allows frame synchronization under the APRX architecture to simultaneously complete matched filtering and low-level code cyclic correlation in the frequency domain, significantly reducing the hardware resources occupied by frame synchronization in the receiver, especially the multiplier and storage resource overhead. This greatly reduces processing complexity and processing latency, improves the real-time processing capability of the receiver, and is particularly beneficial for processing high-speed parallel signals.

[0066] Based on the above embodiments, as an optional embodiment, the frequency domain reference sequence is determined in the following manner: The low-level synchronization code sequence is subjected to conjugate inversion, tail zero-padding expansion, and fast Fourier transform to obtain the frequency domain coefficients of the low-level synchronization code sequence. The time-domain matched filter coefficients of the matched filter are subjected to tail-padding expansion and fast Fourier transform processing to obtain the frequency-domain coefficients of the matched filter. The equivalent frequency domain filtering coefficients are determined based on the point-by-point multiplication of the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter. The frequency domain reference sequence is determined based on the frequency domain equivalent filtering coefficients.

[0067] Specifically, on the one hand, the length is The low-level synchronization code sequence is conjugate inverted to obtain... Then, zeros are added to the tail to extend it to... After clicking, proceed Pointed FFT operation is performed to obtain the frequency domain coefficients of the low-level synchronization code sequence. .in, Greater than .

[0068] On the other hand, the length is Time-domain matched filter coefficients To extend the tail by padding to zero After clicking, proceed Point FFT operation yields the frequency domain coefficients of the matched filter. .

[0069] The time-domain matched filter coefficients and frequency-domain matched filter coefficients are multiplied point-by-point, and the result of this point-by-point multiplication is used as the frequency-domain equivalent filter coefficients. .in, The operator represents pointwise multiplication.

[0070] Finally, the frequency-domain equivalent filter coefficients are directly used as the frequency-domain reference sequence. Alternatively, when the matched filter is a low-pass filter, to save multiplier overhead, the frequency-domain equivalent filter coefficients are... By setting each high-frequency coefficient to zero, the final frequency domain reference sequence is obtained. .in, This represents the system oversampling factor.

[0071] The frame synchronization method provided by this invention obtains the frequency domain coefficients of the low-level synchronization code sequence by performing conjugate inversion, zero-padding, and fast FFT transformation on the low-level synchronization code sequence. Simultaneously, it obtains the frequency domain coefficients of the matched filter by performing zero-padding and fast FFT transformation on the time-domain matched filter coefficients. Based on the point-by-point multiplication of the frequency domain coefficients of the low-level synchronization code sequence and the matched filter coefficients, the equivalent frequency domain filter coefficients are determined, thereby establishing the frequency domain reference sequence. This lays the foundation for achieving low-complexity matched filtering and low-level code sliding correlation operations using frequency domain processing techniques. It enables frame synchronization under the APRX architecture to simultaneously perform matched filtering and low-level code cyclic correlation in the frequency domain, significantly reducing the multiplier and storage resource overhead of frame synchronization in the receiver, greatly reducing processing complexity and latency, and improving the receiver's real-time processing capabilities.

[0072] Based on the above embodiments, as an optional embodiment, the symbols in the synchronization header of the data frame are determined based on a low-level symbol in the low-level synchronization code sequence and a high-level symbol in the high-level synchronization code sequence. The length of the advanced synchronization code sequence is matched with the preset number of first consecutive processing cycles.

[0073] The advanced synchronization code sequence is of length equal to the preset number of first consecutive processing cycles. A matching sequence. Generally, the length of the advanced synchronization code sequence is equal to the preset number of the first consecutive processing cycles. The advanced synchronization code sequence includes a number equal to the number of the first consecutive processing cycles. Advanced code elements.

[0074] Alternatively, the advanced synchronization code sequence is a binary pseudo-random sequence.

[0075] For example, the advanced synchronization code sequence is determined based on the m-sequence, denoted as... .

[0076] Specifically, in combination Figure 2 As shown, the synchronization header of the data frame adopts a two-dimensional hierarchical structure, consisting of a length equal to the parallelism of the digital receiver. The low-level synchronization code sequence and its length are the preset number of the first consecutive processing cycles. It is composed of high-level synchronization code sequences, and its total length is [missing information]. equal and The product of.

[0077] The two-dimensional structure of the synchronization header of a data frame and the receiver The parallel processing architecture (APRX architecture) is tightly coupled. Specifically, the two-dimensional structure of the synchronization header can be logically regarded as a... OK A matrix of columns.

[0078] When the low-level synchronization code sequence is mapped to a spatial dimension, its individual code element Corresponding to parallel processing by the receiver within a single processing cycle One data branch; when the high-level synchronization code sequence is mapped to the time dimension, its individual code element Corresponding to continuous One processing cycle.

[0079] Therefore, any symbol in the synchronization header of the data frame Both are determined based on a low-level symbol from a low-level synchronization code sequence and a high-level symbol from a high-level synchronization code sequence.

[0080] For example, any symbol It is generated by multiplication of a low-level symbol from a low-level synchronization code sequence and a high-level symbol from a high-level synchronization code sequence.

[0081] Furthermore, any two symbols in the synchronization header Different, used to identify different symbols The low-level symbols and / or high-level symbols are different. The symbols in the synchronization header segment... The total number is the product of the number of low-level symbols in the low-level synchronization code sequence and the number of high-level symbols in the high-level synchronization code sequence, which is also the product of the preset number of the first consecutive processing cycles and the parallelism of the receiver.

[0082] Furthermore, if the two-dimensional structure of the synchronization header of a data frame is expanded into a one-dimensional time-domain sequence, then the first... Each symbol can be represented as: in .

[0083] The frame synchronization method provided by this invention employs a two-dimensional layered structure in the synchronization header of the data frame. This ensures that each symbol in the synchronization header is determined based on a low-level symbol in the low-level synchronization code sequence and a high-level symbol in the high-level synchronization code sequence. Furthermore, the length of the low-level synchronization code sequence matches the parallelism of the receiver, and the length of the high-level synchronization code sequence matches the preset number of first consecutive processing cycles. This structural design allows the receiver to perform fast correlation acquisition using the low-level code while simultaneously performing subsequent fine synchronization processing using the structure of the high-level code, thus forming the signal basis of the two-level frame synchronization method of this invention.

[0084] Based on the above embodiments, as an optional embodiment, determining the frame synchronization parameters of the data frame based on the temporal circular convolution sequence of the signal to be synchronized includes: Based on the time-domain circular convolution sequence, determine the parallel valid data of the signal to be synchronized without circular aliasing; The parallel valid data is subjected to frame synchronization processing to obtain the frame synchronization parameters of the data frame.

[0085] The length of the parallel effective data is the same as the parallelism of the receiver.

[0086] Specifically, if the frequency domain representation of the signal to be synchronized is obtained after overlap preservation, then after obtaining the time-domain circular convolution sequence of the signal to be synchronized, the non-circularly aliased portion of the signal to be synchronized, with the same length as the parallelism of the receiver, is determined from the time-domain circular convolution sequence. Parallel effective data .

[0087] use Parallel effective data Frame synchronization processing is performed to obtain the frame synchronization parameters of the data frame, thereby determining the starting position of the synchronization header segment of the data frame.

[0088] Optionally, the frame synchronization device includes a data processor and a frame synchronization RAM (Random Access Memory); the parallel valid data is obtained based on parallel baseband data processed by the data selector; the frame synchronization processing of the parallel valid data to obtain the frame synchronization parameters of the data frame includes: The parallel valid data is subjected to coarse synchronization processing to obtain coarse synchronization parameters; Based on the coarse synchronization parameters, the target branch data segment is extracted from the frame synchronization RAM; The target branch data segment is subjected to fine synchronization processing to obtain fine synchronization parameters.

[0089] Among them, the data selector acts as a state control switch, and its output is dynamically switched according to the stage of the frame synchronization process to ensure that subsequent processing modules (such as the overlap retention module) receive the correct data stream; the core function of the frame synchronization RAM is to provide data backtracking capability for the second-level fine synchronization.

[0090] Specifically, the front-end module of the digital receiver performs quadrature down-conversion and analog-to-digital conversion on the received signal to be synchronized, and outputs... Parallel baseband data. The parallel baseband data stream is split into two paths, which are sent to the data selector and the frame synchronization RAM, respectively.

[0091] In each processing cycle, Parallel baseband data is written to frame synchronization RAM, and its write address pointer is incremented sequentially to form a continuous data history.

[0092] Frame synchronization processing includes a first-stage coarse synchronization phase and a second-stage fine synchronization phase. In the first-stage coarse synchronization phase, the receiver continuously searches for the synchronization header segment; at this time, the data selector selects the value directly output by the ADC. Parallel baseband data is sent to subsequent modules for processing to obtain... Parallel and effective data. For The parallel valid data is coarsely synchronized, and coarse synchronization parameters indicating the suspected synchronization head position are detected.

[0093] The data selector switches the data source and reads the target branch data segment, including the suspected synchronization header position, back from the frame synchronization RAM based on the coarse synchronization parameters. In other words, the read address of the frame synchronization RAM is controlled according to the coarse synchronization parameter results of the first-level coarse synchronization to achieve accurate reading of data within a specific time window.

[0094] Further, the suspected synchronization header position is precisely verified through the second-level fine synchronization stage, that is, the target branch data segment is finely synchronized to obtain fine synchronization parameters, so as to determine the starting position of the synchronization header segment of the data frame based on the coarse synchronization parameters and the fine synchronization parameters.

[0095] The frame synchronization method provided by this invention, through the joint design of a data selector and a frame synchronization RAM, allows the data selector to switch data sources according to the frame synchronization stage status, and the frame synchronization RAM to provide data backtracking capability for the second-level fine synchronization. This enables the retention of key data for accurate analysis in subsequent fine synchronization without interrupting real-time data stream processing, thus achieving both flexibility and efficiency in processing.

[0096] Based on the above embodiments, as an optional embodiment, the step of performing frame synchronization processing on the parallel valid data to obtain the frame synchronization parameters of the data frame includes: The parallel valid data is coarsely synchronized to obtain a coarse timing clock index and an optimal parallel branch index. Based on the coarse timing clock index, the target baseband data segment of the target clock processing cycle is determined from the parallel baseband data of the signal to be synchronized; Based on the optimal parallel branch index, the target branch data segment of the target branch is determined from the target baseband data segment; The target branch data segment is subjected to fine synchronization processing to obtain a fine timing clock index.

[0097] The frame synchronization parameters include the coarse synchronization parameters for the first-level coarse synchronization and the fine synchronization parameters for the second-level fine synchronization. The coarse synchronization parameters include, but are not limited to, the coarse timing clock index and the optimal parallel branch index, while the fine synchronization parameters include, but are not limited to, the fine timing clock index.

[0098] Specifically, the goal of the first-level frame synchronization stage is to quickly capture the approximate location of the signal under conditions of significant time and frequency uncertainty. Parallel valid data is coarsely synchronized to obtain a coarse timing clock index. And the optimal parallel branch index Coarse synchronization parameters.

[0099] Based on coarse timing clock index And the optimal parallel branch index Perform data backtracking and branch selection, including based on coarse timing clock index. The read address pointer of the control frame synchronization RAM is used to read data temporarily stored in the frame synchronization RAM. In the parallel baseband data, the process traces back to the data segment containing the suspected synchronization header and rereads the relevant results corresponding to that data segment. In other words, the target clock processing cycle is determined from the parallel baseband data of the signal to be synchronized. The target baseband data segment. Among them, The target baseband data segment is read back from the frame synchronization RAM.

[0100] Also based on the optimal parallel branch index ,from Extracting the optimal parallel branch index from the relevant data stream of the target baseband data segment. The data stream from the corresponding optimal branch is used for subsequent processing, that is, from... The optimal parallel branch index is determined from the baseband data segment of the target road. The corresponding target branch data segment For subsequent processing.

[0101] The goal of the second-level frame synchronization stage is to perform fine-grained timing calibration and frequency estimation within a smaller uncertainty range based on the results of coarse synchronization. Therefore, for the target tributary data segment... Perform precise synchronization processing to obtain a precise timing clock index. .

[0102] The frame synchronization method provided by this invention employs a two-level synchronization strategy. It performs coarse synchronization processing on parallel valid data to obtain a coarse timing clock index and an optimal parallel branch index. Based on these two indices, it backtracks from the frame synchronization RAM to obtain the target branch data segment. Fine synchronization processing is then performed only on the target branch data segment. That is, only after the initial signal capture via coarse synchronization is the more complex second-level fine synchronization initiated using the buffered data in the frame synchronization RAM. This "on-demand processing" and "step-by-step solution" mechanism significantly reduces unnecessary computation, effectively lowers the occupancy of key hardware resources such as large-scale FFT / IFFT modules, multipliers, and storage units, reduces computational complexity and unnecessary computation, decreases frame synchronization processing latency, significantly shortens the average synchronization setup time, and improves the receiver's real-time processing capabilities.

[0103] Based on the above embodiments, as an optional embodiment, the coarse synchronization processing of the parallel effective data to obtain the coarse timing clock index and the optimal parallel branch index includes: For each valid data stream in the parallel valid data, square-law detection is performed on each valid data stream to obtain the instantaneous power value of each valid data stream; For each valid data stream, the latest instantaneous power value of the cumulative length is summed and accumulated according to the sliding step size to obtain the cumulative power value of each valid data stream; the sliding step size is determined based on the first continuous processing cycle number; the cumulative length is determined based on a preset second continuous processing cycle number; the second continuous processing cycle number is greater than or equal to twice the first continuous processing cycle number; Perform a peak search on the cumulative power values ​​of each valid data stream to determine the target peak value that exceeds a preset threshold; Based on the target peak value, the coarse timing clock index and the optimal parallel branch index are determined.

[0104] Specifically, in the first-stage coarse synchronization phase, to eliminate the influence of carrier phase on correlation peak values, [measures are taken to address these issues]. Each valid data in the parallel valid data Square-law detection is performed on each valid data stream to obtain the instantaneous power value of each valid data stream. .

[0105] Therefore, the expression for performing square-law detection on each channel of the parallel effective data to obtain the instantaneous power value of each channel of effective data is as follows: .

[0106] To enhance detection performance at low signal-to-noise ratios, sliding incoherent accumulation is further employed. This involves... Parallel, length of The loop register, every Each processing cycle stores data in the loop register. The instantaneous power values ​​are summed once for noncoherent accumulation to enhance the signal-to-noise ratio.

[0107] In other words, for each valid data stream, based on the number of consecutive processing cycles in the first cycle... A determined sliding step size is used for the second consecutive processing cycle number based on a preset value. The latest instantaneous power values ​​for a given cumulative length are summed to obtain the cumulative power value for each valid data stream. .

[0108] Among them, if used The index of the cumulative block is then... Cumulative power value of effective data for each branch The calculation formula is as follows: .

[0109] Further analysis of the incoherent accumulation results, i.e., the cumulative power value of each valid data stream. The CA-CFAR detector uses constant false alarm rate (CA-CFAR) detection to perform peak search on the cumulative power values ​​of each valid data stream, and determines the target peak value that exceeds a preset threshold. The CA-CFAR detector sets an adaptive decision threshold by calculating the average noise power within a reference window around the unit under test, thereby maintaining a constant false alarm probability under varying noise backgrounds.

[0110] When a target peak value exceeding a threshold is detected, the coarse timing clock index corresponding to the target peak value is determined. and the optimal parallel branch index , which serves as the coarse synchronization parameter for the first-level coarse synchronization output.

[0111] The frame synchronization method provided by this invention, through square-law detection, sliding incoherent accumulation, and peak search of parallel effective data, can eliminate the influence of carrier phase on correlation peaks and enhance detection performance at low signal-to-noise ratios. cumulative length and The sliding step size ensures that during the sliding process, at least one cumulative window can completely cover all [the area / areas]. The energy of each correlation peak is used to avoid missing the peak due to the window truncation effect, thus capturing the approximate location of the signal as accurately and quickly as possible in the presence of large time and frequency uncertainties. At the same time, coarse synchronization uses computationally simple square-law detection and incoherent accumulation to avoid large-scale, long-point FFT / IFFT operations throughout the entire data stream.

[0112] Based on the above embodiments, as an optional embodiment, the step of performing fine synchronization processing on the target branch data segment to obtain a fine timing clock index includes: The target branch data segment is sent into multiple frequency slots respectively. For each frequency slot, the target branch data segment is digitally mixed according to the preset assumed frequency of each frequency slot to obtain the mixed output data of each frequency slot. For each frequency slot, the frequency slot decision value is determined based on the coherent cumulative energy of each data sub-segment of the target branch data segment in each frequency slot. A two-dimensional decision matrix is ​​constructed based on the frequency slot decision values ​​of multiple frequency slots within the decision period; the decision period is determined based on the number of the second consecutive processing cycles. The maximum peak value is searched in the two-dimensional decision matrix, and the fine timing clock index is determined based on the processing clock coordinate value of the coordinates corresponding to the maximum peak value.

[0113] Specifically, to estimate and compensate for carrier frequency offset caused by factors such as Doppler, this embodiment employs multi-slot hypothesis testing to perform multi-slot pre-setting and mixing operations, and to optimize the target branch data segment of the optimal branch. Multiple (e.g.) are fed in parallel (Number) frequency slots, each frequency slot is configured according to a preset assumed frequency for that frequency slot. For the target branch data segment Digital mixing is performed to compensate for potential frequency offset, resulting in the mixing output data for each frequency slot. At this point, the... The expression for the mixing output data of each frequency slot is: .

[0114] When an unknown frequency offset exists, prolonged coherent accumulation can lead to energy cancellation due to phase rotation. To achieve frequency offset robustness, this embodiment employs segmented intra-segment coherent accumulation and inter-segment incoherent accumulation operations. Therefore, it is necessary to segment the length of... (Corresponding to one high-level code period) target branch data segment Divided into There are data segments, each with a length of . , that is .

[0115] For coherent accumulation within a segment, in a shorter period of time... Within each sampling period, the phase rotation caused by frequency offset is relatively small, allowing for coherent accumulation to achieve the maximum signal-to-noise ratio gain. Therefore, for each frequency slot, the coherent accumulation energy of each data segment in each frequency slot is calculated, where each data segment in the first sampling period... The expression for the coherent cumulative energy of each frequency slot is as follows: .

[0116] For inter-segment noncoherent accumulation, for each frequency slot, the target branch data segment... The incoherent accumulation of the coherent accumulated energy of each data segment in the frequency slot is directly summed to avoid inter-segment phase mismatch, thus obtaining the frequency slot decision value for that frequency slot. The expression for the frequency slot decision value for each frequency slot is as follows: .

[0117] The hybrid accumulation strategy of intra-segment coherent accumulation and inter-segment incoherent accumulation takes into account both the high gain of coherent accumulation and the frequency offset robustness of incoherent accumulation.

[0118] After intra-segment coherent accumulation and inter-segment incoherent accumulation, a two-dimensional joint peak decision and fine synchronization parameter output are performed, based on... Each frequency slot during the decision period The frequency slot decision value obtained inside , build a Given a two-dimensional decision matrix, search for the maximum peak value within the matrix and assign the coordinates of the maximum peak value. Processing clock coordinate values It was determined to be a precision timing clock index. .

[0119] Finally, by combining the results of coarse and fine synchronization, the starting sampling point index of the PN code can be accurately calculated. This determines the starting position of the synchronization header segment of the data frame.

[0120] Optionally, the starting sampling point index of the PN code Based on precise timing clock index And the optimal parallel branch index The function is determined by it.

[0121] Optionally, the starting sampling point index of the PN code The calculation formula is as follows: .

[0122] The last term in the formula causes the starting sampling point index to roll back. This value is used to eliminate the latency introduced by low-level code correlation.

[0123] The frame synchronization method provided by this invention innovatively integrates a multi-slot parallel processing mechanism in the second-level fine synchronization stage, accurately detects the frame header position and estimates key synchronization parameters, and then accurately calculates the starting position of the PN code in the current data frame based on the output precise timing information composed of coarse timing clock index, fine timing clock index and optimal parallel branch index.

[0124] Based on the above embodiments, as an optional embodiment, after searching for the maximum peak value in the two-dimensional decision matrix, the method further includes: The coarse frequency offset estimate is determined based on the frequency slot index coordinate value corresponding to the coordinate of the maximum peak value.

[0125] Specifically, after intra-segment coherent accumulation and inter-segment incoherent accumulation, a two-dimensional joint peak decision and fine synchronization parameter output are performed, based on... Each frequency slot during the decision period The frequency slot decision value obtained inside , build a Given a two-dimensional decision matrix, search for the maximum peak value within the matrix and assign the coordinates of the maximum peak value. Frequency slot index coordinates It was determined to be the coarse frequency offset estimate. .

[0126] In high-speed mobile scenarios such as low-Earth orbit satellite communications where significant Doppler frequency offset exists, the frequency offset drastically worsens the correlation between the signal and the local synchronization code, leading to a severe deterioration or even failure in synchronization performance. Correlation schemes struggle to perform efficient multi-slot parallel correlation detection under the APRX architecture, thus failing to provide a reliable coarse frequency offset estimate for subsequent modules during frame synchronization. This undoubtedly increases the acquisition range and computational complexity of subsequent carrier synchronization modules.

[0127] The frame synchronization method provided by this invention innovatively integrates a multi-slot parallel processing mechanism in the second-stage fine synchronization. This enables coarse-grained parallel detection and rough estimation of Doppler frequency offset within a certain range while simultaneously performing precise timing. This effectively overcomes the problem of synchronization failure caused by the sharp deterioration of correlation peaks due to frequency offset, ensuring reliable frame synchronization performance in high-speed mobile scenarios such as low-Earth orbit satellite communication. It improves synchronization robustness and accuracy in highly dynamic environments, enhancing the system's environmental adaptability. Furthermore, by providing a reliable coarse frequency offset estimate during the frame synchronization stage, it provides crucial prior information for the subsequent carrier synchronization module. This allows the carrier synchronization module to significantly narrow its frequency search range, thereby significantly accelerating carrier acquisition speed and reducing its computational burden. This not only improves the efficiency of individual modules but also optimizes the link design and processing flow of the entire communication system and the entire receiver link, improving overall performance and efficiency while reducing the complexity of subsequent modules.

[0128] Based on the above embodiments, as an optional embodiment, determining the frequency domain representation of the signal to be synchronized includes: The signal to be synchronized is subjected to quadrature downconversion to obtain a zero-IF analog baseband signal; The analog baseband signal is sampled and quantized according to a preset sampling rate to obtain parallel baseband data; Based on the parallel baseband data of the current cycle and the reserved baseband data of the previous cycle, the overlapping data blocks are determined; The frequency domain representation is obtained by performing a fast Fourier transform on the overlapping data blocks. The step of determining the parallel valid data of the signal to be synchronized without cyclic aliasing based on the time-domain circular convolution sequence includes: Based on the parallelism of the digital receiver, the parallel effective data without cyclic aliasing is extracted from the time-domain circular convolution sequence.

[0129] Parallel baseband data is generated by Parallel data streams constitute the path. The parallelism of the receiver processing is based on the preset sampling rate of the ADC. and system processing clock frequency It's confirmed.

[0130] Overlapping data blocks are data blocks constructed based on parallel baseband data and suitable for frequency domain processing.

[0131] The current cycle is the current processing clock cycle, and the previous cycle is the processing clock cycle preceding the current processing clock cycle. Retained baseband data refers to the baseband data from the previous cycle's parallel baseband data that has been retained in the current cycle.

[0132] Specifically, the front-end module of the digital receiver is responsible for processing the received signal to be synchronized. Process it.

[0133] First, orthogonal downconversion is performed on the intermediate frequency (IF) signal to be synchronized, converting it into a zero-IF analog baseband complex signal. Among them, analog baseband complex signals From in-phase components and orthogonal components Composition, that is .

[0134] Subsequently, the ADC operates at the preset sampling rate. For analog baseband signals Sampling and quantization are performed to obtain parallel baseband data. The parallelism of the receiver processing is... Based on the preset sampling rate and processing clock The decision was made jointly, and their relationship was as follows: .

[0135] Therefore, in each processing clock cycle The ADC will output A number of parallel complex data samples are obtained from... Parallel baseband data composed of parallel data streams can be uniformly represented as This serves as the input for subsequent processing modules.

[0136] Furthermore, to achieve efficient linear correlation using FFT, an overlap-preserving method is employed to construct overlapping data blocks suitable for frequency domain processing from the parallel baseband data. Specifically, the overlap-preserving method is used to... The parallel baseband data of the path is input to the overlap retention module, which uses a length of... The sliding data window, in the first Each processing clock cycle will convert the current cycle's... parallel baseband data (New data) and data retained from the previous period The baseband data (old data) is retained and spliced ​​together to form a new one. Point FFT input data block, also known as overlapping data block. .

[0137] The overlap-and-hold module determines the operation of overlapping data blocks based on the parallel baseband data of the current cycle and the held baseband data of the previous cycle. Logically, it is equivalent to a shift register, that is, the oldest data in the register is used for the operation. Discard the remaining data. The data is moved to the front of the shift register, and then the new data is moved to the front of the shift register. The data is filled into the end of the shift register.

[0138] Therefore, the mathematical model for overlapping data blocks is as follows: ; in, This is to retain the baseband data from the previous cycle. This is used as an overlapping data block for subsequent input to the FFT module.

[0139] Subsequently, the output of the overlap retention module is retained. Point-overlapping data blocks As input, FFT operation, frequency domain multiplication, and IFFT operation are performed sequentially.

[0140] Point-overlapping data blocks Sent to a The point FFT processing module performs FFT transformation processing. The point FFT processing module will treat it as an overlapping data block of the time-domain signal. Transform into the corresponding frequency domain representation That is, by performing a Fast Fourier Transform on the overlapping data blocks, the expression for the frequency domain representation can be obtained as follows: .

[0141] Frequency domain representation of the signal to be synchronized With pre-stored, length is frequency domain reference sequence The pointwise complex multiplication is performed, and the resulting pointwise multiplication is determined as the frequency domain correlation product of the signal to be synchronized. .

[0142] Frequency domain correlation product Sent to a The point IFFT processing module performs IFFT processing, multiplying the frequency domain correlations. Transforming back to the time domain yields the time-domain circular convolution sequence of the signal to be synchronized. .

[0143] Based on the principle of overlap preservation, the subsequent... Each sample represents a valid linear correlation value without cyclic aliasing. Therefore, from the temporal circular convolution sequence, the following values ​​are extracted: A non-aliased value is used as The parallel correlation results are used to obtain the parallel effective data of the signal to be synchronized. .

[0144] The frame synchronization method provided by this invention performs orthogonal downconversion, analog-to-digital conversion, overlap preservation, and FFT transform on the received signal to be synchronized before frame synchronization to obtain the frequency domain representation of the signal to be synchronized. Further, the frequency domain correlation product of the signal to be synchronized is determined by point-by-point multiplication of the frequency domain representation and the frequency domain reference sequence. Then, the frequency domain correlation product is subjected to IFFT transform and decyclic aliasing to obtain parallel effective data for frame synchronization. This lays the foundation for using frequency domain processing technology to achieve low-complexity matched filtering and low-level code sliding correlation operations, thereby improving the real-time processing capability of the receiver.

[0145] To better illustrate the frame synchronization method provided by the present invention, an embodiment is provided below to describe the complete process of the frame synchronization method.

[0146] Figure 3 This is the second flowchart illustrating the frame synchronization method provided by the present invention, as shown below. Figure 3 As shown, the frame synchronization method includes, but is not limited to, the following steps S1-S9.

[0147] Step S1: The signal to be synchronized is down-converted and analog-to-digital converted by the digital receiver front end to obtain... Parallel baseband data streams, also known as baseband I / Q data streams, where the parallelism... It is determined by both the receiver sampling rate and the system processing clock frequency.

[0148] Step S2: Obtain the data from each processing cycle Parallel baseband data is simultaneously fed into the data selector and the frame synchronization RAM; the frame synchronization RAM is used to buffer the parallel baseband data, and its write address is sequentially incremented, while the read address is controlled by the coarse synchronization parameters generated by the subsequent frame synchronization module.

[0149] Step S3: The data selector selects the data source based on the current stage of frame synchronization. In the first-level frame synchronization (coarse synchronization) stage, parallel baseband data directly output by the analog-to-digital converter is selected; in the second-level frame synchronization (fine synchronization) stage, buffered parallel baseband data read back from the frame synchronization RAM is selected.

[0150] Step S4: Parallel baseband data is fed into an overlap retention module. This module, through buffering and shifting operations, stores the data input in the current cycle. Parallel baseband data and data retained from the previous cycle The path retains baseband data splicing to generate a length of Overlapping data blocks.

[0151] Step S5: For Overlapping data blocks of length Point FFT yields the frequency domain representation of the signal to be synchronized.

[0152] Step S6: Combine the transformed frequency domain representation with a set of preset values ​​of length [missing information]. The frequency domain reference coefficients are multiplied point by point; this process is equivalent to the cyclic correlation operation between matched filtering and the low-level synchronization code in the time domain. It should be noted that... Figure 3 In this paper, for ease of understanding, frequency domain matched filtering and frequency domain low-level code cyclic correlation are represented by different symbols. However, based on the point-by-point multiplication of frequency domain reference coefficients, the process of multiplying frequency domain representation with frequency domain reference coefficients is actually equivalent to the process of frequency domain matched filtering and frequency domain low-level code cyclic correlation.

[0153] Step S7: Perform a multiplication of the frequency domain correlation products. Point IFFT yields a length of The temporal circular convolution sequence is truncated, and the latter part that is not affected by the aliasing effect of circular convolution is extracted. The path data serves as parallel valid data for effective output.

[0154] Step S8: Send the valid parallel data output into a two-level frame synchronization processing module. This module performs first-level frame synchronization and second-level frame synchronization according to preset logic.

[0155] In the first-level frame synchronization, also known as coarse synchronization, which aims to quickly capture the approximate location of the signal, the input is first... Perform square-law detection on each of the parallel valid data streams, and then perform the following operations in parallel on each of the square-law detected data streams: 1) Send each valid data stream into a buffer of length [length missing]. The buffer is cached and updated in the circular register; 2) Every time passing Each clock cycle processes the data stored in the loop register. Each data point is incoherently accumulated once to enhance the signal-to-noise ratio; 3) For the noncoherent accumulation result execution unit CA-CFAR, the existence of the signal is determined by detecting the target peak value exceeding the preset threshold, and the corresponding coarse timing clock index and optimal parallel branch index are output according to the target peak value.

[0156] Figure 4 These are the effect diagrams before and after coarse synchronization incoherent accumulation provided by the present invention, wherein... Figure 4 (a) is the effect diagram before coarse synchronization incoherent accumulation. Figure 4 (b) is the effect diagram after coarse synchronization incoherent accumulation.

[0157] like Figure 4 As shown in (a), this includes the instantaneous power value before accumulation. The horizontal axis represents the processing clock cycle. The vertical axis represents the parallel branch index. Due to low-level code In advanced code Appears periodically in the middle. Figure 4 (a) is visible There are several relevant peaks, but the noise and interference floor is high, so the peaks are not obvious.

[0158] like Figure 4 As shown in (b), this includes the accumulated power value. The horizontal axis represents the cumulative block index. As can be seen, after accumulation, the signal-to-noise ratio is significantly improved, forming a clear peak.

[0159] In addition, adopt cumulative length and The sliding step size ensures that during the sliding process, at least one cumulative window can completely cover all areas. The energy of each related peak is used to avoid missing the peak due to the window truncation effect, which is manifested in the possibility of two adjacent strong peaks appearing in the figure.

[0160] The second-level frame synchronization, also known as fine synchronization, involves performing precise timing calibration based on the coarse synchronization results and providing a coarse frequency offset estimate. The following steps are performed during this process.

[0161] First, based on the coarse timing clock index of the first-level frame synchronization output, the read address of the frame synchronization RAM is traced back to reread the data containing the synchronization header and obtain the target baseband data segment.

[0162] Next, based on the output optimal parallel branch index, from Extract the data stream of the branch from the parallel data of the branch to obtain the target branch data segment.

[0163] Then, to perform frequency offset estimation, the target branch data segment is compared with... Digital mixing is performed on local oscillation signals of different frequencies (slots) to obtain... The path carries signals with different frequency offset assumptions, i.e., the mixed output data.

[0164] Finally, for Each of the channels in the mixed output data performs the following operations in parallel: 1) Send the data into a buffer of length [length missing]. In the loop register; 2) After After one processing cycle, the loop register... The data is segmented and coherently accumulated, and then the accumulated results of each segment are incoherently accumulated to obtain the frequency slot decision value of the current frequency slot in the processing cycle. 3) Execute the above process continuously. Next, the frequency slot branch is obtained. Individual frequency slot decision value.

[0165] For all Individual frequency slots Within a judgment period The joint peak search is performed on the frequency slot decision values, and the frequency slot index and time index corresponding to the maximum peak value are the final coarse frequency offset estimate and fine timing clock index.

[0166] Figure 5 This is an example diagram of the two-dimensional decision matrix provided by the present invention, such as... Figure 5 As shown, all Individual frequency slots The judgment value obtained within each judgment period It constitutes a A two-dimensional decision matrix, with the horizontal axis representing the processing clock cycle index. The vertical axis represents the frequency slot index. Search for the maximum peak value in the two-dimensional decision matrix, and find the coordinates corresponding to the maximum peak value. This refers to the self-weight judgment result, where the frequency slot index coordinate value... Corresponding coarse frequency offset estimate Processing clock coordinate values Corresponding precise timing clock index .

[0167] Step S9: Finally, based on the timing information (coarse timing index and fine timing index) output by the two-level frame synchronization module, the optimal parallel branch, and the coarse frequency offset estimate, the starting position of the PN code in the synchronization header of the current data frame is accurately calculated.

[0168] Furthermore, to verify the effectiveness of the two-level frame synchronization method applicable to the APRX architecture in this embodiment, tests and simulations were conducted based on the following simulation parameters: 1. Receiver processes clock frequency Sampling rate Oversampling factor Parallelism ; 2. Low-level synchronization code sequence The number of signs (i.e., the length) is The length after oversampling is Advanced synchronization code sequence The number of signs (i.e., the length) is The total length of the synchronization code is ; 3. The number of FFT and IFFT points is 128, and the number of frequency slots is... Frequency step ; 4. Number of segments in the second-level frame synchronization data segment Length of each segment .

[0169] Figure 6 The graph shows the performance simulation results of the frame synchronization method provided by this invention. Figure 6 As shown, the correct detection probability of the frame synchronization method provided by the present invention is demonstrated under different signal-to-noise ratio (SNR) conditions. When the SNR is -12dB, the correct detection probability can reach a relatively high level of 95%. When the SNR is not lower than -11dB, the correct detection probability can be stabilized at a level close to 100%. This proves that the embodiments of the present invention, through a two-level synchronization strategy and an optimized cumulative detection algorithm, have excellent low SNR capture capability and high reliability. They can achieve fast and accurate frame synchronization in environments with poor SNR, and have significant technical advantages and high practical value.

[0170] Therefore, in view of the shortcomings of related technologies such as high resource consumption, high processing latency, and inability to perform effective coarse frequency offset estimation, the low-complexity two-level frame synchronization method for APRX architecture provided by this invention can achieve reliable and robust frame synchronization with low latency and hardware complexity.

[0171] Figure 7 This is a schematic diagram of the frame synchronization device provided by the present invention, as shown below. Figure 7 As shown, the frame synchronization device includes, but is not limited to, a frequency domain representation acquisition module 701, a matched filtering module 702, an inverse fast Fourier transform module 703, and a frame synchronization parameter acquisition module 704.

[0172] The frequency domain representation acquisition module 701 is used to determine the frequency domain representation of the signal to be synchronized.

[0173] The matched filtering module 702 is used to determine the frequency domain correlation product of the signal to be synchronized based on the point-by-point multiplication result of the frequency domain representation and the frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched with the parallelism of the digital receiver.

[0174] The inverse fast Fourier transform module 703 is used to perform an inverse fast Fourier transform on the frequency domain correlation product to obtain the time domain circular convolution sequence of the signal to be synchronized.

[0175] The frame synchronization parameter acquisition module 704 is used to determine the frame synchronization parameters of the data frame based on the time-domain circular convolution sequence of the signal to be synchronized, so as to determine the starting position of the synchronization header of the data frame.

[0176] It should be noted that the frame synchronization device provided by the present invention can execute the frame synchronization method described in any of the above embodiments during specific operation, and this embodiment will not elaborate on this.

[0177] The frame synchronization device provided by this invention determines the frequency domain reference sequence by fusing the frequency domain coefficients of the matched filter and the frequency domain coefficients of the low-level synchronization code sequence. It then employs frequency domain processing techniques to achieve low-complexity matched filtering and low-level code sliding correlation operations. Specifically, it determines the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation of the signal to be synchronized and the frequency domain reference sequence. This allows frame synchronization under the APRX architecture to simultaneously complete matched filtering and low-level code cyclic correlation in the frequency domain, significantly reducing the hardware resources occupied by frame synchronization in the receiver, especially the multiplier and storage resource overhead. This greatly reduces processing complexity and processing latency, improves the real-time processing capability of the receiver, and is particularly beneficial for processing high-speed parallel signals.

[0178] Optionally, the frequency domain representation acquisition module further includes: an orthogonal downconversion module, an analog-to-digital converter, an overlap-preservation module, and an FFT processing module.

[0179] The orthogonal downconversion module is used to perform orthogonal downconversion on the signal to be synchronized to obtain a zero-IF analog baseband signal.

[0180] The analog-to-digital converter is used to sample and quantize the analog baseband signal according to a preset sampling rate to obtain parallel baseband data.

[0181] The overlap retention module is used to determine overlapping data blocks based on the parallel baseband data of the current cycle and the retained baseband data of the previous cycle.

[0182] The FFT processing module is used to perform a fast Fourier transform on the overlapping data blocks to obtain the frequency domain representation.

[0183] Optionally, the frame synchronization parameter acquisition module further includes: an effective data acquisition module and a two-level frame synchronization module.

[0184] The effective data acquisition module is used to determine the parallel effective data of the signal to be synchronized without cyclic aliasing based on the time-domain circular convolution sequence of the signal to be synchronized.

[0185] The two-level frame synchronization module is used to perform frame synchronization processing on the parallel valid data to obtain the frame synchronization parameters of the data frame.

[0186] Optionally, the effective data acquisition module further includes an effective data interception module.

[0187] The effective data extraction module is used to extract the parallel effective data without cyclic aliasing from the time-domain circular convolution sequence according to the parallelism of the digital receiver.

[0188] Optionally, the two-level frame synchronization module further includes: a coarse synchronization processing module, a clock data segment extraction module, a tributary data segment extraction module, and a fine synchronization processing module.

[0189] The coarse synchronization processing module is used to perform coarse synchronization processing on the parallel valid data to obtain a coarse timing clock index and an optimal parallel branch index.

[0190] The clock data segment extraction module is used to determine the target baseband data segment of the target clock processing cycle from the parallel baseband data of the signal to be synchronized based on the coarse timing clock index.

[0191] The branch data segment extraction module is used to determine the target branch data segment of the target branch from the target baseband data segment based on the optimal parallel branch index.

[0192] The fine synchronization processing module is used to perform fine synchronization processing on the target branch data segment to obtain a fine timing clock index.

[0193] It should be noted that the frame synchronization device provided by the present invention can execute the frame synchronization method described in any of the above embodiments during specific operation, and this embodiment will not elaborate on this.

[0194] Figure 8 This is a schematic diagram of the receiver provided by the present invention, as shown below. Figure 8 As shown, the receiver 800 includes, but is not limited to, the frame synchronization device 700 provided in any of the above embodiments.

[0195] It should be noted that the receiver provided by the present invention, in specific operation, can be based on the frame synchronization device provided in any of the above embodiments and execute the frame synchronization method described in any of the above embodiments, which will not be elaborated in this embodiment.

[0196] The receiver provided by this invention determines the frequency domain reference sequence by fusing the frequency domain coefficients of the matched filter and the frequency domain coefficients of the low-level synchronization code sequence. It then employs frequency domain processing techniques to achieve low-complexity matched filtering and low-level code sliding correlation operations. Specifically, it determines the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation of the signal to be synchronized and the frequency domain reference sequence. This allows frame synchronization under the APRX architecture to simultaneously complete matched filtering and low-level code cyclic correlation in the frequency domain, significantly reducing the hardware resources occupied by frame synchronization in the receiver, especially the multiplier and storage resource overhead. This greatly reduces processing complexity and processing latency, improves the receiver's real-time processing capability, and is particularly beneficial for processing high-speed parallel signals.

[0197] Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 9 As shown, the electronic device may include: a processor 910, a communications interface 920, a memory 930, and a communication bus 940, wherein the processor 910, the communications interface 920, and the memory 930 communicate with each other through the communication bus 940. The processor 910 can call logical instructions in the memory 930 to execute the frame synchronization method provided in any of the above embodiments. The frame synchronization method includes, but is not limited to, the following steps: determining the frequency domain representation of the signal to be synchronized; determining the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation and the frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched with the parallelism of the digital receiver; performing an inverse fast Fourier transform on the frequency domain correlation product to obtain the time-domain circular convolution sequence of the signal to be synchronized; and determining the frame synchronization parameters of the data frame based on the time-domain circular convolution sequence of the signal to be synchronized to determine the starting position of the synchronization header of the data frame.

[0198] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0199] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the frame synchronization method provided in any of the above embodiments. The frame synchronization method includes, but is not limited to, the following steps: determining the frequency domain representation of the signal to be synchronized; determining the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation and the frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched with the parallelism of the digital receiver; performing an inverse fast Fourier transform on the frequency domain correlation product to obtain a time-domain circular convolution sequence of the signal to be synchronized; and determining the frame synchronization parameters of the data frame based on the time-domain circular convolution sequence of the signal to be synchronized to determine the starting position of the synchronization header of the data frame.

[0200] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the frame synchronization method provided in any of the above embodiments. The frame synchronization method includes, but is not limited to, the following steps: determining the frequency domain representation of the signal to be synchronized; determining the frequency domain correlation product of the signal to be synchronized based on the pointwise multiplication result of the frequency domain representation and the frequency domain reference sequence; the frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched with the parallelism of the digital receiver; performing an inverse fast Fourier transform on the frequency domain correlation product to obtain a time-domain circular convolution sequence of the signal to be synchronized; and determining the frame synchronization parameters of the data frame based on the time-domain circular convolution sequence of the signal to be synchronized, so as to determine the starting position of the synchronization header of the data frame.

[0201] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0202] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A frame synchronization method, characterized in that, include: Determine the frequency domain representation of the signal to be synchronized; Based on the point-by-point multiplication result of the frequency domain representation and the frequency domain reference sequence, the frequency domain correlation product of the signal to be synchronized is determined; The frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched to the parallelism of the digital receiver. Perform an inverse fast Fourier transform on the frequency domain correlation product to obtain the time-domain circular convolution sequence of the signal to be synchronized; Based on the time-domain circular convolution sequence of the signal to be synchronized, the frame synchronization parameters of the data frame are determined, so as to determine the starting position of the synchronization header of the data frame. The frequency domain reference sequence is determined based on the following method: The low-level synchronization code sequence is subjected to conjugate inversion, tail zero-padding expansion, and fast Fourier transform to obtain the frequency domain coefficients of the low-level synchronization code sequence. The time-domain matched filter coefficients of the matched filter are subjected to tail-padding expansion and fast Fourier transform processing to obtain the frequency-domain coefficients of the matched filter. The equivalent frequency domain filtering coefficients are determined based on the point-by-point multiplication of the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter. The frequency domain reference sequence is determined based on the frequency domain equivalent filter coefficients; The determination of frame synchronization parameters for data frames based on the temporal circular convolution sequence of the signal to be synchronized includes: Based on the time-domain circular convolution sequence, determine the parallel valid data of the signal to be synchronized without circular aliasing; The parallel valid data is subjected to frame synchronization processing to obtain the frame synchronization parameters of the data frame.

2. The frame synchronization method according to claim 1, characterized in that, The symbols in the synchronization header of the data frame are determined based on a low-level symbol in the low-level synchronization code sequence and a high-level symbol in the high-level synchronization code sequence. The length of the advanced synchronization code sequence is matched with the preset number of first consecutive processing cycles.

3. The frame synchronization method according to claim 2, wherein performing frame synchronization processing on the parallel valid data to obtain the frame synchronization parameters of the data frame includes: The parallel valid data is coarsely synchronized to obtain a coarse timing clock index and an optimal parallel branch index. Based on the coarse timing clock index, the target baseband data segment of the target clock processing cycle is determined from the parallel baseband data of the signal to be synchronized; Based on the optimal parallel branch index, the target branch data segment of the target branch is determined from the target baseband data segment; The target branch data segment is subjected to fine synchronization processing to obtain a fine timing clock index.

4. The frame synchronization method according to claim 3, wherein performing coarse synchronization processing on the parallel valid data to obtain a coarse timing clock index and an optimal parallel branch index includes: For each valid data stream in the parallel valid data, square-law detection is performed on each valid data stream to obtain the instantaneous power value of each valid data stream; For each valid data stream, the latest instantaneous power value of the cumulative length is summed and accumulated according to the sliding step size to obtain the cumulative power value of each valid data stream; the sliding step size is determined based on the first continuous processing cycle number; the cumulative length is determined based on a preset second continuous processing cycle number; the second continuous processing cycle number is greater than or equal to twice the first continuous processing cycle number; Perform a peak search on the cumulative power values ​​of each valid data stream to determine the target peak value that exceeds a preset threshold; Based on the target peak value, the coarse timing clock index and the optimal parallel branch index are determined.

5. The frame synchronization method according to claim 4, wherein performing fine synchronization processing on the target branch data segment to obtain a fine timing clock index includes: The target branch data segment is sent into multiple frequency slots respectively. For each frequency slot, the target branch data segment is digitally mixed according to the preset assumed frequency of each frequency slot to obtain the mixed output data of each frequency slot. For each frequency slot, the frequency slot decision value is determined based on the coherent cumulative energy of each data sub-segment of the target branch data segment in each frequency slot. A two-dimensional decision matrix is ​​constructed based on the frequency slot decision values ​​of multiple frequency slots within the decision period; the decision period is determined based on the number of the second consecutive processing cycles. The maximum peak value is searched in the two-dimensional decision matrix, and the fine timing clock index is determined based on the processing clock coordinate value of the coordinates corresponding to the maximum peak value.

6. The frame synchronization method according to claim 5, further comprising, after searching for the maximum peak value in the two-dimensional decision matrix: The coarse frequency offset estimate is determined based on the frequency slot index coordinate value corresponding to the coordinate of the maximum peak value.

7. The frame synchronization method according to claim 1, characterized in that, Determining the frequency domain representation of the signal to be synchronized includes: The signal to be synchronized is subjected to quadrature downconversion to obtain a zero-IF analog baseband signal; The analog baseband signal is sampled and quantized according to a preset sampling rate to obtain parallel baseband data; Based on the parallel baseband data of the current cycle and the retained baseband data of the previous cycle, the overlapping data blocks are determined; The frequency domain representation is obtained by performing a fast Fourier transform on the overlapping data blocks. The step of determining the parallel valid data of the signal to be synchronized without cyclic aliasing based on the time-domain circular convolution sequence includes: Based on the parallelism of the digital receiver, the parallel effective data without cyclic aliasing is extracted from the time-domain circular convolution sequence.

8. A frame synchronization device, characterized in that, include: The frequency domain representation acquisition module is used to determine the frequency domain representation of the signal to be synchronized; The matched filtering module is used to determine the frequency domain correlation product of the signal to be synchronized based on the point-by-point multiplication result of the frequency domain representation and the frequency domain reference sequence. The frequency domain reference sequence is determined based on the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter; the length of the low-level synchronization code sequence is matched to the parallelism of the digital receiver. The inverse fast Fourier transform module is used to perform an inverse fast Fourier transform on the frequency domain correlation product to obtain the time domain circular convolution sequence of the signal to be synchronized. The frame synchronization parameter acquisition module is used to determine the frame synchronization parameters of the data frame based on the time-domain circular convolution sequence of the signal to be synchronized, so as to determine the starting position of the synchronization header of the data frame. The frequency domain reference sequence is determined based on the following method: The low-level synchronization code sequence is subjected to conjugate inversion, tail zero-padding expansion, and fast Fourier transform to obtain the frequency domain coefficients of the low-level synchronization code sequence. The time-domain matched filter coefficients of the matched filter are subjected to tail-padding expansion and fast Fourier transform processing to obtain the frequency-domain coefficients of the matched filter. The equivalent frequency domain filtering coefficients are determined based on the point-by-point multiplication of the frequency domain coefficients of the low-level synchronization code sequence and the frequency domain coefficients of the matched filter. The frequency domain reference sequence is determined based on the frequency domain equivalent filter coefficients; The determination of frame synchronization parameters for data frames based on the temporal circular convolution sequence of the signal to be synchronized includes: Based on the time-domain circular convolution sequence, determine the parallel valid data of the signal to be synchronized without circular aliasing; The parallel valid data is subjected to frame synchronization processing to obtain the frame synchronization parameters of the data frame.

9. A receiver, characterized in that, include: The frame synchronization device as described in claim 8.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the frame synchronization method as described in any one of claims 1 to 7.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the frame synchronization method as described in any one of claims 1 to 7.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the frame synchronization method as described in any one of claims 1 to 7.

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