A method for improving the failure of super junction power devices igss

Abstract

This invention provides a method for improving IGSS failure in superjunction power devices, relating to the field of superjunction power device yield improvement technology. The method includes: confirming the failure parameter of the failure region as IGSS based on wafer testing or wafer acceptance testing results; identifying multiple failure causes for IGSS; determining multiple customized solutions based on the first failure cause, and executing these solutions to determine multiple execution results; determining the correlation between the failure morphology and the black silicon distribution generated by a preset etching process based on silicon spikes in the cell region; obtaining the optimal etching process formula when the correlation exists, and optimizing the bottom of the failure morphology based on the optimal etching process formula; obtaining a smooth and spike-free optimal morphology within a preset range of angular morphology by adjusting the gas ratio, and determining the EAS capability limit window of the optimal morphology. This improves IGSS 1V failure and significantly increases mass production yield.

Description

Technical Field

[0001] This invention relates to the field of power device superjunction (SJ) yield improvement technology, and in particular to a method for improving gate-source leakage current (IGSS) failure of superjunction power devices. Background Technology

[0002] Superjunction Metal-Oxide-Semiconductor Field-Effect Transistors (SJ MOS) employ a multiple epitaxial implantation process. To form a matching p-type structure, multiple epitaxial layer growths and p-type ion implantations are necessary, and the number of growth cycles is directly proportional to the cost. Although the multiple epitaxial implantation process is expensive, it allows for control of different implantation energies, dosages, and critical dimensions (CD) after each epitaxial layer, enabling the formation of different p-type region distributions at different depths as required. Mass production of SJ MOS requires precise control of the charge balance between the n-type and p-type layers. Accurate charge balance control is crucial for SJ MOS mass production, significantly impacting the drain-source breakdown voltage (BVDSS).

[0003] Currently, in the mass production of SJ MOS multilayer epitaxy, the electrical parameters of SJ MOS device wafer testing (Circuit Probing, CP) are strictly controlled, among which the energy avalanche stress (EAS) capability is particularly prominent. Therefore, the contact hole silicon loss (CT si loss) method is adopted to improve the EAS capability. However, the problem that comes with this is that due to the mismatch between the contact hole etching etch over etch (CT etch OE) capability, a large area of ​​IGSS 1V failure will appear around the edge, which can affect the yield by up to 50%. This is obviously unacceptable for the mass production requirements of wafers, resulting in a low mass production yield. Summary of the Invention

[0004] The purpose of this invention is to provide a method to improve the IGSS failure of superjunction power devices, and to solve the problem that the insufficient EAS limit capability of superjunction products in wafer testing leads to 1V IGSS failure around the edge, resulting in low mass production yield.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: This invention provides a method for improving IGSS failure in superjunction power devices, comprising: Based on the results of wafer testing or wafer acceptance testing, the failure parameter of the failure area was confirmed as IGSS; Multiple failure causes were identified for IGSS, including a primary failure cause and a secondary failure cause. Based on the primary cause of failure, multiple customized solutions are determined and executed to identify multiple execution results. The multiple customized solutions are different approaches to improve IGSS failure, and the multiple execution results include the failure morphology. Based on the silicon nails in the cell area, it was determined that the morphology of the failure is related to the black silicon distribution generated by the preset etching process; When there is correlation, the optimal etching process formulation is obtained, and the bottom of the failure morphology is optimized according to the optimal etching process formulation to improve the IGSS failure caused by the first failure cause. By adjusting the gas ratio, a smooth and silicon-free optimal morphology is obtained within a preset range of angular morphology, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause.

[0006] In some embodiments, the first cause of failure includes the photoresist thickness not meeting the target thickness, and the second cause of failure includes the contact hole being deepened.

[0007] In some embodiments, the multiple customization schemes include a first customization scheme and a second customization scheme, and the multiple execution results also include a target execution result. Based on a first failure cause, the corresponding multiple customization schemes are determined, and the multiple customization schemes are executed to determine the corresponding multiple execution results, including: When the photoresist thickness does not meet the target thickness, the first customized solution is determined to be to increase the photoresist thickness, or the second customized solution is determined to be to remove the aluminum layer on the surface of the failure area. The photoresist thickness is increased to the target thickness to obtain the target result, or the aluminum layer on the surface of the failure area is removed to obtain the failure morphology. The target result is the result of improving IGSS failure.

[0008] In some embodiments, the target thickness is 2.4 μm.

[0009] In some embodiments, before obtaining the optimal etching process formulation when there is correlation, and optimizing the bottom of the failure morphology based on the optimal etching process formulation to improve IGSS failure caused by the first failure cause, the method further includes: When there is correlation, the ratio of etching gas can be adjusted to obtain multiple etching process formulations; Among multiple etching process formulations, the optimal etching process formulation was determined.

[0010] In some embodiments, the etching gas is a mixture of HBr, SF6, Cl2 and O2.

[0011] In some embodiments, before obtaining a smooth and silicon-nails-free optimal morphology within a preset range of angular morphology by adjusting the gas ratio, and determining the EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause, the method further includes: Under the condition that the bias power or transformer-coupled plasma power is kept constant, the chamber pressure is adjusted to 10-60 mTorr, the HBr flow rate is adjusted to 100-500 sccm, the SF6 flow rate is adjusted to 20-200 sccm, the Cl2 flow rate is adjusted to 0-160 sccm, and the O2 flow rate is adjusted to 0-200 sccm.

[0012] In some embodiments, by adjusting the gas ratio, an optimal morphology that is smooth and free of silicon spikes is obtained within a preset range of angular morphology, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause, including: By adjusting the ratio of HBr, SF6, Cl2 and O2, the optimal morphology was obtained within a preset range of angular morphology. The depth of the optimal morphology is adjusted by adjusting the process window to determine the EAS capability limit window of the optimal morphology. The EAS capability limit window of the optimal morphology meets the mass production conditions and target mass production yield requirements.

[0013] In some embodiments, the preset range of angles is 95°-110°.

[0014] Compared to existing technologies, the method for improving IGSS failure in superjunction power devices provided by this invention confirms the failure parameters of the failure region as IGSS based on wafer testing or wafer acceptance testing results; identifies multiple failure causes for IGSS, including a first failure cause and a second failure cause; determines multiple customized solutions based on the first failure cause, and executes these solutions to determine multiple execution results, whereby the customized solutions are different approaches to improve IGSS failure, and the execution results include the failure morphology; determines the correlation between the failure morphology and the black silicon distribution generated by a preset etching process based on silicon spikes in the cell region; obtains the optimal etching process formula when the correlation exists, and optimizes the bottom of the failure morphology based on the optimal etching process formula to improve IGSS failure caused by the first failure cause; and obtains a smooth and silicon spike-free optimal morphology within a preset range of angular morphology by adjusting the gas ratio, and determines the EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause. In this way, different customized solutions can be determined for different failure causes. By obtaining the optimal etching process formula and optimizing the bottom of the failure morphology based on the optimal etching process formula, the IGSS failure caused by the first failure cause can be improved. By adjusting the gas ratio, a smooth and silicon nail-free optimal morphology can be obtained within a preset range of angle morphology. The EAS capability limit window of the optimal morphology can be determined to improve the IGSS failure caused by the second failure cause, thereby improving IGSS 1V failure and significantly improving mass production yield. Attached Figure Description

[0015] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1 A flowchart illustrating a method for improving IGSS failure in superjunction power devices is shown schematically. Figure 2 A schematic diagram illustrating the IGSS 1V failure principle of SJ MOS is shown. Figure 3 A schematic diagram of CT black silicon is shown; Figure 4 A schematic diagram illustrating the optimal morphology of CT silicon loss is shown. Detailed Implementation

[0016] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0017] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by one of ordinary skill in the art.

[0018] The methods described in the embodiments of the present invention will be explained in detail below.

[0019] Figure 1 A flowchart illustrating a method for improving IGSS failure in superjunction power devices according to an embodiment of the present invention is shown schematically. See [link to flowchart illustration]. Figure 1 As shown, the method for improving IGSS failure in superjunction power devices may include: S101. Based on the wafer test or wafer acceptance test results, confirm that the failure parameter of the failure area is IGSS.

[0020] Specifically, the first step is to investigate the exact location of the IGSS failure in the process flow. Based on the results of wafer probing / wafer acceptance test (CP / WAT), it can be determined that batches of IGSS with edge failures have all undergone CT (cut-and-paste) etching, while batches without IGSS failures are Insulated Gate Bipolar Transistors (IGBTs). The other two batches of SJ MOS did not undergo CT etching. It can be determined that IGSS failure in SJ MOS is strongly correlated with the CT etching process. The next step is to analyze the CT etching process.

[0021] S102. Several failure causes were identified for IGSS.

[0022] The failure has several causes, including a primary cause and a secondary cause. The primary cause is that the photoresist thickness does not meet the target thickness, while the secondary cause is that the contact holes are too deep.

[0023] Specifically, several suspected causes of failure were identified: The first suspected cause was insufficient photoresist thickness, the photoresist thickness not meeting the target thickness, and a distribution of photoresist (PR) that was thicker in the center and thinner at the edges, leading to excessive loss of CT photoresist during CT deepening and damage to the edge dielectric layer, resulting in IGSS failure. The second suspected cause was severe plasma damage at the contact hole corners caused by CT deepening, resulting in a drilling effect along the metal corners.

[0024] Figure 2 A schematic diagram illustrating the IGSS 1V failure principle of an SJ MOS is shown below. Figure 2 As shown, Figure 2 This is a typical wafer testing distribution diagram (Chip Probing Mapping and Positioning, CP MAP) when black silicon occurs. It identifies four main process-related causes of IGSS failure: gate oxide (involving oxidation and etching processes), polysilicon (involving etching morphology and residues), dielectric layer (involving film quality and via etching anomalies), and metal layer (involving metal residues and barrier layer metal anomalies). Figure 2 Taking the Vertical Double-Diffused Metal-Oxide-Semiconductor (VDMOS) device as an example, the structure of the VDMOS device is the same as that of the prior art. The main suspicion is that an abnormality in the metal layer caused the IGSS short circuit.

[0025] S103. Based on the first cause of failure, determine multiple customized solutions and execute multiple customized solutions to determine multiple execution results.

[0026] The multiple formulation schemes represent different approaches to improve IGSS failure, and the multiple execution results include the failure morphology. These multiple formulation schemes include a first and a second formulation scheme, and the multiple execution results also include the target execution result. The target thickness is 2.4 μm.

[0027] Specifically, based on the primary cause of failure, multiple customized solutions are determined and executed to determine the corresponding execution results, including: Step A1: When the photoresist thickness does not meet the target thickness, determine the corresponding first customized solution as a solution to increase the photoresist thickness, or determine the corresponding second customized solution as a solution to remove the aluminum layer on the surface of the failure area.

[0028] Step A2: Increase the photoresist thickness to the target thickness to obtain the target execution result, or remove the aluminum layer on the surface of the failure area to obtain the failure morphology.

[0029] The target execution result is the result of improving IGSS failure.

[0030] Specifically, the photoresist thickness is increased to 2.4 μm to obtain the target result, ensuring that photoresist failure during CT deepening does not affect the quality of the interlayer dielectric (ILD) layer. Alternatively, the aluminum layer on the surface of the failure area is removed to obtain the failure morphology.

[0031] For the target execution results obtained by increasing the photoresist thickness to 2.4μm, the IGSS failure caused by the increased CT photoresist thickness is significantly improved, with an average IGSS failure reduction of about 12.5%, and only a very small number of wafers still have edge IGSS failure.

[0032] S104. Based on the silicon nails in the cell area, determine that the morphology of the failure is related to the black silicon distribution generated by the preset etching process.

[0033] Specifically, Figure 3 A schematic diagram of CT black silicon is shown below. Figure 3 As shown, the morphological analysis of the failure revealed a correlation between the edge failure of the SJ MOS and the black silicon distribution generated after a CT silicon loss of 5000A. Since silicon spikes were found in the wafer center dicing, edge dicing, and cell regions, primarily in the cell regions, it can be determined that this is related to the etching process formulation.

[0034] S105. Obtain the optimal etching process formula when there is correlation, and optimize the bottom of the failure morphology according to the optimal etching process formula to improve the IGSS failure caused by the first failure cause.

[0035] Specifically, the method further includes obtaining the optimal etching process formulation when there is correlation, and optimizing the bottom of the failure morphology based on the optimal etching process formulation to improve IGSS failure caused by the primary failure cause. Step B1: When there is correlation, adjust the ratio of etching gas to obtain multiple etching process formulations.

[0036] The etching gas is a mixture of HBr, SF6, Cl2 and O2.

[0037] When there is correlation, that is, when the silicon nails of the unit area on the lower surface of the contact hole are etched, multiple etching process formulas can be obtained by adjusting the ratio of etching gas (HBr / SF6 / Cl2 / O2). There can be up to 10 etching process formulas. The number of etching process formulas can be varied. Here, there is no specific limit to the number of etching process formulas.

[0038] Step B2: Determine the optimal etching process formulation from among multiple etching process formulations.

[0039] Among multiple etching process formulations, the optimal etching process formulation is determined. For specific procedures on adjusting the depth to the required position for mass production, please refer to existing technologies.

[0040] S106. By adjusting the gas ratio, a smooth and silicon-free optimal morphology is obtained within a preset range of angular morphology, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause.

[0041] Specifically, before obtaining a smooth and silicon-nails-free optimal morphology within a preset range of angular topography by adjusting the gas ratio, and determining the EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause, the method further includes: With the bias power or transformer coupled plasma power (Bias Power / TCP Power) kept constant, the chamber pressure was adjusted to 10-60 mTorr, the HBr flow rate to 100-500 sccm, the SF6 flow rate to 20-200 sccm, the Cl2 flow rate to 0-160 sccm, and the O2 flow rate to 0-200 sccm.

[0042] Specifically, by adjusting the gas ratio, a smooth and silicon-nails-free optimal morphology is obtained within a preset range of angular topography, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause, including: Step C1: By adjusting the ratio of HBr, SF6, Cl2 and O2, the optimal morphology is obtained within the preset range of angular morphology.

[0043] The preset angle range is 95°-110°.

[0044] While maintaining a constant bias power or transformer-coupled plasma power (Bias Power / TCP Power), adjust the ratios of HBr, SF6, Cl2, and O2 within the ranges of 10-60 mTorr chamber pressure, 100-500 sccm HBr flow rate, 20-200 sccm SF6 flow rate, 0-160 sccm Cl2 flow rate, and 0-200 sccm O2 flow rate. There can be 10 possible ratios of HBr, SF6, Cl2, and O2, and the number of possible ratios is not specifically limited here. Adjusting to these 10 ratios will yield 10 different angular morphologies.

[0045] For example, Table 1 shows the ratio of two gases, including Design of Experiments (DOE) 1 and DOE 2, bias power, TCP power, pressure, HBr flow rate, SF6 flow rate, Cl2 flow rate, O2 flow rate, and the presence and morphology of silica nails under microscopic examination.

[0046] Table 1. Ratio of the two gases

[0047] Microscopic examination of the surface morphology at angles of 95°-110° reveals whether it is smooth and free of silica spikes, thus selecting the optimal morphology. The optimal morphology is one with a smooth surface and no silica spikes. The depth of each point in the morphology is measured to determine if it is consistent; inconsistency indicates irregularity, meaning the surface is not smooth, while consistency indicates a smooth surface. Figure 4 A schematic diagram illustrating the optimal morphology of CT silicon loss is shown below. Figure 4 As shown, Figure 4 The optimal morphology is one with a smooth surface and no silicon spikes. This ensures silicon failure without the presence of black silicon at the bottom, which could lead to IGSS failure.

[0048] Step C2: Adjust the process window for the depth of the optimal morphology to determine the EAS capability limit window of the optimal morphology.

[0049] Among them, the EAS capability limit window with the optimal morphology satisfies the mass production conditions and the target mass production yield requirements.

[0050] Specifically, the depth of the optimal morphology is adjusted by adjusting the process window to determine the EAS capability limit window of the optimal morphology, and the EAS capability limit window is checked to ensure that it meets the mass production conditions and target mass production yield requirements.

[0051] This invention deepens silicon loss during the CT etching process of SJ products. The superjunction structure in the superjunction power device achieves charge balance through alternating P / N pillars, improving the device's breakdown voltage (BV) and reducing on-resistance. The depth of the contact holes directly affects carrier injection efficiency and contact resistance. A key challenge is that CT etching introduces a 1V IGSS failure around the edge due to large areas of black silicon on the contact hole surface. Improving the etching process eliminates this IGSS failure issue. A three-pronged strategy—precise etching depth control, junction protection design, and efficient annealing repair—allows for improved performance through deeper contact holes while minimizing the impact of silicon loss on yield. The process window needs to be controlled within a depth deviation of <5%, supplemented by reliability screening, with an expected yield improvement of 8-12%. In actual implementation, process parameters need to be dynamically adjusted based on online monitoring data to ensure the integrity of the superjunction structure in the superjunction power device remains within safe limits.

[0052] This invention can greatly optimize the EAS limit capability of semiconductor devices by deepening the silicon loss of the contact holes and changing the current path. At the same time, it can improve the product yield around the edge, reduce the yield loss caused by black silicon in the contact holes, better achieve the stability of mass production process, reduce the fluctuation of wafer test electrical parameters, and reduce the economic losses caused by electrical parameter failures.

[0053] The method for improving IGSS failure in superjunction power devices according to the present invention includes: confirming the failure parameters of the failure region as IGSS based on wafer testing or wafer acceptance testing results; identifying multiple failure causes for IGSS, including a first failure cause and a second failure cause; determining multiple customized solutions based on the first failure cause, and executing the multiple customized solutions to determine multiple execution results, wherein the multiple customized solutions are different solutions for improving IGSS failure, and the multiple execution results include the failure morphology; determining the correlation between the failure morphology and the black silicon distribution generated by a preset etching process based on silicon spikes in the cell region; obtaining the optimal etching process formula when there is a correlation, and optimizing the bottom of the failure morphology based on the optimal etching process formula to improve the IGSS failure caused by the first failure cause; obtaining a smooth and silicon spike-free optimal morphology within a preset range of angular morphology by adjusting the gas ratio, and determining the EAS capability limit window of the optimal morphology to improve the IGSS failure caused by the second failure cause. In this way, different customized solutions can be determined for different failure causes. By obtaining the optimal etching process formula and optimizing the bottom of the failure morphology based on the optimal etching process formula, the IGSS failure caused by the first failure cause can be improved. By adjusting the gas ratio, a smooth and silicon nail-free optimal morphology can be obtained within a preset range of angle morphology. The EAS capability limit window of the optimal morphology can be determined to improve the IGSS failure caused by the second failure cause, thereby improving IGSS 1V failure and significantly improving mass production yield.

[0054] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for improving IGSS failure in superjunction power devices, characterized in that, include: Based on the results of wafer testing or wafer acceptance testing, the failure parameter of the failure area was confirmed as IGSS; Multiple failure causes were identified for the IGSS, including a first failure cause and a second failure cause; Based on the first failure cause, multiple customized solutions are determined and executed to determine multiple execution results. The multiple customized solutions are different solutions to improve IGSS failure, and the multiple execution results include the failure morphology. Based on the silicon nails in the unit area, it is determined that the morphology of the failure is related to the black silicon distribution generated by the preset etching process; When there is correlation, the optimal etching process formulation is obtained, and the bottom of the failure morphology is optimized according to the optimal etching process formulation to improve the IGSS failure caused by the first failure cause. By adjusting the gas ratio, a smooth and silicon-free optimal morphology is obtained within a preset range of angular morphology, and the EAS capability limit window of the optimal morphology is determined to improve IGSS failure caused by the second failure cause.

2. The method for improving IGSS failure of superjunction power devices according to claim 1, characterized in that, The first cause of failure includes the photoresist thickness not meeting the target thickness, and the second cause of failure includes the contact hole being deepened.

3. The method for improving IGSS failure of superjunction power devices according to claim 2, characterized in that, The plurality of customized schemes include a first customized scheme and a second customized scheme, and the plurality of execution results also include a target execution result. The step of determining the corresponding plurality of customized schemes based on the first failure cause and executing the plurality of customized schemes to determine the corresponding plurality of execution results includes: When the photoresist thickness does not meet the target thickness, the corresponding first customized solution is determined to be a solution to increase the photoresist thickness, or the corresponding second customized solution is determined to be a solution to remove the aluminum layer on the surface of the failure area. The photoresist thickness is increased to the target thickness to obtain the target execution result, or the aluminum layer on the surface of the failure area is removed to obtain the failure morphology. The target execution result is the result of improving IGSS failure.

4. The method for improving IGSS failure of superjunction power devices according to claim 3, characterized in that, The target thickness is 2.4 μm.

5. The method for improving IGSS failure of superjunction power devices according to claim 1, characterized in that, The method further includes obtaining the optimal etching process formulation when there is correlation, and optimizing the bottom of the failure morphology according to the optimal etching process formulation to improve the IGSS failure caused by the first failure cause, before: When there is correlation, the ratio of etching gas can be adjusted to obtain multiple etching process formulations; Among the plurality of etching process formulations, the optimal etching process formulation is determined.

6. The method for improving IGSS failure of superjunction power devices according to claim 5, characterized in that, The etching gas is a mixture of HBr, SF6, Cl2 and O2.

7. The method for improving IGSS failure of superjunction power devices according to claim 1, characterized in that, Before obtaining a smooth and silicon-nails-free optimal morphology within a preset range of angular topography by adjusting the gas ratio, and determining the EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause, the method further includes: Under the condition that the bias power or transformer-coupled plasma power is kept constant, the chamber pressure is adjusted to 10-60 mTorr, the HBr flow rate is adjusted to 100-500 sccm, the SF6 flow rate is adjusted to 20-200 sccm, the Cl2 flow rate is adjusted to 0-160 sccm, and the O2 flow rate is adjusted to 0-200 sccm.

8. The method for improving IGSS failure of superjunction power devices according to claim 7, characterized in that, The process of adjusting the gas ratio to obtain a smooth and silicon-free optimal morphology within a preset range of angular topography, and determining the EAS capability limit window of the optimal morphology to improve IGSS failure caused by the second failure cause, includes: The optimal morphology is obtained within the preset range of angular morphology by adjusting the ratio of HBr, SF6, Cl2 and O2. The depth of the optimal morphology is adjusted by a process window to determine the EAS capability limit window of the optimal morphology. The EAS capability limit window of the optimal morphology satisfies the mass production conditions and the target mass production yield requirements.

9. The method for improving IGSS failure of superjunction power devices according to claim 1, characterized in that, The preset range of angles is 95°-110°.

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