Display device, method for manufacturing same, and electronic device

Abstract

A display device, a method for manufacturing the same, and an electronic device are disclosed. The display device includes a substrate on which a transistor is disposed. A gate insulator is disposed on the transistor. A conductive layer is disposed on the gate insulator. The plurality of conductive patterns of the conductive layer are spaced apart from each other. The interlayer dielectric layer is disposed on the plurality of conductive patterns. The interlayer dielectric layer includes an inorganic material. The planarization layer is disposed on the interlayer dielectric layer and defines a plurality of openings. The plurality of openings expose the interlayer dielectric layer. The planarization layer includes an inorganic material.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0094654, filed on July 17, 2024, in the Korean Intellectual Property Office (KIPO) and to Korean Patent Application No. 10-2024-0184592, filed on December 12, 2024, in the KIPO, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a display device, a method for manufacturing the display device, and an electronic device. BACKGROUND

[0004] With the development of an information-oriented society, the demand for display devices is on the rise. For example, display devices are being applied to an increasing variety of electronic devices, such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light emitting display device (e.g., an organic light emitting display device). Among such flat panel display devices, the light emitting display device includes a light emitting element that self-emits, so that each pixel of a display panel can emit light by itself without a backlight unit that supplies light to the display panel. SUMMARY

[0005] Aspects of the present disclosure provide a display device capable of providing a high-resolution image and a method for manufacturing a display device.

[0006] Aspects of the present disclosure also provide a method for improving reliability of a display device.

[0007] It should be noted that the objectives of the present disclosure are not limited to the above-mentioned objectives; and other objectives of the present disclosure will be apparent to those skilled in the art from the following description.

[0008] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description.

[0009] According to an embodiment of the present disclosure, a display device includes a substrate on which a transistor is disposed. A gate insulator is disposed on the transistor. A conductive layer is disposed on the gate insulator. A plurality of conductive patterns of the conductive layer are spaced apart from each other. An interlayer dielectric layer is disposed on the plurality of conductive patterns. The interlayer dielectric layer includes an inorganic material. A planarization layer is disposed on the interlayer dielectric layer and defines a plurality of openings. The plurality of openings exposes the interlayer dielectric layer. The planarization layer includes an inorganic material.

[0010] In some embodiments, each of the plurality of conductive patterns can overlap with a corresponding one of the plurality of openings of the planarization layer.

[0011] In some embodiments, the planarization layer can be disposed between adjacent ones of the plurality of conductive patterns in a plan view.

[0012] In some embodiments, the plurality of conductive patterns can comprise a conductive metal, and the plurality of conductive patterns are disposed on the same layer and the upper surfaces of the plurality of conductive patterns are on the same plane.

[0013] In some embodiments, each of the plurality of conductive patterns can have an island shape.

[0014] In some embodiments, the interlayer dielectric layer can be disposed across the substrate. The interlayer dielectric layer can be in direct contact with all of the upper surfaces and lateral side surfaces of the plurality of conductive patterns to cover the plurality of conductive patterns.

[0015] In some embodiments, the interlayer dielectric layer can have a height difference between portions not overlapping the plurality of openings and portions overlapping the plurality of openings.

[0016] In some embodiments, a thickness of the planarization layer can be in a range of about 50% to about 150% of the height difference of the interlayer dielectric layer.

[0017] In some embodiments, the interlayer dielectric layer can comprise a first surface disposed in the plurality of openings and on an opposite side of the surface of the interlayer dielectric layer directly contacting the plurality of conductive patterns. The planarization layer comprises an upper surface higher than the upper surfaces of the plurality of conductive patterns.

[0018] In some embodiments, the upper surface of the planarization layer can be on the same plane as the first surface of the interlayer dielectric layer.

[0019] In some embodiments, the upper surface of the planarization layer can be lower than the first surface of the interlayer dielectric layer in a direction perpendicular to the upper surface of the substrate.

[0020] In some embodiments, the upper surface of the planarization layer can be higher than the first surface of the interlayer dielectric layer in a direction perpendicular to the upper surface of the substrate.

[0021] In some embodiments, the planarization layer can be arranged in a pattern completely surrounding the plurality of openings in a plan view.

[0022] In some embodiments, the plurality of conductive patterns can each be located in a corresponding one of the plurality of openings in a plan view. The plurality of conductive patterns and the planarization layer can be spaced apart from each other in the plan view. The planarization layer completely surrounds the plurality of conductive patterns in the plan view.

[0023] In some embodiments, the interlayer dielectric layer can completely cover the plurality of conductive patterns in the plurality of openings in a plan view, and the interlayer dielectric layer can be between the planarization layer and the plurality of conductive layers.

[0024] According to embodiments of the present disclosure, a method for manufacturing a display device includes forming a conductive layer having a plurality of conductive patterns on a gate insulator of a transistor, and then forming an interlayer dielectric layer on the plurality of conductive patterns; forming a planarization layer and a sacrificial layer on the interlayer dielectric layer; and removing a portion of the planarization layer and the sacrificial layer, wherein removing the portion of the planarization layer and the sacrificial layer includes removing the portion of the planarization layer and the sacrificial layer via an etching process including an etch-back process.

[0025] In some embodiments, forming the interlayer dielectric layer on the plurality of conductive patterns can include forming the interlayer dielectric layer such that the interlayer dielectric layer completely covers the plurality of conductive patterns and the interlayer dielectric layer has a uniform thickness with a manufacturing error less than or equal to about 10%.

[0026] In some embodiments, the planarization layer can include an inorganic material, and the sacrificial layer can include an organic material.

[0027] In some embodiments, the planarization layer can define a plurality of openings, and the planarization layer exposes the interlayer dielectric layer through the plurality of openings.

[0028] According to embodiments of the present disclosure, an electronic device includes at least one display device including a substrate on which a transistor is disposed. A display device housing accommodates the at least one display device. An optical member magnifies a display image of the at least one display device or converts a light path. The at least one display device includes a gate insulator disposed on the transistor. A plurality of conductive patterns is disposed on the gate insulator. The plurality of conductive patterns is spaced apart from each other. An interlayer dielectric layer is disposed on the plurality of conductive patterns. The interlayer dielectric layer includes an inorganic material. A planarization layer is disposed on the interlayer dielectric layer and defines a plurality of openings. The plurality of openings exposes the interlayer dielectric layer. The planarization layer includes an inorganic material.

[0029] According to embodiments of the present disclosure, a display device is capable of providing a high-resolution image, and is capable of solving a reliability problem of the display device.

[0030] According to embodiments of this disclosure, a display device includes a substrate on which transistors are disposed. A gate insulator is disposed on the transistors. A conductive layer is disposed on the gate insulator. The conductive layer is arranged in a pattern of separated conductive islands disposed on the same surface. An interlayer dielectric layer is disposed on the conductive layer. The interlayer dielectric layer includes a plurality of first portions disposed on the conductive islands at a first height and a plurality of second portions disposed between the conductive islands at a second height less than the first height. A planarization layer is disposed on the plurality of second portions of the interlayer dielectric layer and located between adjacent first portions of the interlayer dielectric layer.

[0031] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent to those skilled in the art based on the following description. Attached Figure Description

[0032] The above and other aspects and features of this disclosure will become more apparent from the detailed description of non-limiting embodiments of this disclosure with reference to the accompanying drawings.

[0033] Figure 1 This is a perspective view illustrating a head-mounted electronic device according to an embodiment of the present disclosure.

[0034] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 An exploded perspective view of an example of a head-mounted electronic device.

[0035] Figure 3 This is a perspective view illustrating a head-mounted electronic device according to an embodiment of the present disclosure.

[0036] Figure 4 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0037] Figure 5 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0038] Figure 6 This is a plan view illustrating the display layer of a display device according to an embodiment of the present disclosure.

[0039] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6 The cross-sectional view of the display layer is taken by line X-X'.

[0040] Figure 8 According to embodiments of this disclosure Figure 7 An enlarged cross-sectional view of region A.

[0041] Figure 9 According to embodiments of this disclosure Figure 7 An enlarged cross-sectional view of region A.

[0042] Figure 10 is a cross-sectional view of the region A according to an embodiment of the disclosure. Figure 7

[0043] Figure 11 is a plan view of the region C according to an embodiment of the disclosure. Figure 7

[0044] Figure 12 is a cross-sectional view of the display layer taken along the line X-X' of Figure 6

[0045] Figure 13 is a flowchart for illustrating a method for manufacturing the transistor layer in Figure 7

[0046] Figure 14 and Figure 15 is a cross-sectional view of the step S100 of Figure 13

[0047] Figure 16 is a cross-sectional view of the step S200 of Figure 13

[0048] Figure 17 and Figure 18 is a cross-sectional view of the step S300 of Figure 13

[0049] Figure 19 is a cross-sectional view of the step S400 of Figure 13

[0050] Figure 20 is a block diagram of an electronic device according to an embodiment of the disclosure.

[0051] Figure 21 is a view of an electronic device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0052] The present disclosure will now be described more fully with reference to the accompanying drawings, in which some non-limiting embodiments of the present disclosure are illustrated. The present disclosure may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein.

[0053] ​​​​​​​​It will also be understood that, when a layer or substrate is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present. When a layer or substrate is referred to as being "directly on" another layer or substrate, intervening layers can not be present. Like reference numerals refer to like components throughout the specification.

[0054] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element could be termed a first element.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] The inventive concept relates to source and drain electrodes of a pixel transistor, the source and drain electrodes simultaneously contacting an active layer and a lower electrode through a contact hole penetrating the active layer. In case a contact hole penetrating the active layer is formed, the active layer is provided with a thickness range in which the active layer maintains a high mobility of charge carriers such as electrons without defects affecting the electrical properties of the active layer due to over-etching. In particular, the active layer can comprise an oxide semiconductor material.

[0057] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0058] The present disclosure focuses on a display device including a planarization layer that provides a flat surface over an inorganic interlayer dielectric layer covering a plurality of conductive patterns such as separate island-type conductive patterns. The planarization layer can improve reliability of the display device by compensating for a height difference between a plurality of first portions of the interlayer dielectric layer disposed on the conductive patterns at a first height and a plurality of second portions of the interlayer dielectric layer disposed between the conductive patterns at a second height less than the first height.

[0059] Figure 1 is a perspective view illustrating a head-mounted electronic device according to an embodiment of the present disclosure. Figure 2 is a perspective view illustrating a head-mounted electronic device according to an embodiment of the present disclosure. Figure 1 is an exploded perspective view of an example of the head-mounted electronic device of is an exploded perspective view of an example of the head-mounted electronic device of

[0060] Reference Figure 1 and Figure 2 The head-mounted electronic device 1 according to an embodiment includes a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head strap 140, a first display device 10_1, a second display device 10_2, a middle frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector.

[0061] In an embodiment, the first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described with reference to Figure 4 Thus, the description of the first display device 10_1 and the second display device 10_2 will be replaced with the description of the display device 10 described with reference to Figures 4 to 12 .

[0062] The first optical member 151 can be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 can be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 can include at least one convex lens.

[0063] The middle frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and can be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0064] The control circuit board 170 can be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 can be connected to (e.g., electrically connected to) the first display device 10_1 and the second display device 10_2 through the connector. The control circuit board 170 can convert an image source input from the outside into digital video data, and can transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0065] The control circuit board 170 can transmit digital video data associated with a left-eye image optimized for the left eye of the user to the first display device 10_1, and can transmit digital video data associated with a right-eye image optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 170 can transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0066] The display device housing 110 accommodates the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is disposed to cover an open face of the display device housing 110. In an embodiment, the housing cover 120 can include a first eyepiece 131 at which a left eye of a user is placed and a second eyepiece 132 at which a right eye of the user is placed. Although the first eyepiece 131 and the second eyepiece 132 are separately disposed in the example shown in Figure 1 and Figure 2 , embodiments of the present disclosure are not necessarily limited thereto. The first eyepiece 131 and the second eyepiece 132 can be combined into a single element.

[0067] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical member 152. Accordingly, the user can see a virtual image of an image magnified by the first optical member 151 in the first display device 10_1 through the first eyepiece 131, and a virtual image of an image magnified by the second optical member 152 in the second display device 10_2 through the second eyepiece 132.

[0068] The head strap 140 fixes the display device housing 110 to the head of the user so that the first eyepiece 131 and the second eyepiece 132 in the housing cover 120 are respectively maintained in alignment with the left eye and the right eye of the user. In an embodiment, by implementing the display device housing 110 to be small and light, the head-mounted electronic device 1 can include a spectacle frame as shown in Figure 3 without including the head strap 140.

[0069] In addition, the head-mounted electronic device 1 can further include a battery for power supply, an external memory slot for insertion of an external memory, and an external connection port and a wireless communication module for reception of an image source. In an embodiment, the external connection port can be a USB (Universal Serial Bus) terminal, a display port, or an HDMI (High Definition Multimedia Interface) terminal. The wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0070] Figure 3 is a perspective view showing a head-mounted electronic device according to an embodiment of the present disclosure.

[0071] Reference is made to Figure 3The head-mounted electronic device 1_1 according to the embodiment can be an eyeglass-type display device with a small and lightweight display device housing 120_1. The head-mounted electronic device 1_1 according to the embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, eyeglass frames (e.g., temples) 341 and 342, an optical component 320, an optical path conversion component 330, and a display device housing 120_1.

[0072] Figure 3 The display device 10_3 shown is related to the reference. Figure 4 The display device 10 described is essentially the same.

[0073] The display device housing 120_1 can accommodate the display device 10_3, the optical component 320, and the light path conversion component 330. In an embodiment, the image displayed on the display device 10_3 can be magnified by the optical component 320, and the light path of the image is converted by the light path conversion component 330 to be provided to the user's right eye through the right eye lens 312. As a result, the user can see (e.g., visually) an augmented reality image with their right eye, which combines the virtual image displayed on the display device 10_3 with the real-world image observed through the right eye lens 312.

[0074] Despite Figure 3 In the illustrated embodiment, the display device housing 120_1 is located at the right end of the support frame 350, but the embodiments of this disclosure are not limited to this. For example, in one embodiment, the display device housing 120_1 may be located at the left end of the support frame 350. In this embodiment, the image displayed on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 120_1 may be located at both the left and right ends of the support frame 350. In this embodiment, the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0075] Figure 4 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0076] refer to Figure 4In an embodiment, the display device 10 can be applied to various different portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC). For example, in an embodiment, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IOT) device. For another example, the display device 10 can be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD) device. However, embodiments of the present disclosure are not necessarily limited thereto, and the electronic device to which the display device 10 can be applied can be various different small-, medium-, or large-sized electronic devices.

[0077] When viewed from the top (e.g., in a plan view), the display device 10 can have a shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2. In an embodiment, a corner where the short side in the first direction DR1 meets the long side in the second direction DR2 can be rounded with a predetermined curvature or can be a right angle. When viewed from the top, the shape of the display device 10 is not necessarily limited to a quadrilateral, but can be formed in various different shapes such as a shape similar to other polygons, a circular shape, or an elliptical shape.

[0078] The display device 10 can include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0079] The display panel 100 can include a main area MA and a sub area SBA. The main area MA can include a display area DDA and a non-display area NDA (e.g., in a plan view) located around the display area DDA, the display area DDA including pixels for displaying an image.

[0080] The display area DDA can output light from a plurality of emission areas or a plurality of openings which will be described later. For example, the display panel 100 can include a pixel circuit (which includes a switching element), a pixel definition layer defining an emission area or an opening, and a self-emission element. For example, in an embodiment, the self-emission element can include (but is not necessarily limited to) at least one of an organic light-emitting diode including an organic emission layer, a quantum dot light-emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (micro LED). In the following drawings, it is shown that the self-emission element is an organic light-emitting diode.

[0081] The non-display area NDA can be disposed on the outside of the display area DDA (e.g., in a plan view). The non-display area NDA can be defined as an edge region of the main area MA of the display panel 100.

[0082] The sub area SBA can extend from one side of the main area MA. For example, in the embodiment shown in FIG. 1A, the sub area SBA extends from the upper side of the main area MA (e.g., in a direction opposite to the second direction DR2). The sub area SBA can include a flexible material that can be bent, folded, or rolled. For example, when the sub area SBA is bent, the sub area SBA can overlap the main area MA in the thickness direction (e.g., the third direction DR3). The sub area SBA can include a pad connected to the display driver 200 and the circuit board 300. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the display device 10 can not include the sub area SBA, and the display driver 200 and the pad can be disposed in the non-display area NDA. Figure 4

[0083] The display driver 200 can output signals and voltages for driving the display panel 100. In an embodiment, the display driver 200 can be implemented as an integrated circuit (IC) and can be attached to the display panel 100 by a chip-on-glass (COG) technology, a chip-on-plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 can be located in the sub area SBA and can overlap the main area MA in the thickness direction when the sub area SBA is in a bent orientation. For another example, the display driver 200 can be mounted on the circuit board 300.

[0084] In an embodiment, the circuit board 300 can be attached to the pad area of the display panel 100 using anisotropic conductive film (ACF). The circuit board 300 can be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film.

[0085] The touch driver 400 can be mounted on (e.g., disposed on) the circuit board 300. The touch driver 400 can be connected to the touch sensor layer TSL (see FIG. 2) for detecting a touch on the display device 10 and can drive the touch sensor layer TSL of the display device 10. Figure 5

[0086] Figure 5 is a cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0087] Reference will now be made to Figure 5 ​​In an embodiment, the display panel 100 can include a display layer DPL, a touch sensor layer TSL, and a color filter layer CFL. The display layer DPL can include a substrate SUB, a transistor layer TFTL, a display element layer EML, and a thin film encapsulation layer TFEL.

[0088] The substrate SUB can be a base substrate or a base member. In an embodiment, the substrate SUB can be a flexible substrate that can be bent, folded, or rolled up. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but is not necessarily limited thereto. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the substrate SUB can include a glass material or a metal material.

[0089] The transistor layer TFTL can be disposed on the substrate SUB (e.g., directly disposed on the substrate SUB in the third direction DR3). In an embodiment, the transistor layer TFTL can be located in the display area DDA, the non-display area NDA, and the auxiliary area SBA. The transistor layer TFTL can include a plurality of transistors TFT (see FIG. 2). Figure 7 )。

[0090] The display element layer EML can be disposed on the transistor layer TFTL (e.g., directly disposed on the transistor layer TFTL in the third direction DR3). The display element layer EML can be located in the display area DDA. In an embodiment, the display element layer EML can include (but is not necessarily limited to) at least one of an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light emitting diode (micro LED).

[0091] The thin film encapsulation layer TFEL can be located on the display element layer EML (e.g., directly disposed on the display element layer EML in the third direction DR3). The thin film encapsulation layer TFEL can be located in the display area DDA and the non-display area NDA. The thin film encapsulation layer TFEL can cover the upper surface and the side surface of the display element layer EML and can protect the display element layer EML from external oxygen and moisture. The thin film encapsulation layer TFEL can include at least one inorganic film and at least one organic film for encapsulating the display element layer EML. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some implementations, the display device 10 can not include the thin film encapsulation layer TFEL.

[0092] The touch sensor layer TSL can be disposed on the thin-film encapsulation layer TFEL (e.g., directly disposed on the thin-film encapsulation layer TFEL on the third-party DR3). The touch sensor layer TSL can be positioned across the display area DDA and the non-display area NDA. The touch sensor layer TSL can sense the user's touch through mutual capacitance sensing or self-capacitance sensing. However, embodiments of this disclosure are not limited thereto. For example, in some embodiments, the display device 10 may not include a touch sensor layer TSL.

[0093] A color filter layer (CFL) can be disposed on the touch sensor layer (TSL) (e.g., directly on the touch sensor layer (TSL) on the third-party DR3). In an embodiment, the color filter layer (CFL) can be located in the display area (DDA) and the non-display area (NDA). The color filter layer (CFL) can absorb some light introduced from the outside of the display device 10 (e.g., the external environment) to reduce the reflection of external light. Therefore, the color filter layer (CFL) can prevent color distortion due to the reflection of external light.

[0094] In embodiments where the color filter layer CFL is directly disposed on the touch sensor layer TSL, the display device 10 may not have a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small. However, the embodiments of this disclosure are not limited thereto. For example, in some embodiments, the display device 10 may not include the color filter layer CFL.

[0095] like Figure 5 As shown, the portion of the display panel 100 that overlaps with the auxiliary region SBA can be bent. In an embodiment, when a portion of the display panel 100 has a bent orientation, the display driver 200, the circuit board 300, and the touch driver 400 can overlap with the main region MA on the third orientation DR3.

[0096] When a portion of the display panel 100 has a bending orientation, the bending protection layer BPL can protect the underlying structure located in the auxiliary area SBA from bending stress.

[0097] Figure 6 This is a plan view illustrating the display layer of a display device according to an embodiment of the present disclosure.

[0098] refer to Figure 6 The display layer DPL may include multiple pixels PX located in the display area DDA, as well as multiple voltage lines VL, multiple scan lines SL, multiple emission control lines EDL and multiple data lines DL connected to the multiple pixels PX.

[0099] In an embodiment, the plurality of scan lines SL can extend longitudinally in the first direction DR1 and can be spaced apart from each other in a second direction DR2 crossing the first direction DR1. The scan lines SL can be arranged along the second direction DR2. The scan lines SL can sequentially supply a scan signal to the pixels PX.

[0100] In an embodiment, the emission control lines EDL can extend longitudinally in the first direction DR1 and can be spaced apart from each other in the second direction DR2. The emission control lines EDL can be arranged along the second direction DR2. The emission control lines EDL can sequentially supply an emission control signal to the pixels PX.

[0101] In an embodiment, the data lines DL can extend longitudinally in the second direction DR2 and can be spaced apart from each other in the first direction DR1. The data lines DL can be arranged along the first direction DR1. The data lines DL can apply a data voltage to the pixels PX. The data voltage can determine a luminance of each of the plurality of pixels PX.

[0102] In an embodiment, the voltage lines VL can include a main voltage line VL1 and an auxiliary voltage line VL2. At least one of a first supply voltage (e.g., a high-level voltage) and a second supply voltage (e.g., a low-level voltage) can be transmitted to the auxiliary voltage line VL2 through the main voltage line VL1 located in the non-display area NDA. In the following description, the main voltage line VL1 and the auxiliary voltage line VL2 can be collectively referred to as the voltage lines VL.

[0103] The non-display area NDA can surround the display area DDA (e.g., in a plan view). The non-display area NDA can include the scan driver 211 and the emission control driver 213.

[0104] The scan driver 211 can be disposed on an outer side of the display area DDA or on a side portion of the non-display area NDA (e.g., in a plan view). The scan driver 211 can include a plurality of driving transistors for generating a gate signal based on a gate control signal.

[0105] In an embodiment, the emission control driver 213 can be disposed on opposite outer sides of the display area DDA or on opposite side portions of the non-display area NDA (e.g., in a plan view). The emission control driver 213 can include a plurality of emission control transistors for generating an emission signal based on an emission control signal.

[0106] The display layer DPL according to an embodiment can include the display driver 200 located in the sub-area SBA and a plurality of pad electrodes PD. The plurality of pad electrodes PD can be spaced apart from each other in the first direction DR1, and the pad electrodes PD can be respectively connected to different lines.

[0107] Figure 7 is a cross-sectional view of a display layer taken along a line X-X' of FIG. 1A, according to an embodiment of the present disclosure. Figure 6 is a cross-sectional view of a display layer taken along a line X-X' of FIG. 1A, according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view of an embodiment of a display layer DPL included in one pixel PX, and schematically shows a substrate SUB, a transistor layer TFTL, a display element layer EML, and a thin film encapsulation layer TFEL. The substrate SUB has been described above with reference to Figure 5 ; and thus, in order to save description, a redundant description will be omitted.

[0108] Referring to Figure 7 and in conjunction with Figures 1 to 6 , the transistor layer TFTL can be disposed on the substrate SUB.

[0109] The transistor layer TFTL can be disposed on the substrate SUB (e.g., directly on the substrate SUB in the third direction DR3). In an embodiment, the transistor layer TFTL can include a first buffer layer BF1, a transistor TFT, a gate insulator GI, a first conductive layer CDL1, an interlayer dielectric layer ILD, a planarization layer IPL, a second buffer layer BF2, a second conductive layer CDL2, a first via layer VIA1, a third conductive layer CDL3, and a second via layer VIA2.

[0110] The first buffer layer BF1 can be disposed on the substrate SUB (e.g., directly on the substrate SUB in the third direction DR3). The first buffer layer BF1 can prevent air or moisture from penetrating through the substrate SUB. In an embodiment, the first buffer layer BF1 can include multiple inorganic films stacked (e.g., in the third direction DR3) alternately with each other.

[0111] For example, in an embodiment, the first buffer layer BF1 can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0112] The transistor TFT can be disposed on the first buffer layer BF1 (e.g., directly on the first buffer layer BF1 in the third direction DR3). The transistor TFT can be a driving transistor of the pixel PX. The transistor TFT can include a semiconductive material. For example, in an embodiment, the transistor TFT can include polysilicon, amorphous silicon, oxide semiconductor, or other semiconductor materials.

[0113] The transistor TFT can include a channel region CH aligned with (e.g., overlapping) the gate electrode GE in the third direction DR3. Additionally, the transistor TFT can include a source region SA and a drain region DRA located on both sides of the channel region CH in the first direction DR1, respectively. The source region SA and the drain region DRA can become conductive by doping or another method to have a higher conductivity than that of the channel region CH during a process of manufacturing the display device 10.

[0114] The gate insulator GI can be provided over the transistor TFT. The gate insulator GI can prevent penetration of air or moisture. For example, in an embodiment, the gate insulator GI can include a plurality of inorganic films stacked alternately with each other (e.g., in the third direction DR3).

[0115] The gate insulator GI can include an inorganic insulating material. Accordingly, the gate insulator GI can electrically insulate the gate electrode GE from the transistor TFT.

[0116] For example, in an embodiment, the gate insulator GI can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0117] The first conductive layer CDL1 can be provided over the gate insulator GI (e.g., directly over the gate insulator GI in the third direction DR3). In an embodiment, the first conductive layer CDL1 can include the gate electrode GE, the first conductive portion CP1, and the second conductive portion CP2. The first conductive layer CDL1 can be composed of a conductive material such as a conductive metal.

[0118] The gate electrode GE can be provided over the gate insulator GI (e.g., directly over the gate insulator GI in the third direction DR3). The gate electrode GE can overlap the channel region CH of the transistor TFT in the third direction DR3 with the gate insulator GI interposed therebetween.

[0119] The gate electrode GE can include a conductive material. For example, in an embodiment, the gate electrode GE can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, an alloy of these metals, or other conductive materials.

[0120] The first conductive portion CP1 and the second conductive portion CP2 can be electrically connected to the transistor TFT. In an embodiment, the first conductive portion CP1 can be connected to a source region SA of the transistor TFT through a contact hole that penetrates the gate insulator GI, and the second conductive portion CP2 can be connected to a drain region DRA of the transistor TFT through a contact hole that penetrates the gate insulator GI. For example, the first conductive portion CP1 can be a source electrode, and the second conductive portion CP2 can be a drain electrode.

[0121] The first conductive portion CP1 and the second conductive portion CP2 can include a conductive material. For example, in an embodiment, the first conductive portion CP1 and the second conductive portion CP2 can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, an alloy of these metals, or other conductive materials.

[0122] The interlayer dielectric layer ILD can be disposed on (e.g., directly on) the first conductive layer CDL1. The interlayer dielectric layer ILD can completely cover the first conductive layer CDL1 and the gate insulator GI. In an embodiment, the interlayer dielectric layer ILD can have a height difference among different portions of the interlayer dielectric layer ILD. A more detailed description will be given below.

[0123] The interlayer dielectric layer ILD can prevent penetration of air or moisture from the outside (e.g., an external environment) and can protect the first conductive layer CDL1 during a manufacturing process.

[0124] The interlayer dielectric layer ILD can include an inorganic insulating material. For example, in an embodiment, the interlayer dielectric layer ILD can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0125] The planarization layer IPL can be disposed on (e.g., directly on) the interlayer dielectric layer ILD. The planarization layer IPL can provide a flat surface over the interlayer dielectric layer ILD having a height difference. A more detailed description will be given below.

[0126] The planarization layer IPL can include an inorganic insulating material. For example, in an embodiment, the planarization layer IPL can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO xSilicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0127] The second buffer layer BF2 may be disposed on the interlayer dielectric layer ILD and the planarization layer IPL (e.g., directly disposed on the interlayer dielectric layer ILD and the planarization layer IPL on the third-party DR3). However, embodiments of this disclosure are not limited thereto. For example, in some embodiments, the display device 10 may not include the second buffer layer BF2. The second buffer layer BF2 may comprise the same material as the first buffer layer BF1. Therefore, redundant descriptions will be omitted.

[0128] The second conductive layer CDL2 can be disposed on the second buffer layer BF2 (e.g., directly disposed on the second buffer layer BF2 on the third-direction DR3). The second conductive layer CDL2 may include a third conductive portion CP3 and a fourth conductive portion CP4. The third conductive portion CP3 and the fourth conductive portion CP4 may include components disposed on... Figure 6 At least one of the various lines in the display area DDA.

[0129] The second conductive layer CDL2 may include a conductive material, such as a conductive metal. For example, in an embodiment, the second conductive layer CDL2 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, alloys of these metals, or other conductive materials.

[0130] In an embodiment, the third conductive portion CP3 included in the second conductive layer CDL2 can be connected to the first conductive portion CP1 of the first conductive layer CDL1 through contact holes penetrating the interlayer dielectric layer ILD and the second buffer layer BF2. The fourth conductive portion CP4 included in the second conductive layer CDL2 can be connected to the second conductive portion CP2 of the first conductive layer CDL1 through contact holes penetrating the interlayer dielectric layer ILD and the second buffer layer BF2.

[0131] The first via layer VIA1 can be located on the second buffer layer BF2 (e.g., directly disposed on the second buffer layer BF2 on the third-direction DR3) and can cover the second conductive layer CDL2. The first via layer VIA1 can provide a flat surface above the underlying structure. Here, the underlying structure refers to the structure formed by all layers below the first via layer VIA1.

[0132] The first via layer VIA1 may include organic materials. For example, in the embodiments, the first via layer VIA1 may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0133] The third conductive layer CDL3 can be disposed on the first via layer VIA1 (e.g., directly on the first via layer VIA1 in the third direction DR3). The third conductive layer CDL3 can be a connection electrode electrically connecting the second conductive layer CDL2 and the anode electrode AE. In an embodiment, the third conductive layer CDL3 can be electrically connected to the fourth conductive portion CP4 of the second conductive layer CDL2 through a contact hole penetrating the first via layer VIA1.

[0134] The second via layer VIA2 can be disposed on the first via layer VIA1 (e.g., directly on the first via layer VIA1 in the third direction DR3) and can cover the third conductive layer CDL3. The second via layer VIA2 can provide a flat surface over the underlying structure. Here, the underlying structure refers to a structure formed by all layers under the second via layer VIA2.

[0135] The second via layer VIA2 can include an organic material. For example, in an embodiment, the second via layer VIA2 can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

[0136] The display element layer EML can be disposed on the transistor layer TFTL (e.g., directly on the transistor layer TFTL in the third direction DR3). The display element layer EML can include the light emitting element ED and the pixel definition layer PDL. The light emitting element ED can include the anode electrode AE, the emission layer EL, and the cathode electrode CE.

[0137] The anode electrode AE of the light emitting element ED can be disposed on the second via layer VIA2 (e.g., directly on the second via layer VIA2 in the third direction DR3). In an embodiment, the anode electrode AE can be connected to the third conductive layer CDL3 through a contact hole penetrating the second via layer VIA2.

[0138] In an embodiment, the anode electrode AE can be composed of a single layer of silver (Ag), molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or can be composed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to improve reflectivity. The APC alloy can be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0139] The pixel definition layer PDL can be disposed on the second via layer VIA2 (e.g., directly on the second via layer VIA2 in the third direction DR3). The pixel definition layer PDL defines the pixel opening OP and can expose the anode electrode AE in the pixel opening OP. In embodiments, the pixel definition layer PDL can cover edges of the anode electrode AE, and the pixel opening OP can expose a central portion of the anode electrode AE.

[0140] The pixel definition layer PDL can include an organic material or an inorganic material.

[0141] For example, in embodiments in which the pixel definition layer PDL includes an organic material, the pixel definition layer PDL can include an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin, etc.

[0142] For example, in embodiments in which the pixel definition layer PDL includes an inorganic material, the pixel definition layer PDL can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0143] The emission layer EL of the light emitting element ED can be located on the anode electrode AE (e.g., directly on the anode electrode AE in the third direction DR3). The emission layer EL can include an organic material to emit light of a specific color. For example, in embodiments, the emission layer EL can include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer can include a host and a dopant. The organic material layer can include a material that emits a predetermined light, and can be formed using a phosphor or a fluorescent material.

[0144] The cathode electrode CE of the light emitting element ED can be located on the emission layer EL (e.g., disposed on the emission layer EL in the third direction DR3). The cathode electrode CE can be positioned to cover the emission layer EL. The cathode electrode CE can be a common layer disposed across multiple emission layers EL of multiple pixels PX (see Figure 6 ).

[0145] In embodiments, the cathode electrode CE can be formed of a transparent conductive material (TCP) such as ITO and IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). In embodiments in which the cathode electrode CE is made of a semi-transmissive conductive material, light extraction efficiency can be improved by using a microcavity.

[0146] The thin film encapsulation layer TFEL can be formed on the display element layer EML (e.g., disposed directly on the display element layer EML in the third direction DR3). The thin film encapsulation layer TFEL can include at least one inorganic film to prevent penetration of oxygen or moisture into the display element layer EML. The thin film encapsulation layer TFEL can include at least one organic film to protect the display element layer EML from particles such as dust.

[0147] In an embodiment, the thin film encapsulation layer TFEL can include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3.

[0148] In an embodiment, the first encapsulation layer TFE1 can be located on (e.g., disposed directly on) the cathode electrode CE and can completely cover the cathode electrode CE.

[0149] The first encapsulation layer TFE1 can include an inorganic insulating material. For example, in an embodiment, the first encapsulation layer TFE1 can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0150] The second encapsulation layer TFE2 can be located on (e.g., disposed directly on) the first encapsulation layer TFE1 in the third direction DR3 and can completely cover the first encapsulation layer TFE1. The second encapsulation layer TFE2 can provide a flat surface over the first encapsulation layer TFE1.

[0151] In an embodiment, the second encapsulation layer TFE2 can include an organic material and can be, for example, an organic film containing an organic resin such as an acrylic resin, an epoxy resin, a silicone resin, a silicone-acrylic resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0152] The third encapsulation layer TFE3 can be located on (e.g., disposed directly on) the second encapsulation layer TFE2 in the third direction DR3 and can completely cover the second encapsulation layer TFE2.

[0153] The third encapsulation layer TFE3 can include an inorganic insulating material. For example, in an embodiment, the first encapsulation layer TFE1 can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0154] Figure 8is Figure 7 an enlarged cross-sectional view of the region A. Hereinafter, the structures of the first conductive layer CDL1, the interlayer dielectric layer ILD, and the planarization layer IPL will be described in detail.

[0155] With reference to Figure 8 and in conjunction with Figures 1 to 7 The first conductive layer CDL1 can be disposed on the gate insulator GI (e.g., directly disposed on the gate insulator GI in the third direction DR3). The first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE included in the first conductive layer CDL1 can be conductive patterns including a conductive material. The conductive patterns described above can refer to patterns of separate conductive islands.

[0156] According to embodiments of the present disclosure, the included first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE in the first conductive layer CDL1 can be located on the same plane in the first direction DR1. For example, the upper and lower surfaces of the first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE can be coplanar with each other (e.g., in the third direction DR3), and can be disposed on the same layer extending in the first direction DR1, which is a direction parallel to the upper surface of the substrate SUB. The first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE can be spaced apart from each other (e.g., in the first direction DR1). Accordingly, a plurality of conductive patterns can be disposed on the gate insulator GI, and the plurality of conductive patterns can be spaced apart from each other in the first direction DR1.

[0157] According to embodiments of the present disclosure, the included first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE in the first conductive layer CDL1 can have the same thickness Tm (e.g., length in the third direction DR3). However, it should be noted that the widths of the first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE in the first direction DR1 can be different from each other.

[0158] The interlayer dielectric layer ILD can be disposed on (e.g., directly on) the first conductive layer CDL1, and can completely cover the first conductive portion CP1, the second conductive portion CP2, and the gate electrode GE, such as by directly contacting all of the upper surfaces and lateral side surfaces of each of the conductive patterns in the first conductive layer CDL1. The interlayer dielectric layer ILD can completely cover the plurality of conductive patterns disposed below the interlayer dielectric layer ILD. In embodiments, the interlayer dielectric layer ILD can be disposed on the entire substrate SUB.

[0159] According to embodiments of the present disclosure, the interlayer dielectric layer ILD can be formed with a uniform thickness Td (e.g., a length in the third direction DR3) along a profile formed by the underlying structure having a height difference. Accordingly, the interlayer dielectric layer ILD can have different heights that conform to the profile formed by the underlying structure. It should be noted that the meaning of the uniformity of the thickness Td of the interlayer dielectric layer ILD can allow for a range of process errors (e.g., manufacturing errors) of about 10% or less.

[0160] For example, the interlayer dielectric layer ILD can cover along a height difference formed between the plurality of conductive patterns of the first conductive layer CDL1 and the gate insulator GI. Accordingly, the interlayer dielectric layer ILD can have a height difference Hd, such as a height difference between a portion of the interlayer dielectric layer ILD disposed in the opening OPp of the planarization layer IPL and a portion of the interlayer dielectric layer ILD not disposed in the opening OPp of the planarization layer IPL.

[0161] In embodiments, the interlayer dielectric layer ILD can include a first surface d1 and a second surface d3.

[0162] The first surface d1 can be a surface of a portion (e.g., a first portion) of the interlayer dielectric layer ILD positioned such that it overlaps the first conductive layer CDL1 in the third direction DR3. The first surface d1 can be an opposite surface to a surface in direct contact with the first conductive layer CDL1. For example, the first surface d1 can face a side in the third direction DR3. The first surface d1 can be located in the opening OPp of the planarization layer IPL, which will be described later. The first surface d1 can be at a first height.

[0163] The second surface d3 can be a surface of a portion (e.g., a second portion) of the interlayer dielectric layer ILD positioned such that it does not overlap the first conductive layer CDL1 in the third direction DR3 and is disposed between conductive patterns (such as between separate conductive islands on the same plane) of the first conductive layer CDL1. The second surface d3 can be an opposite surface to a surface in direct contact with the gate insulator GI. For example, the second surface d3 can face a side in the third direction DR3. The second surface d3 can not overlap the opening OPp of the planarization layer IPL. The second surface d3 can be in direct contact with the planarization layer IPL. The second surface d3 can be at a second height less than the first height of the first surface d1.

[0164] The first surface d1 and the second surface d3 of the interlayer dielectric layer ILD can be located on different planes in the first direction DR1. A height difference between a plane on which the first surface d1 is located and a plane on which the second surface d3 is located in the first direction DR1 can mean a height difference Hd of the interlayer dielectric layer ILD. The height difference Hd of the interlayer dielectric layer ILD can be less than or equal to the thickness Tm of the first conductive layer CDL1.

[0165] According to embodiments of the disclosure, the interlayer dielectric layer ILD can further include a first side surface d5 and a second side surface d7. The first side surface d5 can be directly connected to the second surface d3 and can face the planarization layer IPL in the first direction DR1. The second side surface d7 can be directly connected to the first surface d1 and can connect the first surface d1 with the first side surface d5.

[0166] According to embodiments of the disclosure, the second side surface d7 of the interlayer dielectric layer ILD can be a curved surface. The second side surface d7 can be formed as a curved surface as a portion of the interlayer dielectric layer ILD is exposed to an etch-back process in an etching process during a process of manufacturing the display device 10. Such a manufacturing process will be described later.

[0167] Generally, in a display device applied to a high resolution device, a plurality of conductive patterns of the first conductive layer CDL1 can be formed in a narrow area. This can mean that the first conductive layer CDL1 formed with the conductive patterns is arranged with a narrow interval. Accordingly, the interlayer dielectric layer ILD can cover a height difference formed by the plurality of conductive patterns of the first conductive layer CDL1, and the interlayer dielectric layer ILD can also have a height difference Hd accordingly. The height difference Hd in the interlayer dielectric layer ILD can be a difference in height between a portion of the interlayer dielectric layer ILD that does not overlap the opening OPp of the planarization layer IPL and a portion of the interlayer dielectric layer ILD that overlaps the opening OPp of the planarization layer IPL.

[0168] According to embodiments of the disclosure, the display device 10 can include a planarization layer IPL that provides a flat surface with respect to the height difference Hd of the interlayer dielectric layer ILD.

[0169] For example, if the insulating layer having a height difference is repeatedly stacked on the conductive pattern included in the high resolution display device in the third direction DR3, a reliability defect in the display device can be caused. For example, if the insulating layer having a height difference is stacked on the conductive pattern included in the high resolution display device without the planarization layer, a reliability defect in the display device can be caused (e.g., a defect due to a portion of the conductive pattern not being covered and exposed and / or a defect due to uneven exposure of the height difference of the conductive pattern, etc.).

[0170] Accordingly, the planarization layer IPL according to embodiments can planarize the height difference in the interlayer dielectric layer ILD and reduce reliability defects of the display device 10.

[0171] According to embodiments of the disclosure, the planarization layer IPL can be disposed (e.g., in a plan view) between adjacent conductive patterns of the first conductive layer CDL1 that are spaced apart from each other. In a cross-sectional view, the planarization layer IPL can define an opening OPp, and the interlayer dielectric layer ILD, such as the first surface d1 of the interlayer dielectric layer ILD, can be exposed through the opening OPp. For example, the planarization layer IPL can be in the form of a single pattern that surrounds the opening OPp.

[0172] According to embodiments of the disclosure, the first conductive layer CDL1 can be positioned such that it overlaps the opening OPp, and the planarization layer IPL can completely surround the first conductive layer CDL1 (e.g., in a plan view). For example, each of the patterns of conductive islands of the first conductive layer CDL1, such as the gate electrode GE, the first conductive portion CP1, and the second conductive portion CP2, can overlap a corresponding opening OPp of the planarization layer IPL.

[0173] According to embodiments of the disclosure, the planarization layer IPL can be formed to completely cover the interlayer dielectric layer ILD and then formed into a shape as shown in FIG. 1B via a subsequent etching process during a process of manufacturing the display device 10. Figure 8 Such a manufacturing process will be described later.

[0174] According to some embodiments, the thickness Tp1 of the planarization layer IPL can have a value in a range of about 50% to about 150% of the height difference Hd of the interlayer dielectric layer ILD.

[0175] For example, if the thickness Tp1 of the planarization layer IPL has a value that is less than about 50% or greater than about 150% of the height difference Hd of the interlayer dielectric layer ILD, the display device 10 can have reliability defects.

[0176] In some embodiments, the planarization layer IPL may include an upper surface p1 facing a third direction DR3. The upper surface p1 of the planarization layer IPL may be coplanar with the first surface d1 of the interlayer dielectric layer ILD. For example, the height of the upper surface p1 of the planarization layer IPL from the top surface of the substrate SUB may be substantially the same as the height of the first surface d1 of the interlayer dielectric layer ILD from the top surface of the substrate SUB. For example, the upper surface p1 of the planarization layer IPL may extend from the first surface d1 of the interlayer dielectric layer ILD (e.g., in the first direction DR1). In embodiments, the interlayer dielectric layer ILD and the planarization layer IPL may form flat surfaces on a third direction DR3.

[0177] In some embodiments, the planarization layer IPL may cover the second side surface d7 of the interlayer dielectric layer ILD.

[0178] As described above, the planarization layer IPL may include inorganic materials. The planarization layer IPL may contain the same material as the interlayer dielectric layer ILD, or it may contain a different material from the interlayer dielectric layer ILD.

[0179] The second buffer layer BF2 can be configured to be in direct contact with the interlayer dielectric layer ILD and the planarization layer IPL (such as the upper surfaces of the interlayer dielectric layer ILD and the planarization layer IPL). According to embodiments of the present disclosure, the second buffer layer BF2 can be formed substantially flat due to its placement on the planarization layer IPL.

[0180] Figure 9 and Figure 10 According to the embodiments Figure 7 An enlarged cross-sectional view of region A.

[0181] refer to Figure 9 and combined Figures 1 to 8 ,exist Figure 9 The planarization layer IPL included in the display device 10s may have a different shape than the planarization layer IPL included in the display device 10. In the following description, the common structures included in the display device 10s and the display device 10s may not be described, and for the sake of brevity, the description will focus on the differences.

[0182] In some embodiments, the planarization layer IPL included in the display device 10s may cover the first side surface d5 and the second surface d3 of the interlayer dielectric layer ILD.

[0183] In some embodiments, the planarization layer IPL included in the display device 10s may include an upper surface p3. The upper surface p3 of the planarization layer IPL may be recessed toward the first conductive layer CDL1 in a third direction DR3 (e.g., in a direction perpendicular to the upper surface of the substrate SUB) and disposed at a height lower than the first surface d1 of the interlayer dielectric layer ILD. Accordingly, the planarization layer IPL included in the display device 10s may expose a portion of the second side surface d7 of the interlayer dielectric layer ILD.

[0184] According to some embodiments, the thickness Tp3 of the planarization layer IPL included in the display device 10s can have a value in the range of about 50% to about 100% of the height difference Hd of the interlayer dielectric layer ILD.

[0185] For example, if the thickness Tp3 of the planarization layer IPL has a value that is less than about 50% of the height difference Hd of the interlayer dielectric layer ILD, then the display device 10s may have a reliability defect.

[0186] According to embodiments of this disclosure, the planarization layer IPL can be formed to completely cover the interlayer dielectric layer ILD, and then formed via a subsequent etching process during the manufacturing process of the display device 10s, as shown in the figure. Figure 9 The shape shown.

[0187] refer to Figure 10 and combined Figures 1 to 8 ,exist Figure 10 The planarization layer IPL included in the display device 10p may have a different shape than the planarization layer IPL included in the display device 10. For the sake of brevity, common structures included in the display device 10 and the display device 10s will not be described in the following description, and the description will focus on the differences.

[0188] In some embodiments, the planarization layer IPL included in the display device 10p may cover the first side surface d5, the second surface d3, and the second side surface d7 of the interlayer dielectric layer ILD.

[0189] In some embodiments, the planarization layer IPL included in the display device 10p may include an upper surface p5. The upper surface p5 of the planarization layer IPL may protrude toward one side in a third direction DR3 (e.g., in a direction perpendicular to the upper surface of the substrate SUB) and be at a height greater than the height of the first surface d1 of the interlayer dielectric layer ILD.

[0190] According to some embodiments, a thickness Tp5 of the planarization layer IPL included in the display device 10p can have a value in a range of about 100% to about 150% of the height difference Hd of the interlayer dielectric layer ILD.

[0191] For example, if the value of the thickness Tp5 of the planarization layer IPL is greater than 150% of the height difference Hd of the interlayer dielectric layer ILD, the display device 10p can have reliability defects.

[0192] According to embodiments of the present disclosure, the planarization layer IPL can be formed to completely cover the interlayer dielectric layer ILD and then formed to a shape as shown in FIG. 1A via a subsequent etching process during a process of manufacturing the display device 10p. Figure 10

[0193] Figure 11 is a plan view of the region C. Figure 7

[0194] Referring to Figure 11 and in conjunction with Figure 7 , in a plan view of Figure 11 , the planarization layer IPL can define the opening OPp and expose the interlayer dielectric layer ILD through the opening OPp. For example, when viewed from the top, the planarization layer IPL can be in the form of a single pattern that completely surrounds the opening OPp.

[0195] When viewed from the top, the interlayer dielectric layer ILD and the gate electrode GE can be located in the opening OPp. When viewed from the top, the interlayer dielectric layer ILD can completely cover the gate electrode GE.

[0196] When viewed from the top, the planarization layer IPL can not overlap the gate electrode GE and can completely surround the gate electrode GE. When viewed from the top, the planarization layer IPL can be spaced apart from the gate electrode GE. When viewed from the top, the interlayer dielectric layer ILD can be disposed between the gate electrode GE and the planarization layer IPL that are spaced apart from each other. In embodiments, when viewed from the top, the planarization layer IPL can completely surround a first conductive layer CDL1, such as a pattern of separate conductive islands that can include the gate electrode GE, the first conductive portion CP1, and the second conductive portion CP2.

[0197] Figure 12 is a cross-sectional view showing an embodiment of a display layer taken along a line X-X' of Figure 6 .

[0198] Referring to Figure 12 and in conjunction with Figures 1 to 11 ​​In an embodiment, the display layer DPL of the display device 10q can include a substrate SUB, a transistor layer TFTL, a display element layer EML, and a thin film encapsulation layer TFEL. The transistor layer TFTL included in the display device 10q can include a plurality of planarization layers stacked with each other in the third direction DR3. For the sake of saving explanation, in the following description, the common structures included in the display device 10q as well as the display device 10 will not be described, and the description will be focused on the differences.

[0199] The transistor layer TFTL can be disposed on the substrate SUB (e.g., directly on the substrate SUB in the third direction DR3). In an embodiment, the transistor layer TFTL included in the display device 10q can include a first buffer layer BF1, a transistor TFT, a gate insulator GI, a first planarization layer IPL1, a first conductive layer CDL1, an interlayer dielectric layer ILD, a second planarization layer IPL2, a second buffer layer BF2, a second conductive layer CDL2, a first via layer VIA1, a third planarization layer IPL3, a third conductive layer CDL3, a second via layer VIA2, and a fourth planarization layer IPL4.

[0200] The gate insulator GI can be disposed on (e.g., directly on) the transistor TFT. The gate insulator GI can cover a height difference formed by the transistor TFT and the first buffer layer BF1 with a uniform thickness. Accordingly, the gate insulator GI can have the height difference.

[0201] The first planarization layer IPL1 can be disposed on (e.g., directly on, in the third direction DR3) the gate insulator GI. The first planarization layer IPL1 can provide a planar surface over the gate insulator GI. The first planarization layer IPL1 can define an opening, and the first planarization layer IPL1 can expose the gate insulator GI through the opening. For example, the first planarization layer IPL1 can surround (e.g., in a plan view) the gate insulator GI.

[0202] The first planarization layer IPL1 can include an inorganic insulating material. For example, in an embodiment, the first planarization layer IPL1 can include silicon nitride (e.g., Si3N4 or SiN x ), silicon oxide (e.g., SiO x such as SiO2), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating materials.

[0203] A second planarization layer IPL2 can be disposed on (e.g., directly on) the interlayer dielectric layer ILD. The second planarization layer IPL2 can provide a planar surface over the interlayer dielectric layer ILD. The second planarization layer IPL2 can have the same structure and features as the planarization layer IPL included in the display device 10. Redundant descriptions are omitted for the sake of saving explanation.

[0204] The third conductive portion CP3 and the fourth conductive portion CP4 included in the second conductive layer CDL2 can be a conductive pattern including a conductive material. The conductive pattern described above can refer to a pattern of separate conductive islands.

[0205] The third conductive portion CP3 and the fourth conductive portion CP4 included in the second conductive layer CDL2 can be located on the same plane in the first direction DR1. For example, the third conductive portion CP3 and the fourth conductive portion CP4 can have the same height from the top surface of the substrate SUB (e.g., in the third direction DR3). The third conductive portion CP3 and the fourth conductive portion CP4 can be spaced apart from each other (e.g., in the first direction DR1). For example, a plurality of conductive patterns can be located on the second buffer layer BF2, and the conductive patterns can be spaced apart from each other in the first direction DR1.

[0206] The first via layer VIA1 can be located on the second buffer layer BF2 (e.g., directly disposed on the second buffer layer BF2 in the third direction DR3) and can completely cover the third conductive portion CP3 and the fourth conductive portion CP4 included in the second conductive layer CDL2. The first via layer VIA1 can cover with a uniform thickness along the height difference formed by the second conductive layer CDL2 and the second buffer layer BF2. Accordingly, the first via layer VIA1 can have a height difference.

[0207] The third planarization layer IPL3 can be disposed on (e.g., directly on) the first via layer VIA1. The third planarization layer IPL3 can provide a planar surface over the first via layer VIA1. The third planarization layer IPL3 can define an opening, and the third planarization layer IPL3 can expose the first via layer VIA1 through the opening. For example, the third planarization layer IPL3 can surround (e.g., in a plan view) the first via layer VIA1.

[0208] The third planarization layer IPL3 can include an inorganic insulating material. For example, in an embodiment, the third planarization layer IPL3 can include silicon nitride (e.g., SiN i3 N4or SiN x ), silicon oxide (e.g., SiO xsilicon nitride (e.g., Si3N4or SiN x ), silicon oxide (e.g., SiO x ), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating material.

[0209] The third conductive layer CDL3 can be a conductive pattern including a conductive material. The conductive pattern described above can refer to a pattern of separate conductive islands.

[0210] The second via layer VIA2 can be disposed on (e.g., directly on in the third direction DR3) the first via layer VIA1 and can cover the third conductive layer CDL3. The second via layer VIA2 can cover along the height difference formed by the third conductive layer CDL3 and the first via layer VIA1 with a uniform thickness. Accordingly, the second via layer VIA2 can have a height difference.

[0211] The fourth planarization layer IPL4 can be disposed on (e.g., directly on) the second via layer VIA2. The fourth planarization layer IPL4 can provide a planar surface over the second via layer VIA2. The fourth planarization layer IPL4 can define an opening, and the fourth planarization layer IPL4 can expose the second via layer VIA2 through the opening. For example, the fourth planarization layer IPL4 can surround (e.g., in a plan view) the second via layer VIA2.

[0212] The fourth planarization layer IPL4 can include an inorganic insulating material. For example, in an embodiment, the fourth planarization layer IPL4 can include silicon nitride (e.g., Si3N4or SiN x ), silicon oxide (e.g., SiO x ), silicon oxynitride (e.g., SiON), titanium oxide, aluminum oxide, or other inorganic insulating material.

[0213] The display element layer EML and the thin film encapsulation layer TFEL included in the display device 10q can be the same as the display element layer EML and the thin film encapsulation layer TFEL included in the display device 10; and thus, to save explanation, redundant descriptions will be omitted.

[0214] The display device 10q includes a plurality of planarization layers IPL capable of providing a planar surface for a height difference formed by a plurality of conductive patterns, thereby reducing reliability defects caused by the height difference in the display device 10q.

[0215] Figure 13 is a flowchart for illustrating a method for manufacturing a transistor layer in Figure 7 .

[0216] Reference is made to Figure 13 in conjunction with Figure 7According to the method (method S1) for manufacturing the display device 10 according to the embodiment, the step S100 of forming the first conductive layer on the gate insulator covering the transistor and then forming the interlayer dielectric layer on the first conductive layer can include: forming the first conductive layer on the gate insulator covering the transistor (step S101); and forming the interlayer dielectric layer on the first conductive layer (step S102).

[0217] Figure 14 and Figure 15 is a cross-sectional view illustrating the step S100 of Figure 13

[0218] Referring to Figure 14 and Figure 15 The step S100 will be described, which includes forming the first conductive layer on the gate insulator covering the transistor and then forming the interlayer dielectric layer on the first conductive layer.

[0219] Initially, the transistor TFT is disposed on the first buffer layer BF1 (e.g., directly on the first buffer layer BF1 in the third direction DR3). In the embodiment, the transistor TFT can be formed via a sputtering deposition process. The transistor TFT can be divided into a plurality of regions having different characteristics from each other. For example, the transistor TFT can include a source region SA, a channel region CH, and a drain region DRA. The source region SA and the drain region DRA can be conductive regions compared to the channel region CH.

[0220] Subsequently, the gate insulator GI is formed on the transistor TFT (e.g., directly on the transistor TFT). The gate insulator GI can completely cover the transistor TFT. For example, the gate insulator GI can completely cover the upper surface and the lateral edges of the transistor TFT.

[0221] In the embodiment, the gate insulator GI can be formed via a process of forming an insulating film using at least one of the above-listed insulating materials (e.g., inorganic insulating materials). The material and / or the method for forming the gate insulator GI can vary according to the embodiment.

[0222] Subsequently, the first conductive layer CDL1 can be formed on the gate insulator GI (e.g., directly on the gate insulator GI in the third direction DR3). In the embodiment, the first conductive layer CDL1 can include a gate electrode GE, a first conductive portion CP1, and a second conductive portion CP2. However, the embodiment of the disclosure is not necessarily limited thereto, and the number of separate conductive islands formed in the conductive layer (such as the first conductive layer CDL1) can vary.

[0223] ​In this process, the gate electrode GE can be formed so that the gate electrode GE overlaps the channel region CH of the transistor TFT in the third direction DR3. In an embodiment, the first conductive portion CP1 can be formed so that the first conductive portion CP1 (e.g., in the third direction DR3) overlaps the source region SA of the transistor TFT, and the second conductive portion CP2 can be formed so that the second conductive portion CP2 (e.g., in the third direction DR3) overlaps the drain region DRA of the transistor TFT.

[0224] In an embodiment, the first conductive layer CDL1 can be formed via a film formation process (e.g., a deposition process) of the conductive film and a patterning process (e.g., an etching process using a mask) of the conductive film. The material and / or the method for forming the first conductive layer CDL1 can vary according to an embodiment. Accordingly, the first conductive layer CDL1 can be formed as a pattern of conductive islands.

[0225] In an embodiment, subsequently, the interlayer dielectric layer ILD is formed on (e.g., directly on) the first conductive layer CDL1. The interlayer dielectric layer ILD can be formed on the entire surface, such as on the entire of the top surface and the lateral edges of the first conductive layer CDL1.

[0226] In this process, the interlayer dielectric layer ILD can cover with a uniform thickness along the height difference formed between the first conductive layer CDL1 and the gate insulator GI. Accordingly, the interlayer dielectric layer ILD can have the height difference Hd. The height difference Hd has been described above, and will not be described again in order to save the explanation.

[0227] In this process, the height difference Hd of the interlayer dielectric layer ILD can be less than or equal to the thickness Tm of the first conductive layer CDL1.

[0228] In an embodiment, the interlayer dielectric layer ILD can be formed via a film formation deposition process using at least one of the above-listed insulating materials (e.g., inorganic insulating materials). However, the material and / or the method for forming the interlayer dielectric layer ILD can vary according to an embodiment.

[0229] Figure 16 is a cross-sectional view illustrating Figure 13 Step S200.

[0230] Referring to Figure 16 Step S200 in which a planarization layer and a sacrificial layer are formed on the interlayer dielectric layer will be described.

[0231] Initially, a planarization layer IPL is formed on (e.g., disposed directly on) the interlayer dielectric layer ILD. The planarization layer IPL can completely cover the interlayer dielectric layer ILD, such as the entirety of the upper surface and lateral side surfaces of the interlayer dielectric layer ILD.

[0232] In this process, the planarization layer IPL can be formed with a uniform thickness along the height difference Hd of the interlayer dielectric layer ILD. Accordingly, the planarization layer IPL can have a height difference.

[0233] In embodiments, the planarization layer IPL can be formed via a deposition process that forms a film of at least one of the above-listed insulating materials (e.g., inorganic insulating materials). The material and / or method used to form the planarization layer IPL can vary according to embodiments.

[0234] In embodiments, subsequently, a sacrificial layer SFL is formed on (e.g., disposed directly on) the planarization layer IPL. The sacrificial layer SFL can completely cover the planarization layer IPL. In this process, the sacrificial layer SFL can provide a planar surface over the planarization layer IPL.

[0235] In embodiments, the sacrificial layer SFL can include an organic material, and can include, for example, polyimide, polyamide, phenol, acrylic, epoxy, and silicone. In embodiments, in addition to the above-listed materials, the sacrificial layer SFL can include any material used in organic photoresist (PR).

[0236] Figure 17 and Figure 18 is a cross-sectional view illustrating Figure 13 step S300.

[0237] Referring to Figure 17 and Figure 18 , a step of removing a portion of the planarization layer and the sacrificial layer (step S300) will be described.

[0238] Initially, an etching process is performed on the sacrificial layer SFL.

[0239] In embodiments, the etching process can be performed using an ashing process and / or a back-etching process. Accordingly, this process can be performed without any mask.

[0240] For example, in embodiments, an ashing process can be first performed to remove the sacrificial layer SFL. This process can be performed using a plasma containing oxygen or oxygen ions. In this process, the sacrificial layer SFL including an organic material can be mostly removed without damaging the planarization layer IPL.

[0241] Subsequently, when a portion of the planarization layer IPL is exposed, a back-etching process is performed. This process can control the etching selectivity between the sacrificial layer SFL and the planarization layer IPL. Accordingly, in this process, the sacrificial layer SFL can be completely removed, while the planarization layer IPL can be partially removed to provide a flat surface over the interlayer dielectric layer ILD having the height difference Hd. In embodiments, the step S300 of removing a portion of the planarization layer IPL and the sacrificial layer SFL can be repeated two or more times, in whole or in part, as needed.

[0242] In this process, the planarization layer IPL can define an opening OPp and expose the interlayer dielectric layer ILD through the opening OPp.

[0243] In this process, a portion of the interlayer dielectric layer ILD in direct contact with the planarization layer IPL can be removed by a back-etching process. Accordingly, the interlayer dielectric layer ILD can include a second side surface d7 connecting the first surface d1 and the first side surface d5. As described above, the second side surface d7 can be a curved surface. For example, the second side surface d7 of the interlayer dielectric layer ILD can mean that the planarization layer IPL is formed by performing a back-etching process in a process of manufacturing the display device 10.

[0244] Reference Figure 18 and in conjunction Figures 8 to 10 In this process, the upper surface p1 of the planarization layer IPL can be on the same plane as the first surface d1 of the interlayer dielectric layer ILD, can protrude from the first surface d1 toward one side in the third direction DR3, or can be recessed from the first surface d1 toward the opposite side in the third direction DR3. Redundant descriptions will be omitted for the sake of illustration.

[0245] In embodiments, the thickness Tp of the planarization layer IPL can have a value in the range of about 50% to about 150% of the height difference Hd of the interlayer dielectric layer. Redundant descriptions will be omitted for the sake of illustration.

[0246] Figure 19 is a cross-sectional view illustrating Figure 13 the step S400.

[0247] Reference Figure 19 A step of forming a second conductive layer on the interlayer dielectric layer and the planarization layer (step S400) will be described.

[0248] Initially, the second buffer layer BF2 is formed on (e.g., disposed directly on) the interlayer dielectric layer ILD and the planarization layer IPL. The second buffer layer BF2 can be in direct contact with the interlayer dielectric layer ILD and the planarization layer IPL. In this process, the second buffer layer BF2 is on the planarization layer IPL, and thus can have a substantially flat film. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some implementations, the display device 10 (see Figure 7 ) can not include the second buffer layer BF2.

[0249] In embodiments, the second buffer layer BF2 can be formed via a deposition process that forms a film of at least one of the above-enumerated insulating materials (e.g., inorganic insulating materials). The material and / or method used to form the second buffer layer BF2 can vary according to embodiments.

[0250] In embodiments, subsequently, a second conductive layer CDL2 is formed on the second buffer layer BF2. In embodiments, the second conductive layer CDL2 can include a third conductive portion CP3 and a fourth conductive portion CP4.

[0251] In embodiments, the third conductive portion CP3 can be connected to the first conductive portion CP1 through a contact hole, and the fourth conductive portion CP4 can be connected to the second conductive portion CP2 through a contact hole.

[0252] In embodiments, the second conductive layer CDL2 can be formed via a film formation process (e.g., a deposition process) of a conductive film and a patterning process (e.g., an etching process using a mask) of the conductive film. However, the material and / or method used to form the second conductive layer CDL2 can vary according to embodiments. Accordingly, the third conductive portion CP3 and the fourth conductive portion CP4 included in the second conductive layer CDL2 can be formed as a pattern of conductive islands.

[0253] In embodiments, subsequently, a first via layer VIA1 covering the second conductive layer CDL2 can be formed. In this process, the first via layer VIA1 can provide a flat surface for a height difference formed between the second conductive layer CDL2 and the second buffer layer BF2.

[0254] In embodiments, the first via layer VIA1 can be formed via a process that applies at least one of the above-enumerated organic materials. However, the material and / or method used to form the first via layer VIA1 can vary according to embodiments.

[0255] In embodiments, a third conductive layer CDL3 can be formed subsequently on the first via layer VIA1. The third conductive layer CDL3 can be connected to the fourth conductive portion CP4 through a contact hole.

[0256] In an embodiment, the third conductive layer CDL3 can be formed via a film formation process (e.g., a deposition process) of a conductive film and a patterning process (e.g., an etching process using a mask) of the conductive film. However, the material and / or method for forming the third conductive layer CDL3 can vary according to an embodiment. Accordingly, the third conductive layer CDL3 can be formed as a pattern of conductive islands.

[0257] In an embodiment, a second via layer VIA2 covering the third conductive layer CDL3 can be subsequently formed. In this process, the second via layer VIA2 can provide a flat surface with respect to a height difference formed between the third conductive layer CDL3 and the first via layer VIA1.

[0258] In an embodiment, the second via layer VIA2 can be formed via a process of applying at least one of the above-enumerated organic materials. However, the material and / or method for forming the second via layer VIA2 can vary according to an embodiment.

[0259] In this way, it is possible to form Figure 7 the transistor layer TFTL shown in FIG. 1B.

[0260] Referring back to Figures 1 to 19 , the display devices 10, 10s, 10p, and 10q according to embodiments of the disclosure include a planarization layer IPL that provides a flat surface over inorganic insulating layers covering a plurality of conductive patterns, thereby reducing reliability defects of the display devices 10, 10s, 10p, and 10q.

[0261] Further, in the display devices 10, 10s, 10p, and 10q according to embodiments of the disclosure, the planarization layer IPL is partially removed via an etching process, and thus a mechanical polishing process (e.g., a CMP process) is not required. As a result, manufacturing costs of the display devices 10, 10s, 10p, and 10q can be saved.

[0262] Further, in the display devices 10, 10s, 10p, and 10q according to embodiments of the disclosure, the planarization layer IPL is partially removed via an etching-back process, and thus a mask is not required. Accordingly, the display devices 10, 10s, 10p, and 10q can be more easily manufactured.

[0263] Figure 20 is a block diagram of an electronic device according to an embodiment of the disclosure.

[0264] Referring to Figure 20 and in conjunction with Figure 1 and Figure 19The display apparatuses 10, 10s, 10p, and 10q according to the embodiments can be applied to various electronic apparatuses 1. The electronic apparatus 1 according to the embodiments can include the display apparatuses 10, 10s, 10p, and 10q described above, and can further include a module or apparatus having an additional function other than the display apparatuses 10, 10s, 10p, and 10q.

[0265] The electronic apparatus 1 according to the embodiments can include a display module 11, a processor 12, a memory 13, and a power module 14.

[0266] In an embodiment, the processor 12 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0267] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, an image data signal and / or an input control signal can be transmitted to the display module 11. The display module 11 can process the received signal and output image information through a display screen.

[0268] In an embodiment, the power module 14 can include a power supply module such as a power adapter and a battery device, and a power conversion module that converts power supplied by the power supply module to generate power necessary for the operation of the electronic apparatus 1.

[0269] At least one element of the electronic apparatus 1 described above can be included in a display apparatus according to the embodiments described above. Furthermore, some of the respective modules functionally included in one module can be included in the display apparatus, and some other modules can be provided separately from the display apparatus. For example, in an embodiment, the display apparatus can include the display module 11, and the processor 12, the memory 13, and the power module 14 can be implemented as other apparatuses within the electronic apparatus 1 rather than within the display apparatus.

[0270] Figure 21 is a view showing an electronic apparatus according to a plurality of embodiments of the disclosure.

[0271] Reference Figure 21 , the display apparatus 10 according to the embodiments (see Figure 7The various electronic devices 1 of the embodiments described herein (e.g., the embodiments of FIGS. 1A-1C) can include not only image display electronic devices such as a smartphone 10 la, a tablet PC 10 lb, a laptop computer 10 lc, a TV 10 ld, and a desktop monitor 10 le, but also wearable electronic devices including a display module such as smart glasses 10 2a, a head-mounted display 10 2b, and a smart watch 10 2c, and electronic devices for vehicles 10 3 such as a central information display (CID) placed on an instrument panel, a center console and an instrument panel of a vehicle, and an interior mirror display.

[0272] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display device, wherein, The display device includes: a substrate over which a transistor is provided; a gate insulator provided over the transistor; a conductive layer provided over the gate insulator, a plurality of conductive patterns of the conductive layer being spaced apart from each other; an interlayer dielectric layer provided over the plurality of conductive patterns, the interlayer dielectric layer including an inorganic material; and a planarization layer provided over the interlayer dielectric layer and defining a plurality of openings that expose the interlayer dielectric layer, wherein the planarization layer includes an inorganic material.

2. The display device according to claim 1, wherein Each of the plurality of conductive patterns overlaps with one of the plurality of openings of the planarization layer.

3. The display device according to claim 2, wherein In a plan view, the planarization layer is provided between adjacent ones of the plurality of conductive patterns.

4. The display device according to claim 3, wherein: the plurality of conductive patterns include a conductive metal; and the plurality of conductive patterns are provided on the same layer and upper surfaces of the plurality of conductive patterns are located on the same plane.

5. The display device of claim 4, wherein, Each of the plurality of conductive patterns has an island shape.

6. The display device according to claim 1, wherein: the interlayer dielectric layer is provided over the entire substrate; and the interlayer dielectric layer is in direct contact with all of upper surfaces and lateral side surfaces of the plurality of conductive patterns to cover the plurality of conductive patterns, wherein the interlayer dielectric layer has a difference in height between a portion not overlapping with the plurality of openings and a portion overlapping with the plurality of openings, and wherein a thickness of the planarization layer is within a range of 50 % to 150 % of the difference in height of the interlayer dielectric layer.

7. The display device according to claim 1, wherein: the interlayer dielectric layer includes a first surface provided in the plurality of openings and located on an opposite side of a surface of the interlayer dielectric layer that is in direct contact with the plurality of conductive patterns; the planarization layer includes an upper surface that is higher than upper surfaces of the plurality of conductive patterns.

8. The display device of claim 7, wherein, the upper surface of the planarization layer is located on the same plane as the first surface of the interlayer dielectric layer.

9. The display device according to claim 7, wherein the upper surface of the planarization layer is lower than the first surface of the interlayer dielectric layer in a direction perpendicular to an upper surface of the substrate.

10. The display device of claim 7, wherein, the upper surface of the planarization layer is higher than the first surface of the interlayer dielectric layer in a direction perpendicular to an upper surface of the substrate.

11. The display device according to claim 1, wherein In a plan view, the planarization layer is arranged in a pattern that completely surrounds the plurality of openings, wherein: in the plan view, the plurality of conductive patterns are respectively located in the plurality of openings; in the plan view, the plurality of conductive patterns and the planarization layer are spaced apart from each other; and in the plan view, the planarization layer completely surrounds the plurality of conductive patterns, wherein: in the plan view, the interlayer dielectric layer completely covers the plurality of conductive patterns in the plurality of openings; and the interlayer dielectric layer is located between the planarization layer and the plurality of conductive patterns.

12. A method for manufacturing a display device, wherein, The method includes: forming a conductive layer having a plurality of conductive patterns over a gate insulator covering a transistor, and then forming an interlayer dielectric layer over the plurality of conductive patterns; forming a planarization layer and a sacrificial layer on the interlayer dielectric layer; and removing a portion of the planarization layer and the sacrificial layer, wherein the removing the portion of the planarization layer and the sacrificial layer includes removing the portion of the planarization layer and the sacrificial layer via an etching process including an etch-back process.

13. The method of claim 12, wherein, The forming the interlayer dielectric layer on the plurality of conductive patterns includes forming the interlayer dielectric layer such that the interlayer dielectric layer completely covers the plurality of conductive patterns and the interlayer dielectric layer has a uniform thickness with a manufacturing error less than or equal to 10%.

14. The method of claim 12, wherein: the planarization layer includes an inorganic material; and the sacrificial layer includes an organic material.

15. The method of claim 14, wherein, The planarization layer defines a plurality of openings, and the planarization layer exposes the interlayer dielectric layer through the plurality of openings.

16. An electronic device, wherein, The electronic device includes: at least one display device including a substrate on which a transistor is disposed; a display device housing accommodating the at least one display device; and an optical member magnifying a display image of the at least one display device or converting an optical path, wherein the at least one display device includes: a gate insulator disposed on the transistor; a plurality of conductive patterns disposed on the gate insulator and spaced apart from each other; an interlayer dielectric layer disposed on the plurality of conductive patterns, the interlayer dielectric layer including an inorganic material; and a planarization layer disposed on the interlayer dielectric layer and defining a plurality of openings exposing the interlayer dielectric layer; wherein the planarization layer includes an inorganic material. 17.The electronic device of claim 16, wherein, Each of the plurality of conductive patterns overlaps with a corresponding one of the plurality of openings of the planarization layer. 18.The electronic device of claim 17, wherein, In a plan view, the planarization layer is disposed between adjacent ones of the plurality of conductive patterns.

19. The electronic device of claim 18, wherein: the plurality of conductive patterns include a conductive metal; and the plurality of conductive patterns are disposed on the same layer as each other and upper surfaces of the plurality of conductive patterns lie on the same plane. 20.The electronic device of claim 19, wherein, Each of the plurality of conductive patterns has an island shape.

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