A clock signal frequency detection circuit

Abstract

The embodiment of the present application discloses a clock signal frequency detection circuit, which comprises a first edge pulse generator, a first latch, a switch module, a time length comparison module and a second edge pulse generator. The first edge pulse generator is used for generating a first clock edge pulse signal according to the edge of a clock signal to be detected. The first latch is used for receiving the first clock edge pulse signal and generating a first control signal according to the first clock edge pulse signal. The switch module is turned on or turned off according to the first control signal. The time length comparison module is used for comparing the period of the first clock edge pulse signal with a reference time and outputting a comparison result. The second edge pulse generator is used for generating a second clock edge pulse signal according to the edge of the comparison result. The technical scheme of the embodiment of the present application realizes low-power clock signal frequency detection by starting the time length comparison module at the edge of the clock signal to be detected and stopping the time length comparison module after comparison.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a clock signal frequency detection circuit. Background Technology

[0002] In low-power sensor applications such as portable audio devices and wearable electronic devices, the enable pin of the chip may be omitted due to the limited number of pins. Often, the presence or absence of a clock input, or the clock frequency, is used to enable the chip. When there is no clock or the frequency is low, the chip needs to stop working and enter an extremely low-power standby state. Only when the clock frequency exceeds a certain threshold does the chip enter normal operating mode. Currently, the common practice is to keep the chip continuously powered on. However, this approach is clearly unsuitable for applications that are extremely sensitive to power consumption. Summary of the Invention

[0003] This invention provides a clock signal frequency detection circuit to achieve low-power clock signal frequency detection.

[0004] According to one aspect of the present invention, a clock signal frequency detection circuit is provided, comprising:

[0005] A first edge pulse generator is used to generate a first clock edge pulse signal based on the edge of the clock signal under test. The input terminal of the first edge pulse generator is connected to the clock signal under test.

[0006] A first latch, wherein the set terminal of the first latch is connected to the output terminal of the first edge pulse generator, the first latch is used to receive the first clock edge pulse signal and generate a first control signal according to the first clock edge pulse signal;

[0007] A switching module, wherein the input terminal of the switching module is connected to a power signal, and the control terminal of the switching module is connected to the output terminal of the first latch, and the switching module is used to turn on or off according to the first control signal;

[0008] A time length comparison module is provided, wherein the first input terminal of the time length comparison module is connected to the output terminal of the first edge pulse generator, and the second input terminal of the time length comparison module is connected to the output terminal of the switch module. The time length comparison module is used to compare the period of the first clock edge pulse signal with the reference time and output the comparison result.

[0009] A second edge pulse generator is configured to generate a second clock edge pulse signal based on the edge of the comparison result. The input of the second edge pulse generator is connected to the output of the time length comparison module, and the output of the second edge pulse generator is connected to the reset terminal of the first latch.

[0010] Optionally, a second latch is also included, wherein a first terminal of the second latch is connected to the clock signal under test, and a second terminal of the second latch is connected to the output terminal of the first latch. The second latch is used to latch and output the final latched output signal.

[0011] Optionally, the time length comparison module includes a bias circuit, a primary comparison circuit, a second-stage comparison circuit, and a reference setting circuit;

[0012] The first terminal of the bias circuit is connected to the output terminal of the switching module, and the second terminal of the bias circuit is connected to the ground terminal. The first terminal of the primary comparator circuit is connected to the output terminal of the switching module, and the second terminal of the primary comparator circuit is connected to the third terminal of the bias circuit. The first terminal of the second-stage comparator circuit is connected to the output terminal of the switching module, and the second terminal of the second-stage comparator circuit is connected to the third terminal of the primary comparator circuit. The third terminal of the second-stage comparator circuit is connected to the fourth terminal of the primary comparator circuit, and the fourth terminal of the second-stage comparator circuit is connected to the second edge pulse generator. The fifth terminal of the second-stage comparator circuit is connected to the ground terminal. The first terminal of the reference setting circuit is connected to the fifth terminal of the primary comparator circuit, and the second terminal of the reference setting circuit is connected to the ground terminal. The third terminal of the reference setting circuit is connected to the sixth terminal of the primary comparator circuit, and the fourth terminal of the reference setting circuit is connected to the ground terminal. The bias circuit is used to establish a bias current.

[0013] The primary comparison circuit receives the output signal from the reference setting circuit and amplifies it initially to increase the bias of the reference setting circuit; the second-stage comparison circuit further amplifies the initially amplified signal and outputs the comparison result; the reference setting circuit generates the reference time.

[0014] Optionally, the bias circuit includes a first resistor, a first transistor, and a second transistor;

[0015] The first end of the first resistor is connected to the output end of the switching module, the second end of the first resistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the first transistor is connected to the first terminal of the first transistor, their common connection point is connected to the second end of the primary comparator circuit, the second terminal of the second transistor is connected to the ground terminal, and the gate of the second transistor is connected to the first terminal of the second transistor.

[0016] Optionally, the primary comparator circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0017] The first terminal of the third transistor is connected to the output terminal of the switching module, the first terminal of the fourth transistor is connected to the output terminal of the switching module, the second terminal of the third transistor is connected to the first terminal of the fifth transistor, their common terminal is connected to the third terminal of the second-stage comparator circuit, the gate of the third transistor is connected to the gate of the fourth transistor, their common connection point is connected to the second terminal of the fourth transistor and the second terminal of the second-stage comparator circuit, the second terminal of the fourth transistor is connected to the first terminal of the sixth transistor, their common connection point is connected to the third terminal of the bias circuit, the gate of the sixth transistor is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to the first terminal of the reference setting circuit, and the second terminal of the fifth transistor is connected to the third terminal of the reference setting circuit.

[0018] Optionally, the size ratio of the third transistor to the fourth transistor is equal to the size ratio of the fifth transistor to the sixth transistor.

[0019] Optionally, the reference setting circuit includes a second resistor, a first capacitor, and a seventh transistor;

[0020] The first end of the second resistor is connected to the fifth end of the primary comparator circuit, the second end of the second resistor is connected to the ground terminal, the first end of the first capacitor is connected to the sixth end of the primary comparator circuit, the second end of the first capacitor is connected to the ground terminal, the first terminal of the seventh transistor is connected to the first end of the first capacitor, the second terminal of the seventh transistor is connected to the second end of the first capacitor, and the gate of the seventh transistor is connected to the output terminal of the first edge pulse generator.

[0021] Optionally, the time base set by the reference setting circuit is:

[0022] ;

[0023] in, Let be the capacitance value of the first capacitor. is the resistance value of the second resistor, and m is the size ratio of the third transistor to the fourth transistor.

[0024] Optionally, the second-stage comparator circuit includes an eighth transistor and a ninth transistor;

[0025] The first terminal of the eighth transistor is connected to the output terminal of the switching module, the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is connected to the ground terminal, the gate of the eighth transistor is connected to the third terminal of the primary comparator circuit, and the gate of the ninth transistor is connected to the fourth terminal of the primary comparator circuit.

[0026] Optionally, the switching module includes a PMOS transistor, the first terminal of which is connected to a power supply signal, the gate of which is connected to the output terminal of the first latch, and the second terminal of which is connected to the second input terminal of the time length comparison module.

[0027] The technical solution of this invention uses a first edge pulse generator to detect the edge of the clock signal under test and generate a first clock edge pulse signal. A first latch controls the on / off state of a switching module, and a time length comparison module compares the period of the clock signal under test with an internal reference time. A second edge pulse generator resets the first latch, thus achieving periodic determination of the frequency of the clock signal under test. In this embodiment, the time length comparison module is activated at the edge of the clock signal under test and deactivated after comparison, achieving low-power clock signal frequency detection.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a digital frequency detection circuit in related technologies;

[0031] Figure 2 This is a schematic diagram of a frequency detection circuit based on delay comparison in related technologies;

[0032] Figure 3 This is a schematic diagram of the result of a frequency detection circuit based on delay comparison in related technologies;

[0033] Figure 4 This is a schematic diagram of a low-power clock frequency detection circuit in the prior art;

[0034] Figure 5 This is a schematic diagram of a clock signal frequency detection circuit provided in an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of another clock signal frequency detection circuit provided in an embodiment of the present invention;

[0036] Figure 7 This is a circuit schematic diagram of a time length comparison module provided in an embodiment of the present invention;

[0037] Figure 8 This is a circuit diagram of a clock signal frequency detection circuit provided in an embodiment of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0040] Figure 1 This is a schematic diagram of a digital frequency detection circuit in related technologies, such as... Figure 1As shown, a digital frequency detection circuit includes a standard clock, a gated counter, a comparator, and a latch. Detection is achieved by comparing the counter value with a reference value within a certain time interval. However, a standard clock requires additional power and is difficult to obtain. Figure 2 This is a schematic diagram of a frequency detection circuit based on delay comparison in related technologies, such as... Figure 2 As shown, the frequency detection circuit based on delay comparison includes a sawtooth wave generator, a reference voltage generator, a comparator, and a latch. Figure 3 This is a schematic diagram of a frequency detection circuit based on delay comparison in related technologies. The frequency detection circuit based on delay comparison can convert a clock signal into a sawtooth wave of the same frequency. For example... Figure 3 As shown, relative to reference value 1, the sawtooth wave does not exceed reference value 1, so the comparator output is high. Relative to reference value 2, the sawtooth wave exceeds reference value 2, therefore the comparator output is a pulse signal. Since the slope of the sawtooth wave is fixed, its amplitude is proportional to its period. Setting the frequency by setting a voltage reference value or the slope of the sawtooth wave obviously requires generating additional reference voltage and current, and the reference and comparison need to be continuous.

[0041] Figure 4 Here is a schematic diagram of a low-power clock frequency detection circuit in the prior art. Figure 4 As shown, the low-power clock frequency detection circuit includes a system clock terminal CLK, a system enable terminal EN, a clock enable circuit 20, a frequency sampling circuit 21, a charge pump 22, a comparator 23, and an output stage 24. The clock enable circuit 21 consists of a first AND gate T1, whose two inputs are connected to the system clock terminal CLK and the system enable terminal EN, respectively. The frequency sampling circuit 21 includes a first D flip-flop T2, a second D flip-flop T3, a second AND gate T4, a first OR gate T5, and a delay unit DELAY. VDD is high. The charge pump 22 consists of a charging current source T6, a charging switch S1, a discharging switch S2, and a capacitor C. VREF is the reference voltage. The output stage 24 includes a third D flip-flop T8 and a second OR gate T9. Both the charge pump 22 and the comparator 23 require additional circuitry and need to operate continuously.

[0042] In view of this, Figure 5 This is a schematic diagram of a clock signal frequency detection circuit provided in an embodiment of the present invention. This embodiment is suitable for clock frequency detection with high power consumption requirements. Figure 5 As shown, the circuit includes:

[0043] A first edge pulse generator 101 is connected to the input of the clock signal CLK to be measured, and is used to generate a first clock edge pulse signal based on the edge of the clock signal CLK. A first latch 102 is connected to the output of the first edge pulse generator 101, and is used to receive the first clock edge pulse signal and generate a first control signal based on the first clock edge pulse signal. A switch module 103 is connected to the input of a power supply signal, and its control terminal is connected to the output of the first latch 102. The switch module 103 is used to turn on or off according to the first control signal. Disconnect; Time length comparison module 104, the first input terminal of time length comparison module 104 is connected to the output terminal of first edge pulse generator 101, the second input terminal of time length comparison module 104 is connected to the output terminal of switch module 103, time length comparison module 104 is used to compare the period of first clock edge pulse signal with reference time and output comparison result; Second edge pulse generator 105, the input terminal of second edge pulse generator 105 is connected to the output terminal of time length comparison module 104, the output terminal of second edge pulse generator 105 is connected to the reset terminal of first latch 102, second edge pulse generator 105 is used to generate second clock edge pulse signal according to the edge of comparison result.

[0044] The first edge pulse generator 101 detects the edge of the clock signal CLK under test and generates a pulse signal, namely the first clock edge pulse signal. This first clock edge pulse signal can be generated when the rising edge of the clock signal CLK is detected, or when the falling edge of the clock signal CLK is detected. The width of the first clock edge pulse signal is very narrow, but its period is the same as the period of the clock signal CLK under test. The first latch 102 can be an RS latch. The set terminal of the first latch 102 is connected to the output terminal of the first edge pulse generator 101 and can receive the first clock edge pulse signal. The reset terminal of the first latch 102 is connected to the output terminal of the second edge pulse generator 105 and can receive the second clock edge pulse signal. When the set terminal input is 1, the first latch 102 outputs 1; when the reset terminal input is 1, the first latch 102 outputs 0; when both the reset and set terminal inputs are 0, the first latch 102 retains the original data.

[0045] The switching module 103 can be a switch or an enable terminal of the time-length comparison module 104. It can receive a first control signal output from the first latch 102 and turn on or off according to the first control signal. For example, when the first control signal is high, the switching module 103 can be turned on, transmitting the power supply voltage to the output terminal; when the first control signal is low, the switching module 103 can be turned off. The first input terminal of the time-length comparison module 104 can receive a first clock edge pulse signal, and the second input terminal can receive the power supply voltage output from the switching module 103. The time-length comparison module 104 only starts comparison operation when it receives the power supply voltage. The second edge pulse generator 105 can receive the comparison result output by the time-length comparison module 104. When the second edge pulse generator 105 detects an edge of the comparison result, it generates a short pulse, namely the second clock edge pulse signal, which can be used to reset the first latch 102.

[0046] Specifically, when the frequency of the clock signal CLK under test is relatively low, assuming that the first edge pulse generator 101 detects the rising edge of the clock signal CLK under test and generates a short pulse, setting the first latch 102, the time length comparison module 104 starts working, and the time length comparison module 104 starts comparing the period of the clock signal CLK under test with the reference time. If the period of the clock signal CLK under test is longer than the reference time, the comparison result output by the time length comparison module 104 changes from high level to low level, the second edge pulse generator 105 generates a reset pulse, resetting the first latch 102, the time length comparison module 104 turns off, the comparison ends, and it waits for the arrival of the next edge of the clock signal CLK under test to start a new round of detection. When the frequency of the clock signal CLK under test is relatively high, assuming that the first edge pulse generator 101 detects the rising edge of the clock signal CLK under test and generates a pulse, setting the first latch 102, the time length comparison module 104 starts working. Since the period of the clock signal CLK under test is shorter than the reference time, the comparison result output by the time length comparison module 104 is a continuous high level. The first latch 102 will not reset, and the time length comparison module 104 will continue to work.

[0047] The technical solution of this invention uses a first edge pulse generator to detect the edge of the clock signal under test and generate a first clock edge pulse signal. A first latch controls the on / off state of a switching module, and a time length comparison module compares the period of the clock signal under test with an internal reference time. A second edge pulse generator resets the first latch, thus achieving periodic determination of the frequency of the clock signal under test. In this embodiment, the time length comparison module is activated at the edge of the clock signal under test and deactivated after comparison, achieving low-power clock signal frequency detection.

[0048] In some alternative embodiments of the present invention, reference continues to be made. Figure 5 The clock signal frequency detection circuit also includes a second latch 106. The first terminal of the second latch is connected to the clock signal to be measured, and the second terminal of the second latch 106 is connected to the output terminal of the first latch 102. The second latch 106 is used to latch and output the final latched output signal.

[0049] The second latch 106 can be a low-level enabled latch. The first terminal of the second latch 106 is connected to the clock signal CLK under test, and the second latch 106 is synchronized with the clock signal CLK. The second terminal of the second latch 106 is connected to the output terminal of the first latch 102, and can receive the first control signal from the first latch 102 as the data to be latched. The output terminal of the second latch 106 outputs the frequency detection result. The first latch 102 adopts a "level input, edge latch" latch structure. For example, when the clock signal CLK under test is low, the input of the second latch 106 can be directly transmitted to the output. On the rising edge of the clock, the output result is latched. This ensures that the comparison result can be output promptly even with level input or low-frequency input, while guaranteeing the stability of the output result.

[0050] Figure 6 This is a schematic diagram of another clock signal frequency detection circuit provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 6 As shown, the time length comparison module 104 includes a bias circuit 201, a primary comparison circuit 202, a second-stage comparison circuit 203, and a reference setting circuit 204.

[0051] The first terminal of the bias circuit 201 is connected to the output terminal of the switch module 103, the second terminal of the bias circuit 201 is connected to the ground terminal, the first terminal of the primary comparator circuit 202 is connected to the output terminal of the switch module 103, the second terminal of the primary comparator circuit 202 is connected to the third terminal of the bias circuit 201, the first terminal of the second-stage comparator circuit 203 is connected to the output terminal of the switch module 103, the second terminal of the second-stage comparator circuit 203 is connected to the third terminal of the primary comparator circuit 202, the third terminal of the second-stage comparator circuit 203 is connected to the fourth terminal of the primary comparator circuit 202, the fourth terminal of the second-stage comparator circuit 203 is connected to the second edge pulse generator 105, the fifth terminal of the second-stage comparator circuit 203 is connected to the ground terminal, the first terminal of the reference setting circuit 204 is connected to the fifth terminal of the primary comparator circuit 202, the second terminal of the reference setting circuit 204 is connected to the ground terminal, the third terminal of the reference setting circuit 204 is connected to the sixth terminal of the primary comparator circuit 202, and the fourth terminal of the reference setting circuit 204 is connected to the ground terminal.

[0052] The bias circuit 201 is used to establish the bias current; the primary comparator circuit 202 is used to receive the output signal of the reference setting circuit 201 and perform preliminary amplification, while increasing the bias of the reference setting circuit 201; the second-stage comparator circuit 203 is used to further amplify the preliminary amplified signal and output the comparison result; the reference setting circuit 204 is used to generate the reference time.

[0053] The bias circuit 201 establishes a bias current, providing a stable current for the subsequent primary comparator circuit 202 and the second-stage comparator circuit 203. The first terminal of the bias circuit 201 is connected to the output terminal of the switching module 103; the comparator module 104 will only power on during the entire duration when the switch is on. The second terminal of the bias circuit 201 is connected to ground, forming a current loop. The primary comparator circuit 202 can be a differential amplifier. It can receive a reference voltage from the reference setting circuit 204 and a power supply voltage from the switching module 104. It initially amplifies the difference between the two input voltages and transmits the amplified signal to the second-stage comparator circuit 203. Due to its high gain, even a difference in input voltage only in the millivolt range will result in a significant change in the output. The second-stage comparator circuit 203 receives the signal from the primary comparator circuit 202, amplifies it again, converts the analog voltage signal into a digital level signal, and outputs it to the second edge pulse generator 105. The reference setting circuit 204 may include capacitors and resistors to generate a reference voltage.

[0054] Specifically, when the switching module 103 is turned on, the bias circuit 201 starts working, establishing a stable operating point for the entire module. The reference setting circuit 204 generates a stable reference voltage, determined by the resistor and capacitor of the reference time charging circuit. The capacitor begins charging, the voltage begins to rise, and is sent to the other input of the primary comparator. When the capacitor charging voltage is less than the reference voltage, the primary comparator circuit 202 outputs a low level, which is amplified by the second-stage comparator circuit 203 and kept high by the second edge pulse generator 105. When the capacitor charging voltage is greater than the reference voltage, the primary comparator circuit 201 detects that the capacitor voltage exceeds the reference voltage, the output state of the primary comparator circuit 202 flips, and is transmitted to the second-stage comparator circuit 203. The output of the second-stage comparator circuit 203 jumps from high to low and is transmitted to the second edge pulse generator 105.

[0055] Figure 7 This is a circuit schematic diagram of a time length comparison module provided in an embodiment of the present invention, such as... Figure 7 As shown, in some optional embodiments of the present invention, the bias circuit 201 includes a first resistor R1, a first transistor NM3, and a second transistor NM4;

[0056] The first end of the first resistor R1 is connected to the output end of the switching module 103. The second end of the first resistor R1 is connected to the first terminal of the first transistor NM3. The second terminal of the first transistor NM3 is connected to the first terminal of the second transistor NM4. The gate of the first transistor NM3 is connected to the first terminal of the first transistor NM3. Their common connection point is connected to the second end of the primary comparator circuit 202. The second terminal of the second transistor NM4 is connected to the ground terminal. The gate of the second transistor NM4 is connected to the first terminal of the second transistor NM4.

[0057] In this configuration, the first resistor R1 can be a current-limiting resistor. The first transistor NM3 and the second transistor NM4 can be NMOS transistors. The first terminal of both transistors NM3 and NM4 can be the drain, and the second terminal can be the source. The gate and drain of the first transistor NM3 are connected together to establish the bias voltage and bias current. The gate of the second transistor NM4 is connected to the gate of the first transistor NM3.

[0058] Specifically, when the switching module 104 is turned on, the power supply voltage flows through the first resistor R1 and then into the drain of the first transistor NM3. Since the gate and drain of the first transistor NM3 are connected together, the magnitude of the current is determined by the first resistor R1, the gate voltage of the first transistor NM3, and the gate voltage of the second transistor NM4. The gate of the first transistor NM3 is connected to the gates of the sixth transistor NM2 and the fifth transistor NM1 of the primary comparator circuit 202, providing them with a bias voltage. Thus, the bias current of the sixth transistor NM2 is set to V. GS_NM4 / R0 / n. Where n is the size ratio of the first transistor NM3 and the second transistor NM2, R0 is the resistance value of the reference setting circuit 204, and V... GS_NM4 This is the voltage across the second transistor NM4. The current of the first transistor NM1 is also set to V. GS_NM4 / R0 / n*m. Where m is the size ratio of the fourth transistor P2 and the fifth transistor P1.

[0059] In some alternative embodiments of the present invention, reference continues to be made. Figure 7 The primary comparator circuit 202 includes a third transistor P1, a fourth transistor P2, a fifth transistor NM1, and a sixth transistor NM2;

[0060] The first terminal of the third transistor P1 is connected to the output terminal of the switching module 103. The first terminal of the fourth transistor P2 is connected to the output terminal of the switching module 103. The second terminal of the third transistor P1 is connected to the first terminal of the fifth transistor NM1. Their common terminal is connected to the third terminal of the second-stage comparator circuit 203. The gate of the third transistor P1 is connected to the gate of the fourth transistor P2. Their common connection point is connected to the second terminal of the fourth transistor P2 and the second terminal of the second-stage comparator circuit 203, respectively. The second terminal of the fourth transistor P2 is connected to the first terminal of the sixth transistor NM2. Their common connection point is connected to the third terminal of the bias circuit 201. The gate of the sixth transistor NM2 is connected to the first terminal of the sixth transistor NM2. The second terminal of the sixth transistor NM2 is connected to the first terminal of the reference setting circuit 204. The second terminal of the fifth transistor NM1 is connected to the third terminal of the reference setting circuit 204.

[0061] In this circuit, the third transistor P1 and the fourth transistor P2 can be PMOS transistors, forming a current mirror. The current ratio is m. The fifth transistor NM1 and the sixth transistor NM2 can be NMOS transistors, serving as the input stage of the source input amplifier, receiving the input signal from the reference setting circuit 204. They also increase the current bias for the reference setting circuit 204.

[0062] In some alternative embodiments of the present invention, reference continues to be made. Figure 7 The size ratio of the third transistor P1 to the fourth transistor P2 is equal to the size ratio of the fifth transistor NM1 to the sixth transistor NM2.

[0063] In this circuit, the third transistor P1 and the fourth transistor P2 form a current mirror. The fifth transistor NM1 and the sixth transistor NM2 form the input stage of the source-input amplifier. Clearly, the primary comparator circuit 202 and the reference setting circuit 204 highly integrate amplifier functionality, current biasing functionality, and voltage reference functionality.

[0064] In some alternative embodiments of the present invention, reference continues to be made. Figure 7 The reference setting circuit 204 includes a second resistor R0, a first capacitor C0, and a seventh transistor NM5;

[0065] The first end of the second resistor R0 is connected to the fifth end of the primary comparator circuit 202, and the second end of the second resistor R0 is connected to the ground terminal. The first end of the first capacitor C0 is connected to the sixth end of the primary comparator circuit 202, and the second end of the first capacitor C0 is connected to the ground terminal. The first terminal of the seventh transistor NM5 is connected to the first end of the first capacitor C0, and the second terminal of the seventh transistor NM5 is connected to the second end of the first capacitor C0. The gate of the seventh transistor NM5 is connected to the output terminal of the first edge pulse generator 101.

[0066] The second resistor R0 is connected to the sixth transistor NM2. When the switching module 103 is turned on, the voltage across the second resistor R0 is V. GS_NMS4 The reference voltage input is used as the primary comparator circuit 202. The seventh transistor NM5 can be an NMOS transistor. The first terminal of the seventh transistor NM5 can be the drain, and the second terminal can be the source. The gate of the seventh transistor NM5 is connected to the output terminal of the first edge pulse generator 101. When the first edge pulse generator 101 detects the edge of the clock signal CLK to be measured, it can generate a short pulse, namely the first clock edge pulse signal. The first clock edge pulse signal can briefly turn on the seventh transistor NM5, short-circuit the two ends of the first capacitor C0, and cause the first capacitor C0 to discharge rapidly. After the first clock edge pulse signal ends, the seventh transistor NM5 turns off, and the first capacitor C0 begins to charge.

[0067] In some alternative embodiments of the present invention, reference continues to be made. Figure 7 The time base set by the reference setting circuit 204 is:

[0068] ;

[0069] in, Let C0 be the capacitance value of the first capacitor. R0 is the resistance value of the second resistor, and m is the size ratio of the third transistor P1 to the fourth transistor P2.

[0070] The reference time is determined by the size ratio of the second resistor R0, the first capacitor C0, and the third transistor P1 and the fourth transistor P2. The reference time is independent of the power supply voltage and the parameters of the bias circuit. If the second resistor R0 and the first capacitor C0 are selected as temperature-independent components, the comparison result is temperature-independent, improving voltage and temperature stability. By setting the third transistor P1 and the fourth transistor P2, the time constant can be scaled, reducing the size of the capacitor and resistor, and optimizing area, power consumption, and accuracy.

[0071] For example, the primary comparator circuit 202 generates a self-biased current by utilizing the bias voltage generated by the bias circuit 201. The current flowing through the sixth transistor NM2 is approximately I. R0 =V GS_NM4 / R0; the current flowing through the fifth transistor NM1 is approximately I. R0 =V GS_NM4 / R / m. The size ratio of the third transistor P1 to the fourth transistor P2 is equal to the size ratio of the fifth transistor NM1 to the sixth transistor NM2. Assume the size ratio of the third transistor P1 to the fourth transistor P2 is m. When the comparator delay is negligible, according to the definition of capacitance... and Where Q is the charge of the first capacitor C0, C is the capacitance of the first capacitor C0, V is the voltage across the first capacitor C0, I is the current flowing through the first capacitor C0, and t is time. The comparison time standard is then set as:

[0072] T0 =C0*V GS_NM4 / (V GS_NM4 / R0) / m = C0*R0 / m;

[0073] The reference time depends only on the capacitance of the first capacitor C0, the resistance of the second resistor R0, and the size ratio m of the third transistor P1 to the fourth transistor P2. To amplify the reference time, simply set the size ratio m of the third transistor P1 to the fourth transistor P2 to a decimal. Furthermore, hysteresis can be achieved by changing the values ​​of the first capacitor C0, the second resistor R0, and the size ratio m of the third transistor P1 to the fourth transistor P2 when the output is high and low.

[0074] In the technical solution of this invention, the time length comparison module does not operate continuously. When the frequency is below a threshold, the time length comparison module only operates for a period of time within one cycle. If the frequency is continuous, it is in a turned-off state, thereby saving power consumption. The time length comparison module is independent of power supply voltage and temperature, and can be established quickly; its establishment time does not affect the comparison accuracy. Furthermore, it does not require an additional voltage, current, or frequency reference.

[0075] In some alternative embodiments of the present invention, reference continues to be made. Figure 7 The second-stage comparator circuit 203 includes an eighth transistor P0 and a ninth transistor NM0;

[0076] The first terminal of the eighth transistor P0 is connected to the output terminal of the switching module, the second terminal of the eighth transistor P0 is connected to the first terminal of the ninth transistor NM0, the second terminal of the ninth transistor NM0 is connected to the ground terminal, the gate of the eighth transistor P0 is connected to the third terminal of the primary comparator circuit, and the gate of the ninth transistor NM0 is connected to the fourth terminal of the primary comparator circuit.

[0077] In this circuit, the eighth transistor P0 is a PMOS transistor, and its first terminal can be the drain and its second terminal can be the source. The ninth transistor NM0 is an NMOS transistor, and its first terminal can be the drain and its second terminal can be the source. The second-stage comparator circuit 203 can be a common-source amplifier, which can further amplify and shape the voltage output from the primary comparator circuit 202 into a digital signal, and finally output it to the second edge pulse generator 105.

[0078] In some alternative embodiments of the present invention, reference continues to be made. Figure 7The switching module 103 includes a PMOS transistor. The first terminal of the PMOS transistor is connected to a power supply signal, the gate of the PMOS transistor is connected to the output terminal of the first latch 102, and the second terminal of the PMOS transistor is connected to the second input terminal of the time length comparison module 104.

[0079] In this PMOS transistor, the first terminal can be the source, and the second terminal can be the drain. The gate of the PMOS transistor is the control terminal, connected to the output of the first latch 102, and can receive the first control signal. When the first control signal is high, the voltage difference between the gate and source of the PMOS transistor is zero, and the PMOS transistor is turned off. The time length comparison module 104 is de-energized. When the first control signal is low, the voltage difference between the gate and source of the PMOS transistor is negative, and the PMOS transistor is turned on. The time length comparison module 104 begins to operate.

[0080] Figure 8 This is a circuit schematic diagram of a clock signal frequency detection circuit provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the first edge pulse generator 101 includes a buffer B1 and a first delay unit. The system comprises a first inverter N1 and a first AND gate AND1. A first latch 102 is an RS latch with two inputs, S and R, where S is the set input and R is the reset input, set is the set signal, and rst is the reset signal. It has two outputs, Q and QN, with the ON and ONB logics of Q and QN being opposite. A switching module 103 includes a PMOS transistor whose control terminal is connected to the output QN of the RS latch, and can receive the first control signal ONB. A second edge pulse generator 105 includes a second inverter N2 and a second AND gate AND2. The output of the second AND gate AND2 is connected to the reset terminal R of the RS latch. A second latch 106 can be a level trigger with two inputs, D and EN, where D is the data input and EN is the enable signal input. A second delay circuit is also included before the data input D. The output of the second latch 106 is Q, and the second latch 106 outputs the latched output signal FREQ_HI.

[0081] The basic working principle of this invention is as follows: (Refer to...) Figure 8When the frequency of the clock signal CLK under test is relatively low, the RS latch is set on the rising edge of the clock signal CLK, the switching module 103 is turned on, the power supply to the time length comparison module 104 is turned on, and the voltage across the first capacitor C0 is quickly reset to 0. Then, the comparison between the period of the clock signal CLK under test and the reference time begins. When the period of the clock signal CLK under test is greater than the reference time, the output of the time length comparison module 104 changes from high level to low level, the RS latch is reset, the power supply to the time length comparison module 104 is turned off, and the comparison ends. When the frequency of the clock signal CLK under test is relatively high, the voltage on the first capacitor C0 does not have time to reach the inversion threshold, the time length comparison module 104 does not invert, the output remains high, and the RS latch does not reset. The time length comparison module 104 will continue to work. When the input of the clock signal CLK under test is a continuous high level or low level, the RS latch can be reset regardless of the original output state. If the original output state was low frequency, the RS latch was reset, and the time length comparison module 104 was not working, then there was no condition to set the bit, and the state was maintained. If the original output state was high frequency, the RS latch was set, and the time length comparison module 104 was working, then when the level duration exceeded the set reference time, the detected clock signal CLK under test was low frequency, the RS latch was reset, and the time length comparison module 104 stopped working until a new edge of the clock signal CLK under test arrived.

[0082] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0083] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A clock signal frequency detection circuit, characterized in that, include: A first edge pulse generator is used to generate a first clock edge pulse signal based on the edge of the clock signal under test. The input terminal of the first edge pulse generator is connected to the clock signal under test. A first latch, wherein the set terminal of the first latch is connected to the output terminal of the first edge pulse generator, the first latch is used to receive the first clock edge pulse signal and generate a first control signal according to the first clock edge pulse signal; A switching module, wherein the input terminal of the switching module is connected to a power signal, and the control terminal of the switching module is connected to the output terminal of the first latch, and the switching module is used to turn on or off according to the first control signal; A time length comparison module is provided, wherein the first input terminal of the time length comparison module is connected to the output terminal of the first edge pulse generator, and the second input terminal of the time length comparison module is connected to the output terminal of the switch module. The time length comparison module is used to compare the period of the first clock edge pulse signal with the reference time and output the comparison result. A second edge pulse generator is configured to generate a second clock edge pulse signal based on the edge of the comparison result. The input of the second edge pulse generator is connected to the output of the time length comparison module, and the output of the second edge pulse generator is connected to the reset terminal of the first latch.

2. The clock signal frequency detection circuit according to claim 1, characterized in that, It also includes a second latch, the first terminal of which is connected to the clock signal under test, and the second terminal of which is connected to the output terminal of the first latch. The second latch is used to latch and output the final latched output signal.

3. The clock signal frequency detection circuit according to claim 1, characterized in that, The time length comparison module includes a bias circuit, a primary comparison circuit, a second-stage comparison circuit, and a reference setting circuit; The first terminal of the bias circuit is connected to the output terminal of the switching module, and the second terminal of the bias circuit is connected to the ground terminal. The first terminal of the primary comparator circuit is connected to the output terminal of the switching module, and the second terminal of the primary comparator circuit is connected to the third terminal of the bias circuit. The first terminal of the second-stage comparator circuit is connected to the output terminal of the switching module, and the second terminal of the second-stage comparator circuit is connected to the third terminal of the primary comparator circuit. The third terminal of the second-stage comparator circuit is connected to the fourth terminal of the primary comparator circuit, and the fourth terminal of the second-stage comparator circuit is connected to the second edge pulse generator. The fifth terminal of the second-stage comparator circuit is connected to the ground terminal. The first terminal of the reference setting circuit is connected to the fifth terminal of the primary comparator circuit, and the second terminal of the reference setting circuit is connected to the ground terminal. The third terminal of the reference setting circuit is connected to the sixth terminal of the primary comparator circuit, and the fourth terminal of the reference setting circuit is connected to the ground terminal. The bias circuit is used to establish a bias current. The primary comparison circuit receives the output signal from the reference setting circuit and amplifies it initially to increase the bias of the reference setting circuit; the second-stage comparison circuit further amplifies the initially amplified signal and outputs the comparison result; the reference setting circuit generates the reference time.

4. The clock signal frequency detection circuit according to claim 3, characterized in that, The bias circuit includes a first resistor, a first transistor, and a second transistor; The first end of the first resistor is connected to the output end of the switching module, the second end of the first resistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the first transistor is connected to the first terminal of the first transistor, their common connection point is connected to the second end of the primary comparator circuit, the second terminal of the second transistor is connected to the ground terminal, and the gate of the second transistor is connected to the first terminal of the second transistor.

5. The clock signal frequency detection circuit according to claim 3, characterized in that, The primary comparator circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first terminal of the third transistor is connected to the output terminal of the switching module, the first terminal of the fourth transistor is connected to the output terminal of the switching module, the second terminal of the third transistor is connected to the first terminal of the fifth transistor, their common terminal is connected to the third terminal of the second-stage comparator circuit, the gate of the third transistor is connected to the gate of the fourth transistor, their common connection point is connected to the second terminal of the fourth transistor and the second terminal of the second-stage comparator circuit, the second terminal of the fourth transistor is connected to the first terminal of the sixth transistor, their common connection point is connected to the third terminal of the bias circuit, the gate of the sixth transistor is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to the first terminal of the reference setting circuit, and the second terminal of the fifth transistor is connected to the third terminal of the reference setting circuit.

6. The clock signal frequency detection circuit according to claim 5, characterized in that, The size ratio of the third transistor to the fourth transistor is equal to the size ratio of the fifth transistor to the sixth transistor.

7. The clock signal frequency detection circuit according to claim 5, characterized in that, The reference setting circuit includes a second resistor, a first capacitor, and a seventh transistor; The first end of the second resistor is connected to the fifth end of the primary comparator circuit, the second end of the second resistor is connected to the ground terminal, the first end of the first capacitor is connected to the sixth end of the primary comparator circuit, the second end of the first capacitor is connected to the ground terminal, the first terminal of the seventh transistor is connected to the first end of the first capacitor, the second terminal of the seventh transistor is connected to the second end of the first capacitor, and the gate of the seventh transistor is connected to the output terminal of the first edge pulse generator.

8. The clock signal frequency detection circuit according to claim 7, characterized in that, The time base set by the reference setting circuit is: ； in, Let be the capacitance value of the first capacitor. is the resistance value of the second resistor, and m is the size ratio of the third transistor to the fourth transistor.

9. The clock signal frequency detection circuit according to claim 3, characterized in that, The second-stage comparator circuit includes an eighth transistor and a ninth transistor; The first terminal of the eighth transistor is connected to the output terminal of the switching module, the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is connected to the ground terminal, the gate of the eighth transistor is connected to the third terminal of the primary comparator circuit, and the gate of the ninth transistor is connected to the fourth terminal of the primary comparator circuit.

10. The clock signal frequency detection circuit according to claim 1, characterized in that, The switching module includes a PMOS transistor, the first terminal of which is connected to a power supply signal, the gate of which is connected to the output terminal of the first latch, and the second terminal of which is connected to the second input terminal of the time length comparison module.

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