A servo driver system and a method for diagnosing power switching transistor faults therein

Abstract

This application discloses a servo driver system and its power switch fault diagnosis method. By combining a pre-charging circuit, a three-phase full-bridge rectifier circuit, a digital processing circuit, a PWM pre-drive circuit, an analog load circuit, and a fault diagnosis circuit, the system achieves state detection of the power switch during the pre-charging phase of the driver. The pre-charging circuit includes a DC bus, a pre-charging resistor, and a parallel bypass relay to ensure controlled current during the initial power-on phase. The three-phase full-bridge rectifier circuit provides the complete structural foundation for the power switch. The digital processing circuit, in conjunction with the PWM pre-drive circuit, sequentially drives multiple power switches according to a preset test combination during the pre-charging phase, thereby applying controllable switching operations without closing the bypass relay. The fault diagnosis circuit can simultaneously receive the bus voltage signal and the phase voltage signal, compare the two, and output a diagnostic signal. After the diagnostic signal is fed back to the digital processing circuit, it can determine whether there is an abnormality in the power switch.

Description

Technical Field

[0001] This application relates to the field of servo drive technology, and in particular to a servo drive system and a method for diagnosing faults in its power switching transistors. Background Technology

[0002] Servo drives, as core components in industrial automation and motion control systems, are widely used in CNC machine tools, robots, and intelligent manufacturing equipment. Servo drives use internal power switches (such as MOSFETs and IGBTs) to perform high-frequency switching conversion of the DC bus voltage, thereby driving AC servo motors and achieving precise control of motor torque, speed, and position. As critical actuators in servo drives, power switches operate under conditions of high voltage, high current, and high switching frequency, making them highly susceptible to short circuits, open circuits, or performance degradation. If a power switch fails during drive startup or operation, it can not only lead to abnormal motor control but also cause short circuits in the bus power supply, component burnout, or even equipment damage, seriously threatening the safety and reliability of the system.

[0003] In the prior art, there are some publicly available solutions for fault diagnosis of power switching transistors. For example, although the method disclosed in CN120414436A proposes a detection method, it cannot diagnose abnormal impedance changes in power devices; the method disclosed in CN118914790A is based on current characteristic values ​​for judgment, but it is easily affected by load current fluctuations and has limited accuracy; the method disclosed in CN116381477A requires the DC bus voltage to stabilize before diagnosis can be carried out, and it cannot dynamically follow the bus voltage changes at the initial power-on stage. Moreover, its detection relies on high-voltage analog signals entering the AD module, requiring the use of expensive analog isolation chips; the method disclosed in CN114113994A inevitably generates a large current flowing through the load during the detection process, which may cause motor malfunction; the method disclosed in CN110749811A consumes a large amount of DSP resources during the diagnosis process and does not effectively detect power devices under high voltage, so the accuracy of the diagnostic conclusion cannot be guaranteed; the method disclosed in CN110350484A cannot avoid large current flowing through the load, which still poses a hidden danger to the safety of system operation. In summary, existing technical solutions either have limited diagnostic scope, interfere with the load during detection, or have high hardware costs and resource consumption, making it difficult to simultaneously meet the comprehensive requirements of real-time performance, security, and low cost.

[0004] Therefore, in the pre-charging phase of the servo driver, how to effectively diagnose the faults of the power switching transistors before the relay closes, ensure that no current flows through the load during the detection process to avoid unexpected load actions, and dynamically adapt to changes in the bus voltage has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a servo driver system and a fault diagnosis method for its power switching transistor, aiming to solve the problems that existing technical solutions have limited diagnostic scope, or cause interference to the load during detection, or have high hardware costs and resource consumption, making it difficult to simultaneously meet the comprehensive requirements of real-time performance, safety, and low cost.

[0006] In a first aspect, a servo drive system, the system comprising:

[0007] The system includes a pre-charging circuit, a three-phase full-bridge rectifier circuit, a digital processing circuit, a PWM pre-drive circuit, an analog load circuit, and a fault diagnosis circuit.

[0008] The pre-charging circuit includes a DC bus and a pre-charging resistor connected in series on the DC bus, and a bypass relay connected in parallel on the pre-charging resistor.

[0009] The first terminal of the three-phase full-bridge rectifier circuit is electrically connected to the output terminal of the pre-charging circuit, and the three-phase full-bridge rectifier circuit includes multiple power switching transistors;

[0010] The output terminal of the digital processing circuit is electrically connected to the input terminal of the PWM pre-drive circuit, and the output terminal of the PWM pre-drive circuit is electrically connected to the second terminal of the three-phase full-bridge rectifier circuit. The PWM pre-drive circuit is used to isolate, amplify, and buffer the PWM signal output by the digital processing circuit to obtain a drive signal, and input the drive signal to the three-phase full-bridge rectifier circuit.

[0011] The digital processing circuit is used to drive the multiple power switching transistors through the PWM pre-drive circuit according to a preset PWM test combination during the pre-charge stage when the bypass relay is disconnected and the DC bus is connected to the three-phase full-bridge rectifier circuit via the pre-charge resistor.

[0012] The output terminal of the analog load circuit is electrically connected to the third terminal of the three-phase full-bridge rectifier circuit. The analog load circuit is used to provide a controlled equivalent load during the pre-charge phase.

[0013] The first input terminal of the fault diagnosis circuit is electrically connected to the output terminal of the pre-charge circuit, the second input terminal of the fault diagnosis circuit is electrically connected to the fourth terminal of the PWM pre-drive circuit, and the output terminal of the fault diagnosis circuit is electrically connected to the input terminal of the digital processing circuit. The fault diagnosis circuit is used to receive the bus voltage signal and the phase voltage signal generated by the PWM test combination during the pre-charge stage, compare the bus voltage signal and the phase voltage signal, and output a diagnostic signal to indicate the operating state of the power switch.

[0014] Optionally, in the above scheme, the fault diagnosis circuit includes a first voltage divider network, a second voltage divider network, and a comparison unit;

[0015] The first voltage divider network is used to divide the bus voltage corresponding to the bus voltage signal to generate a first threshold voltage and a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

[0016] The second voltage divider network is used to divide the phase voltage corresponding to the phase voltage signal to generate a sampling voltage;

[0017] The comparison unit includes a first comparator and a second comparator. The first comparator is used to compare the first threshold voltage and the sampled voltage and output a first signal. The second comparator is used to compare the second threshold voltage and the sampled voltage and output a second signal. The first signal and the second signal are combined by logic circuitry to generate the diagnostic signal.

[0018] In the above scheme, optionally, the preset PWM test combination includes multiple preset PWM test items, which are: all bridge arms of the three-phase full-bridge rectifier circuit are turned off, the lower bridge arm of the U phase of the three-phase full-bridge rectifier circuit is turned on individually, the lower bridge arm of the V phase is turned on individually, the lower bridge arm of the W phase is turned on individually, the upper bridge arm of the U phase is turned on individually, the upper bridge arm of the V phase is turned on individually, and the upper bridge arm of the W phase is turned on individually.

[0019] Optionally, in the above scheme, the digital processing circuit internally stores a truth table corresponding to the plurality of preset PWM test items, which is used to compare the diagnostic signal with the expected value of the truth table and determine the fault state of the corresponding power switch based on the comparison result.

[0020] Optionally, in the above scheme, the simulated load circuit includes a resistor network for forming a controlled equivalent load during the pre-charge phase, so as to diagnose the power switching transistor without driving the actual motor.

[0021] Secondly, a method for diagnosing faults in the power switching transistors of a servo driver system, the method comprising:

[0022] During the pre-charge phase, the bypass relay is disconnected, and the DC bus is connected to the three-phase full-bridge rectifier circuit via the pre-charge resistor.

[0023] The digital processing circuit drives multiple power switching transistors of the three-phase full-bridge rectifier circuit sequentially through the PWM pre-drive circuit according to a preset PWM test combination.

[0024] The fault diagnosis circuit receives the bus voltage signal output from the DC bus and the phase voltage signal output from the three-phase full-bridge rectifier circuit, compares the bus voltage signal and the phase voltage signal, and outputs a diagnostic signal; wherein, the diagnostic signal is used to indicate the operating status of the power switch transistor.

[0025] The digital processing circuit compares the diagnostic signal with a pre-stored truth table and determines whether the power switch is faulty based on the comparison result.

[0026] Optionally, in the above scheme, the digital processing circuit sequentially drives multiple power switching transistors of the three-phase full-bridge rectifier circuit through a PWM pre-drive circuit according to a preset PWM test combination, including:

[0027] The digital processing circuit drives all bridge arms of the three-phase full-bridge rectifier circuit to turn off through the PWM pre-drive circuit.

[0028] The digital processing circuit sequentially drives the U-phase lower bridge arm, the V-phase lower bridge arm, and the W-phase lower bridge arm to conduct individually through the PWM pre-drive circuit.

[0029] The digital processing circuit sequentially drives the U-phase upper bridge arm, the V-phase upper bridge arm, and the W-phase upper bridge arm to conduct individually via the PWM pre-drive circuit.

[0030] In the above scheme, optionally, the diagnostic signal output by the fault diagnosis circuit is a single-level signal, and the digital processing circuit compares the diagnostic signal with the expected value in the truth table.

[0031] Compared with the prior art, this application has at least the following beneficial effects:

[0032] Based on further analysis and research of existing technical problems, this application recognizes that existing technical solutions or diagnostic scopes are limited, or there is interference with the load during detection, or the hardware cost and resource consumption are high, making it difficult to simultaneously meet the comprehensive requirements of real-time performance, safety and low cost. By organically combining the pre-charging circuit, three-phase full-bridge rectifier circuit, digital processing circuit, PWM pre-drive circuit, analog load circuit and fault diagnosis circuit, the status detection of power switching transistors is realized in the pre-charging stage of the driver. The pre-charging circuit includes a DC bus, a pre-charging resistor, and a parallel bypass relay to ensure controlled current during the initial power-on phase, preventing surge damage to the devices. A three-phase full-bridge rectifier circuit provides the complete structural foundation for the power switching transistors. The digital processing circuit, in conjunction with the PWM pre-drive circuit, can sequentially drive multiple power switching transistors according to a preset test combination during the pre-charging phase, thus applying controllable switching operations without closing the bypass relay. The analog load circuit provides a controlled equivalent load environment during this phase, preventing the actual motor load from being excited and avoiding unnecessary movement. The fault diagnosis circuit can simultaneously receive the bus voltage signal and the phase voltage signal, compare them, and output a diagnostic signal. This diagnostic signal is fed back to the digital processing circuit to determine if there is any abnormality in the power switching transistors. Therefore, it can be deduced that the system of this application can complete fault detection of the power switching transistors during the pre-charging phase without driving the motor to generate a large current. This avoids catastrophic consequences caused by short circuits, open circuits, or impedance abnormalities in power devices, and also avoids the shortcomings of existing technologies that require voltage stabilization for diagnosis or involve large current flowing through the load during diagnosis. Therefore, the system can effectively detect and locate power device faults in the early stages of power-on, ensuring the safety and reliability of servo drive operation and fundamentally solving the technical problems of diagnostic lag, load malfunction and device damage in the background technology. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a servo driver system framework provided in one embodiment of this application;

[0034] Figure 2 A schematic diagram of a servo driver system provided in one embodiment of this application;

[0035] Figure 3 This application provides a method for diagnosing power switch tube faults in a servo driver system according to one embodiment.

[0036] Figure 4 A waveform diagram illustrating the operating conditions of a servo driver system provided in one embodiment of this application;

[0037] Figure 5 Two waveform diagrams illustrating the operating conditions of a servo driver system provided in one embodiment of this application;

[0038] Figure 6 A three-waveform diagram of the operating conditions of a servo driver system provided in one embodiment of this application;

[0039] Figure 7 Four waveform diagrams illustrating the operating conditions of a servo driver system provided in one embodiment of this application;

[0040] Figure 8 A waveform diagram of the operating conditions of a servo driver system provided in one embodiment of this application;

[0041] Figure 9 For normal power switching transistors, the truth table correspondence between PWM combinations and feedback levels of the fault diagnosis circuit is shown.

[0042] Figure 10 For any single phase short circuit, the truth table correspondence between the PWM combination and the feedback level of the fault diagnosis circuit;

[0043] Figure 11 For any U-phase bridge arm open circuit, one of the truth table correspondences between the PWM combination and the feedback level of the fault diagnosis circuit;

[0044] Figure 12 For any U-phase bridge arm open circuit, the truth table correspondence between the PWM combination and the feedback level of the fault diagnosis circuit is shown in Part 2.

[0045] Figure label:

[0046] 1-Pre-charge circuit; 2-Three-phase full-bridge rectifier circuit; 3-Digital processing circuit; 4-PWM pre-drive circuit; 5-Analog load circuit; 6-Fault diagnosis circuit. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] In the description of this application: unless otherwise stated, "a plurality of" means two or more. The terms "first," "second," "third," etc., in this application are intended to distinguish the objects referred to and do not have any special meaning in terms of technical connotation (e.g., they should not be construed as an emphasis on importance or order). Expressions such as "including," "comprising," and "having" also mean "not limited to" (certain units, components, materials, steps, etc.).

[0049] In one embodiment, such as Figure 1As shown, a servo driver system is provided, the system including a pre-charging circuit 1, a three-phase full-bridge rectifier circuit 2, a digital processing circuit 3, a PWM pre-drive circuit 4, an analog load circuit 5, and a fault diagnosis circuit 6;

[0050] The pre-charging circuit 1 includes a DC bus and a pre-charging resistor connected in series on the DC bus, as well as a bypass relay connected in parallel on the pre-charging resistor.

[0051] The first terminal of the three-phase full-bridge rectifier circuit 2 is electrically connected to the output terminal of the pre-charging circuit 1, and the three-phase full-bridge rectifier circuit 2 includes multiple power switching transistors;

[0052] The output terminal of the digital processing circuit 3 is electrically connected to the input terminal of the PWM pre-drive circuit 4, and the output terminal of the PWM pre-drive circuit 4 is electrically connected to the second terminal of the three-phase full-bridge rectifier circuit 2. The PWM pre-drive circuit 4 is used to isolate, amplify and buffer the PWM signal output by the digital processing circuit 3 to obtain a drive signal, and input the drive signal to the three-phase full-bridge rectifier circuit 2.

[0053] The digital processing circuit 3 is used to drive the multiple power switching transistors through the PWM pre-drive circuit 4 according to a preset PWM test combination during the pre-charge stage when the bypass relay is disconnected and the DC bus is connected to the three-phase full-bridge rectifier circuit 2 via the pre-charge resistor.

[0054] The output terminal of the analog load circuit 5 is electrically connected to the third terminal of the three-phase full-bridge rectifier circuit 2. The analog load circuit 5 is used to provide a controlled equivalent load during the pre-charge phase.

[0055] The first input terminal of the fault diagnosis circuit 6 is electrically connected to the output terminal of the pre-charge circuit 1, the second input terminal of the fault diagnosis circuit 6 is electrically connected to the fourth terminal of the PWM pre-drive circuit 4, and the output terminal of the fault diagnosis circuit 6 is electrically connected to the input terminal of the digital processing circuit 3. The fault diagnosis circuit 6 is used to receive the bus voltage signal and the phase voltage signal generated by the PWM test combination during the pre-charge stage, compare the bus voltage signal and the phase voltage signal, and output a diagnostic signal to indicate the operating status of the power switch.

[0056] The servo driver system proposed in this application organically combines a pre-charge circuit 1, a three-phase full-bridge rectifier circuit 2, a digital processing circuit 3, a PWM pre-drive circuit 4, an analog load circuit 5, and a fault diagnosis circuit 6 to achieve status detection of the power switching transistors during the pre-charge phase of the driver. The pre-charge circuit 1 includes a DC bus, a pre-charge resistor, and a parallel bypass relay to ensure controlled current during initial power-on and prevent surge impact on the devices. The three-phase full-bridge rectifier circuit 2 provides the complete structural foundation for the power switching transistors. The digital processing circuit 3, in conjunction with the PWM pre-drive circuit 4, can sequentially drive multiple power switching transistors according to a preset test combination during the pre-charge phase, thereby applying controllable switching operations without closing the bypass relay. The analog load circuit 5 provides a controlled equivalent load environment during this phase, preventing the actual load on the motor from being excited and avoiding unnecessary movement. The fault diagnosis circuit 6 can simultaneously receive the bus voltage signal and the phase voltage signal, compare them, and output a diagnostic signal. This diagnostic signal is fed back to the digital processing circuit 3 to determine whether there is an abnormality in the power switching transistors. Therefore, it can be deduced that the system of this application can complete the fault detection of the power switching transistor during the pre-charge stage without driving the motor to generate a large current. This avoids catastrophic consequences caused by short circuits, open circuits, or impedance abnormalities in power devices, and also avoids the shortcomings of existing technologies that require voltage stabilization for diagnosis or have a large current flowing through the load during diagnosis. Thus, this system can effectively detect and locate power device faults in the initial power-on stage, ensuring the safety and reliability of the servo drive operation and fundamentally solving the technical problems of diagnostic lag, load malfunction, and device damage in the prior art.

[0057] In this embodiment, the fault diagnosis circuit 6 includes a first voltage divider network, a second voltage divider network, and a comparison unit;

[0058] The first voltage divider network is used to divide the bus voltage corresponding to the bus voltage signal to generate a first threshold voltage and a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

[0059] The second voltage divider network is used to divide the phase voltage corresponding to the phase voltage signal to generate a sampling voltage;

[0060] The comparison unit includes a first comparator and a second comparator. The first comparator is used to compare the first threshold voltage and the sampled voltage and output a first signal. The second comparator is used to compare the second threshold voltage and the sampled voltage and output a second signal. The first signal and the second signal are combined by logic circuitry to generate the diagnostic signal.

[0061] In this embodiment, the first voltage divider network divides the bus voltage signal to generate a first threshold voltage and a second threshold voltage. According to claim 2, the first threshold voltage is greater than the second threshold voltage, and these two form a voltage window for subsequent comparison.

[0062] like Figure 2 As shown, R3, R4, and R5 are the key resistors forming the first voltage divider network. These resistors divide the bus voltage (Vdc) to generate the first threshold voltage V(H_th) and the second threshold voltage V(L_th). Specifically:

[0063] R3 and R4 work together to divide the voltage and generate the first threshold voltage V(H_th);

[0064] R5 determines the second threshold voltage V(L_th).

[0065] Working principle: The bus voltage is divided by resistors R3, R4 and R5, and finally provides V(H_th) and V(L_th) to the comparison unit.

[0066] The function of the second voltage divider network is to divide the phase voltage signal (from each phase of the three-phase full bridge) to generate a sampled voltage, which is then compared with the threshold voltage.

[0067] like Figure 2 As shown, the second voltage divider network consists of resistors R6 and R10, which mainly divides the phase voltages (e.g., phases U, V, or W) to generate the sampling voltage. R6 and R10 divide the phase voltage signal (the voltage output from the three-phase full-bridge) to adapt it for subsequent comparison operations.

[0068] Working principle: By dividing the voltage through R6 and R10, the phase voltage signal is converted into a signal that can be compared with the threshold voltage generated by the first voltage divider network.

[0069] The function of the first comparator U1 is to compare the first threshold voltage (V(H_th)) with the sampled voltage. When the sampled voltage is greater than the first V(H_th), the first comparator outputs a specific signal.

[0070] Working principle: By comparison, the first comparator determines whether to trigger a signal indicating whether the sampled voltage is greater than the first threshold voltage V(H_th).

[0071] The second comparator compares the second threshold voltage (V(L_th)) with the sampled voltage. When the sampled voltage is less than V(L_th), the second comparator outputs another specific signal.

[0072] Working principle: By comparison, the second comparator determines whether to trigger another signal, indicating whether the sampled voltage is less than the lower threshold voltage V(L_th).

[0073] The function of the logic circuit is to receive the output signals of the first comparator and the second comparator and combine them into a diagnostic signal, which will be used for subsequent fault diagnosis.

[0074] The logic circuit may use basic digital logic elements such as AND gates, OR gates, and inverters, or more complex special-purpose logic circuits (such as CPLDs and FPGAs) to accomplish this task.

[0075] Working principle: The signals from the first comparator and the second comparator enter the logic circuit. Based on the result of the threshold comparison, the logic circuit outputs a single-level diagnostic signal for subsequent fault diagnosis or further judgment.

[0076] In this embodiment, the preset PWM test combination includes multiple preset PWM test items, which are: all bridge arms of the three-phase full-bridge rectifier circuit 2 are turned off, the lower bridge arm of phase U is turned on individually, the lower bridge arm of phase V is turned on individually, the lower bridge arm of phase W is turned on individually, the upper bridge arm of phase U is turned on individually, the upper bridge arm of phase V is turned on individually, and the upper bridge arm of phase W is turned on individually.

[0077] In this embodiment, the digital processing circuit 3 internally stores a truth table corresponding to the plurality of preset PWM test items, which is used to compare the diagnostic signal with the expected value of the truth table and determine the fault state of the corresponding power switch based on the comparison result.

[0078] In this embodiment, the simulated load circuit 5 includes a resistor network for forming a controlled equivalent load during the pre-charge phase, so as to diagnose the power switching transistor without driving an actual motor.

[0079] In one embodiment, a servo motor driver or servo amplifier is an electronic device used for precise control of a servo motor. It is the "brain" and "heart" of the servo system, receiving command signals from a host controller (such as a PLC or motion control card) and outputting the required power and precise current and voltage to control the torque, speed, and final position of the servo motor, thereby achieving high-precision motion control.

[0080] Power switching transistors: transistors, IGBTs, MOSFETs, SiC, GaN, and other devices used for power switching.

[0081] DC-link capacitor: The DC bus support capacitor on the power supply side of the three-phase full-bridge switch.

[0082] Pre-charge: Pre-charge, Precharging, Soft-start

[0083] DSP: Digital Processing Circuit 3 is a processor that receives control signals, feedback signals, and outputs power to control the movement of a servo motor.

[0084] Fault diagnosis: It can determine and output a switch quantity through hardware logic. This switch quantity is fed back to the DSP. The DSP, in combination with the control logic, determines whether there is a fault in the power switch.

[0085] Pre-charge resistor: The resistor before the high voltage enters the driver DC_link capacitor.

[0086] Bypass relay: A relay connected in parallel with the pre-charge resistor, used to bypass the pre-charge resistor after starting or enabling the driver.

[0087] No current flows through the load coil: A tiny current, caused by parasitic parameters between components or by the voltage divider sampling resistor, insufficient to drive a significant load movement. In this case, the current is approximately 500µA.

[0088] Traditional servo drives lack fault diagnosis for power devices during the high-voltage pre-charge phase, or there may be current flowing through the load during fault diagnosis, causing unexpected actions.

[0089] Using this embodiment, fault diagnosis of power devices can be completed during the pre-charge stage, and no current flows through the load coil during the diagnosis process, ensuring that the load does not move with large amplitude or high energy, thus ensuring the safety of personnel and the system.

[0090] Servo motor drivers are core components of modern industrial automation, widely used in precision manufacturing, motion control, and other applications. Their power stage typically consists of a three-phase inverter bridge, with each bridge arm composed of six power switching transistors. These power switching transistors operate under high voltage, high current, and high-frequency switching conditions, and are crucial components for the driver's external power output. They are prone to failure when abnormalities occur during installation, operation, load, or environmental conditions.

[0091] The main failures of power switching transistors manifest as short-circuit breakdown, open-circuit failure, and parameter drift (performance degradation) due to aging. If the driver is powered on and enabled without knowing the state of the power transistor, catastrophic consequences can easily occur.

[0092] Short circuit fault: If the power transistor is short-circuited, powering on will cause the DC bus to be directly short-circuited, generating a huge short-circuit current, instantly burning out the faulty transistor, driver chip, sampling resistor, and even causing board explosion, sparks, abnormal load operation, endangering equipment and personnel safety.

[0093] Open circuit fault: This will cause the motor to run with a single phase, resulting in torque pulsation and abnormal noise, causing the precision control to be completely inaccurate, the load to operate abnormally, and other components may be damaged due to the high voltage of back electromotive force generated.

[0094] Shoot-through: If the upper and lower pipes of the same bridge arm are simultaneously connected due to a drive failure, a partial short circuit will be formed, and the consequences are just as serious as a short circuit fault.

[0095] Therefore, it is crucial to perform non-invasive, comprehensive fault diagnosis of power switching transistors before the driver is started, especially in equipment that has been transported, stored, or has been reported to have faults.

[0096] Currently, common power-on startup and detection solutions in the industry typically focus on the pre-charge process of the DC-Link bus to prevent damage to capacitors and rectifier units from sudden power surges. When the DC-Link voltage reaches a certain percentage of the rated bus voltage within a certain time, the system is considered normal, and the relay is closed. This detection method can detect severe short-circuit faults such as bridge arm shoot-through and capacitor short circuits. However, existing technology lacks detection for other failure modes of power transistors, such as open-circuit switching transistors or short circuits in one phase. Therefore, this process cannot fully diagnose the state of the power switching transistors.

[0097] Existing technology 2: Operating the power switch during the pre-charging phase to achieve the purpose of power switch status diagnosis. However, during this process, the DC-Link capacitor has accumulated enough charge. Abnormal switching will cause a large current to flow through the load. The following two fault phenomena illustrate the potential problems.

[0098] Fault Phenomenon 1: If the power switch transistor of the upper bridge arm of phase U is short-circuited, then when the switch transistor of the lower bridge arm of phase U is closed, there will be a risk of direct connection between the upper and lower bridge arms. A considerable short-circuit current will flow through the U-phase bridge arm. If the overcurrent or short-circuit protection of the driver is inadequate, it will cause the power switch transistor to explode and generate sparks.

[0099] Fault Phenomenon 2: If the power switch of the upper arm of phase U is short-circuited, then when the switch of the lower arm of phase V is closed, a large current will flow through the load coil connected to phases UV, causing the load to change unexpectedly.

[0100] Fault Phenomenon 3: If the power switch of the upper arm of phase U is open-circuited, when the upper arm of phase U needs to output a high level after being enabled, phase U cannot output the correct current, which will cause an error in current vector synthesis and lead to an unexpected change in the load state.

[0101] Existing technology 3: Diagnosis can only be performed after the pre-charge has stabilized, and it cannot dynamically follow the fluctuations in the pre-charge voltage for diagnosis.

[0102] Therefore, the purpose of this embodiment is to solve the above problems. During the pre-charging process, before the relay is closed, under the premise that no current flows through the load, the fault diagnosis of the power switch tube is completed, such as abnormal conduction impedance caused by short circuit, open circuit, aging or fault.

[0103] This embodiment discloses a method in a servo driver system where, during the pre-charging phase of the driver, a fault diagnosis circuit 6 judges and outputs a level state, which is fed back to the DSP. The DSP, in conjunction with the control logic truth table, can determine whether the power switch is faulty. Regardless of whether the power switch is damaged, such as due to short circuit, open circuit, aging, or abnormal conduction impedance caused by a fault, no current flows through the load during the detection process, and there is no bridge arm short circuit current.

[0104] like Figure 9 The table shows the truth table correspondence between normal power switching transistors, PWM combinations, and feedback levels of the fault diagnosis circuit.

[0105] like Figure 10 As shown, the truth table correspondence between the PWM combination and the feedback level of the fault diagnosis circuit is shown when any one phase is short-circuited.

[0106] like Figure 11 and Figure 12 As shown, the truth table correspondence between the PWM combination and the feedback level of the fault diagnosis circuit is shown when any bridge arm of phase U is open-circuited. Phases V and W follow the same pattern.

[0107] Truth table contents:

[0108] Switch state: Possible combinations of states.

[0109] Closed bridge arm: DSP operation corresponds to the closing of the power switch tube. UH is the upper bridge arm of phase U, and UL is the lower bridge arm of phase U.

[0110] S_OUT: The high or low level output by the fault diagnosis circuit.

[0111] S_OUT diagnostic reference: The feedback level that should be obtained when the bridge arm is closed for a fault-free driver stored internally in the DSP.

[0112] Diagnostic results: The fault diagnosis results are obtained by comparing S_OUT and S_OUT diagnostic references.

[0113] like Figure 3 As shown, a method for diagnosing power switching transistor faults in a servo drive system is provided. The servo drive system is characterized in that the method includes:

[0114] During the pre-charge phase, the bypass relay is disconnected, and the DC bus is connected to the three-phase full-bridge rectifier circuit via the pre-charge resistor.

[0115] The digital processor sequentially drives multiple power switching transistors of the three-phase full-bridge rectifier circuit through a PWM pre-drive circuit according to a preset PWM test combination.

[0116] The fault diagnosis circuit receives the bus voltage signal output from the DC bus and the phase voltage signal output from the three-phase full-bridge rectifier circuit, compares the bus voltage signal and the phase voltage signal, and outputs a diagnostic signal; wherein, the diagnostic signal is used to indicate the operating status of the power switch transistor.

[0117] The digital processor compares the diagnostic signal with a pre-stored truth table and determines whether the power switch is faulty based on the comparison result.

[0118] In this embodiment, the digital processor sequentially drives multiple power switching transistors of the three-phase full-bridge rectifier circuit through a PWM pre-drive circuit according to a preset PWM test combination, including:

[0119] The digital processor drives all bridge arms of the three-phase full-bridge rectifier circuit to turn off through the PWM pre-drive circuit.

[0120] The digital processor sequentially drives the U-phase lower bridge arm, the V-phase lower bridge arm, and the W-phase lower bridge arm to conduct individually via the PWM pre-drive circuit.

[0121] The digital processor sequentially drives the U-phase upper bridge arm, the V-phase upper bridge arm, and the W-phase upper bridge arm to conduct individually via the PWM pre-drive circuit.

[0122] In this embodiment, the diagnostic signal output by the fault diagnosis circuit is a single-level signal, and the digital processor compares the diagnostic signal with the expected value in the truth table.

[0123] In this embodiment, firstly, the driver auxiliary power is turned on, and the DSP and fault diagnosis circuit can work normally, so the detection stage can be entered (before the bypass relay is closed).

[0124] Then, the actual phase line sampling voltage is compared with the preset theoretical upper and lower limits of the two phase line voltages by a comparator to see if it is still within the range, and outputs S_out.

[0125] Then, the DSP checks the feedback level S_out of the fault detection circuit. If it is low, it means that there is no short circuit in the power circuit.

[0126] Then, turn on the power switch of the lower bridge arm of phase U. The DSP checks the level comparison between S_out and S_OUT diagnostic reference. If they are the same, then according to Table 1, complete the PWM combination output in sequence and compare S_out and S_OUT diagnostic reference in sequence. If they are the same as the truth table, it means that there is no abnormality in the power switch.

[0127] Finally, if S_out and S_OUT diagnostic references are compared and are completely identical, the result is that the power switch is normal; if they are different, the result is that the power switch is abnormal, and the test program will exit immediately.

[0128] Simulation verification waveform illustration:

[0129] Waveform signal description:

[0130] V(G_M1,U),V(g_m2),V(G_M3,V),V(g_m4),V(G_M5,W),V(g_m6):

[0131] The control electrode levels of the six power switching transistors are respectively

[0132] V(vdc): The voltage level of the three-phase full-bridge circuit.

[0133] V(h_th), V(L_th): Reference threshold voltages of the fault diagnosis circuit.

[0134] V(vol_fb): Feedback voltage received by the fault diagnosis circuit

[0135] V(s_out): Output voltage of the fault diagnosis circuit

[0136] I(L1), I(L2), I(L3): Load terminal current

[0137] Calculation process:

[0138] V(H_th)=Vdc / (R3+R4+R5)*(R4+R5);

[0139] V(L_th)=Vdc / (R3+R4+R5)*R5;

[0140] V(vol_fb)=Vdc / (R1+R2+R19)*R2;

[0141] In one embodiment, such as Figure 2 and Figure 4 As shown, this is the fault diagnosis waveform after the simulated pre-charge voltage stabilizes, that is, after VDC becomes constant (power switch is normal).

[0142] Analysis and Summary: When the power switch is working normally, the output waveform of the fault diagnosis circuit corresponds to numbers 1-1 to 1-7 in Truth Table 1, indicating that the power switch is normal. No current flows through the load during the fault diagnosis process.

[0143] In one embodiment, such as Figure 2 and Figure 5 As shown, this is a fault diagnosis waveform during the simulated pre-charge voltage rise phase, which is the VDC change process (the power switch is normal).

[0144] Adjustment: R20 = 1Ω;

[0145] Analysis and Summary: During the voltage rise phase, when the power switch is operating normally, the output waveform of the fault diagnosis circuit corresponds to numbers 1-1 to 1-7 in Truth Table 1, indicating that the power switch is functioning normally. No current flows through the load during the fault diagnosis process.

[0146] In one embodiment, such as Figure 2 and Figure 6 As shown, the fault diagnosis waveform during the simulated pre-charge voltage rise stage, that is, the VDC change process, is an abnormal short circuit of power switch M6.

[0147] Analysis and Summary: In this type of fault condition, the fault diagnosis circuit outputs a fault level to the DSP according to the sequence number 2-1 in truth table 2, corresponding to the waveform from 1.0 to 1.2 ms in the waveform diagram below. The fault is diagnosed, the diagnostic program exits, and the diagnosis result is a power switch failure. No current flows through the load during the fault diagnosis process.

[0148] In one embodiment, such as Figure 2 and Figure 7 As shown, the fault diagnosis waveform during the simulated pre-charge voltage rise stage, that is, the VDC change process, is as follows (the impedance of the power switch M5 is too low when it is off, such as 10kΩ).

[0149] Analysis and Summary: In this type of fault condition, the fault diagnosis circuit outputs a fault level to the DSP according to the sequence number 2-1 in truth table 2, corresponding to the waveform from 1.0 to 1.2 ms in the waveform diagram below. The fault is diagnosed, the diagnostic program exits, and the diagnosis result is a power switch failure. No current flows through the load during the fault diagnosis process.

[0150] In one embodiment, such as Figure 2 and Figure 8 As shown, the fault diagnosis waveform during the simulated pre-charge voltage rise stage, that is, the VDC change process, is shown (the power switch M2 cannot be effectively closed, and a 1MΩ resistor is connected in series in the circuit to simulate this condition).

[0151] Analysis and Summary: In this type of fault condition, the fault diagnosis circuit outputs a fault level to the DSP according to the sequence number 3-2 in truth table 3, corresponding to the waveform from 1.0 to 1.2 ms in the waveform diagram below. The fault is diagnosed, the diagnostic program exits, and the diagnosis result is a power switch failure. No current flows through the load during the fault diagnosis process.

[0152] This embodiment describes a power switch fault detection method performed during the driver pre-charge phase. Regardless of whether power devices are damaged, such as due to short circuits, open circuits, aging, or abnormal conduction impedance caused by faults, no current flows through the load during the detection process, and the circuit can automatically adapt to the supply voltage. The detection threshold range can be flexibly adjusted based on parasitic parameters such as device and loop parameters.

[0153] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A servo drive system, characterized in that, The system includes a pre-charging circuit (1), a three-phase full-bridge rectifier circuit (2), a digital processing circuit (3), a PWM pre-drive circuit (4), an analog load circuit (5), and a fault diagnosis circuit (6). The pre-charging circuit (1) includes a DC bus and a pre-charging resistor connected in series on the DC bus, and a bypass relay connected in parallel on the pre-charging resistor; The first end of the three-phase full-bridge rectifier circuit (2) is electrically connected to the output end of the pre-charging circuit (1), and the three-phase full-bridge rectifier circuit (2) includes multiple power switching transistors; The output terminal of the digital processing circuit (3) is electrically connected to the input terminal of the PWM pre-drive circuit (4), and the output terminal of the PWM pre-drive circuit (4) is electrically connected to the second terminal of the three-phase full-bridge rectifier circuit (2). The PWM pre-drive circuit (4) is used to isolate, amplify and buffer the PWM signal output by the digital processing circuit (3) to obtain a drive signal, and input the drive signal to the three-phase full-bridge rectifier circuit (2). The digital processing circuit (3) is used to drive the multiple power switching transistors through the PWM pre-drive circuit (4) according to the preset PWM test combination during the pre-charge stage when the bypass relay is disconnected and the DC bus is connected to the three-phase full-bridge rectifier circuit (2) via the pre-charge resistor; The output terminal of the analog load circuit (5) is electrically connected to the third terminal of the three-phase full-bridge rectifier circuit (2), and the analog load circuit (5) is used to provide a controlled equivalent load during the pre-charge phase. The first input terminal of the fault diagnosis circuit (6) is electrically connected to the output terminal of the pre-charge circuit (1), the second input terminal of the fault diagnosis circuit (6) is electrically connected to the fourth terminal of the PWM pre-drive circuit (4), and the output terminal of the fault diagnosis circuit (6) is electrically connected to the input terminal of the digital processing circuit (3). The fault diagnosis circuit (6) is used to receive the bus voltage signal and the phase voltage signal generated by the PWM test combination during the pre-charge stage, compare the bus voltage signal and the phase voltage signal, and output a diagnostic signal to indicate the working state of the power switch.

2. The system according to claim 1, characterized in that, The fault diagnosis circuit (6) includes a first voltage divider network, a second voltage divider network, and a comparison unit; The first voltage divider network is used to divide the bus voltage corresponding to the bus voltage signal to generate a first threshold voltage and a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage. The second voltage divider network is used to divide the phase voltage corresponding to the phase voltage signal to generate a sampling voltage; The comparison unit includes a first comparator and a second comparator. The first comparator is used to compare the first threshold voltage and the sampled voltage and output a first signal. The second comparator is used to compare the second threshold voltage and the sampled voltage and output a second signal. The first signal and the second signal are combined by logic circuitry to generate the diagnostic signal.

3. The system according to claim 1, characterized in that, The preset PWM test combination includes multiple preset PWM test items, which are: all bridge arms of the three-phase full-bridge rectifier circuit (2) are turned off, the lower bridge arm of phase U is turned on alone, the lower bridge arm of phase V is turned on alone, the lower bridge arm of phase W is turned on alone, the upper bridge arm of phase U is turned on alone, the upper bridge arm of phase V is turned on alone, and the upper bridge arm of phase W is turned on alone.

4. The system according to claim 3, characterized in that, The digital processing circuit (3) internally stores a truth table corresponding to the plurality of preset PWM test items, which is used to compare the diagnostic signal with the expected value of the truth table and determine the fault state of the corresponding power switch based on the comparison result.

5. The system according to claim 1, characterized in that, The analog load circuit (5) includes a resistor network for forming a controlled equivalent load during the pre-charge phase to enable diagnosis of the power switch without driving the actual motor.

6. A method for diagnosing power switching transistor faults in a servo driver system, utilizing the servo driver system according to any one of claims 1-5, characterized in that, The method includes: During the pre-charge phase, the bypass relay is disconnected, and the DC bus is connected to the three-phase full-bridge rectifier circuit (2) via the pre-charge resistor; The digital processing circuit (3) drives multiple power switching transistors of the three-phase full-bridge rectifier circuit (2) in sequence through the PWM pre-drive circuit (4) according to the preset PWM test combination. The fault diagnosis circuit (6) receives the bus voltage signal output from the DC bus and the phase voltage signal output from the three-phase full-bridge rectifier circuit (2), compares the bus voltage signal and the phase voltage signal, and outputs a diagnostic signal; wherein, the diagnostic signal is used to indicate the working state of the power switch tube; The digital processing circuit (3) compares the diagnostic signal with the pre-stored truth table and determines whether the power switch tube is faulty based on the comparison result.

7. The method according to claim 6, characterized in that, The digital processing circuit (3) drives multiple power switching transistors of the three-phase full-bridge rectifier circuit (2) sequentially through the PWM pre-drive circuit (4) according to a preset PWM test combination, including: The digital processing circuit (3) drives all the bridge arms of the three-phase full-bridge rectifier circuit (2) to turn off through the PWM pre-drive circuit (4); The digital processing circuit (3) sequentially drives the U-phase lower bridge arm, the V-phase lower bridge arm, and the W-phase lower bridge arm to conduct individually through the PWM pre-drive circuit (4); The digital processing circuit (3) sequentially drives the U-phase upper bridge arm, the V-phase upper bridge arm, and the W-phase upper bridge arm to conduct individually through the PWM pre-drive circuit (4).

8. The method according to claim 6, characterized in that, The diagnostic signal output by the fault diagnosis circuit (6) is a single-level signal, and the digital processing circuit (3) compares the diagnostic signal with the expected value in the truth table.

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