Memory management method and storage device

Abstract

The present application provides a memory management method and a storage device. The method comprises: obtaining a write instruction from a host system; determining whether the host system is about to enter a sleep mode based on the write instruction; disabling a first write speed upper limit for a memory module in response to the host system being about to enter the sleep mode; and writing target data from the host system into the memory module while the first write speed upper limit is disabled. Thus, the operation efficiency and the operation stability of the storage device when switching the working mode can be improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] With technological advancements, some types of storage devices (such as flash memory) support multiple operating modes, including normal operation mode and hibernation mode. This allows for a balance between improving system performance and saving power through mode switching. Generally, before a storage device enters hibernation mode, data cached in the host's volatile memory (RAM) is migrated to the storage device's non-volatile memory (NDRAM). Upon returning from hibernation mode to normal operation mode, the previously migrated data is written back to the host's NDRAM to restore the host's operating state before entering hibernation mode.

[0003] However, a common problem in practice is that as the capacity of volatile memory (i.e., RAM) on the host side continues to increase, the amount of data that needs to be migrated before entering hibernation mode also increases. This causes both the host and storage devices to spend more time completing the preparation work before entering hibernation mode, severely impacting the user experience. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can improve the above-mentioned problems and thereby improve the operating efficiency and operational stability of the storage device when switching operating modes.

[0005] Embodiments of the present invention provide a memory management method for a storage device. The storage device includes a memory module. The memory management method includes: obtaining a write instruction from a host system; determining, based on the write instruction, whether the host system is about to enter a hibernation mode; disabling a first write speed limit for the memory module in response to the host system about to enter a hibernation mode; and writing target data from the host system to the memory module if the first write speed limit is disabled.

[0006] Embodiments of the present invention also provide a storage device including a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: obtain a write command from the host system; determine, based on the write command, whether the host system is about to enter a hibernation mode; in response to the host system about to enter a hibernation mode, disable a first write speed limit for the memory module; and, if the first write speed limit is disabled, write target data from the host system to the memory module.

[0007] Based on the above, after receiving a write command from the host system, it can be confirmed whether the host system is about to enter hibernation mode based on this write command. Subsequently, in response to the host system about to enter hibernation mode, the first write speed limit for the memory module can be disabled, and with the first write speed limit disabled, the target data from the host system is written to the memory module. This effectively improves the operating efficiency and stability of the storage device when switching between different operating modes. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating, according to an embodiment of the present invention, whether a host system is about to enter hibernation mode based on a write instruction;

[0012] Figure 5 This is a schematic diagram of the parsed frame information structure packet according to an embodiment of the present invention;

[0013] Figure 6 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0014] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0015] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0016] The host system 11 includes a processor 111 and a buffer memory 112. The processor 111 is responsible for the overall or partial operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0017] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include dynamic random access memory (DRAM) or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0018] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0019] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0020] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0021] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0022] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as bit flipping, low-density parity check code (LDPC code), BCH code, Reed-solomon code (RS code), and exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0026] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0027] In one embodiment, an entity unit may include an entity management unit. In another embodiment, the entity management unit is also referred to as a virtual unit. An entity management unit may include one or more entity erasure units. An entity erasure unit may include multiple entity programmatic units.

[0028] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto. In one embodiment, an entity programming unit is also referred to as an entity page.

[0029] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0030] In one embodiment, multiple programmed units within a single physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a single physical erase unit, an erase voltage can be applied to the multiple programmed units within that unit to change the threshold voltage of at least a portion of the memory cells in those units. By performing an erase operation on a single physical erase unit, the data stored in that unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0032] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0033] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0037] In one embodiment, the host system 11 (or processor 111) can operate in multiple operating modes. For example, the host system 11 (or processor 111) can switch between multiple operating modes to meet the operational needs at different times.

[0038] In one embodiment, the multiple operating modes include at least a normal operating mode and a hibernation mode. Compared to hibernation mode, the host system 11 (or processor 111) has higher performance (e.g., information processing performance) when operating in normal operating mode. However, compared to normal operating mode, the host system 11 (or processor 111) is more energy-efficient when operating in hibernation mode. For example, the clock frequency of the host system 11 (or processor 111) may be higher when operating in normal operating mode to achieve higher performance. Furthermore, compared to normal operating mode, the power consumption per unit time of the host system 11 (or processor 111) may be lower when operating in hibernation mode to achieve better energy savings.

[0039] In one embodiment, taking the Advanced Configuration and Power Interface (ACCI) standard as an example, the aforementioned normal operating mode may include states S0-S3 in the ACPI standard, while the sleep mode may include states S4-S5 in the ACPI standard. However, under different power standards, the states corresponding to the aforementioned normal operating mode and sleep mode may be different and can be adjusted according to practical needs.

[0040] In one embodiment, during normal operation of the host system 11, the memory control circuit 23 may obtain at least one write instruction from the host system 11. The write instruction may be used to instruct the storage device 12 to write (i.e., store) data from the host system 11. The total number of write instructions may be one or more.

[0041] In one embodiment, the write command may be actively retrieved from the buffer memory 112 of the host system 11 by the memory control circuit 23. In another embodiment, the write command may be passively received from the host system 11 by the memory control circuit 23.

[0042] In one embodiment, the memory control circuit 23 may determine whether the host system 11 is about to enter a hibernation mode based on a write instruction. For example, the memory control circuit 23 may determine whether the host system 11 is about to switch from a normal operating mode to a hibernation mode based on a write instruction.

[0043] In one embodiment, during the continuous receipt of write instructions from the host system 11, the memory control circuit 23 can determine whether the received write instruction has switched from one type of write instruction (also referred to as a first type of write instruction) to another type of write instruction (also referred to as a second type of write instruction). In response to the write instruction switching from the first type of write instruction to the second type of write instruction, the memory control circuit 23 can determine that the host system 11 is about to enter a sleep mode. However, if the write instruction has not switched from the first type of write instruction to the second type of write instruction, the memory control circuit 23 can determine that the host system 11 is not about to enter a sleep mode.

[0044] In one embodiment, the first type of write instruction includes Native Command Queuing (NCQ) write instructions, while the second type of write instruction includes Direct Memory Access (DMA) write instructions. However, the instruction types corresponding to the first and second types of write instructions can be adjusted according to practical needs.

[0045] Figure 4 This is a schematic diagram illustrating how a host system is about to enter hibernation mode based on a write command, according to an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, assuming that in the normal operating mode of the host system 11, starting from time point T(1), the memory control circuit 23 sequentially obtains write instructions 41(1)-41(D+1) from the host system 11. Among them, the write instructions 41(1)-41(D) belong to the first type of write instructions (e.g., NCQ write instructions), while the write instruction 41(D+1) belongs to the second type of write instructions (e.g., DMA write instructions).

[0046] Between time points T(1) and T(2), the memory control circuit 23 did not detect a switch from the first type of write instruction to the second type of write instruction. Therefore, between time points T(1) and T(2), the memory control circuit 23 can determine that the host system 11 is not about to enter hibernation mode.

[0047] However, between time points T(2) and T(3), the memory control circuit 23 detects that the acquired write instruction has switched from the first type of write instruction (i.e., write instruction 41(D)) to the second type of write instruction (i.e., write instruction 41(D+1)). In response to the switch of the acquired write instruction from the first type of write instruction to the second type of write instruction, the memory control circuit 23 can determine that the host system 11 is about to enter the hibernation mode.

[0048] In one embodiment, for any write instruction (also referred to as a first write instruction) obtained from the host system 11, the memory control circuit 23 can parse a package containing instruction information of this first write instruction to obtain a parsing result. For example, this package may be a Frame Information Structure (FIS) package or other types of packages. Then, the memory control circuit 23 can determine the type of the first write instruction based on this parsing result.

[0049] In one embodiment, if the parsing result is of a certain type (also referred to as a first type result), the memory control circuit 23 can determine that the first write instruction is a first type write instruction (e.g., an NCQ write instruction). However, if the parsing result is of another type (also referred to as a second type result), the memory control circuit 23 can determine that the first write instruction is a second type write instruction (e.g., a DMA write instruction). The first type result is different from the second type result.

[0050] Figure 5 This is a schematic diagram illustrating the parsing frame information structure packet according to an embodiment of the present invention. Please refer to... Figure 5 Assume that packet 51 is an FIS packet and that packet 51 carries instruction information for the first write instruction.

[0051] In one embodiment, the memory control circuit 23 can parse (e.g., filter or extract) the information content of the FIS type field 501 and the command register field 502 of the information packet 51. The information content of the FIS type field 501 reflects the type of the information packet 51. For example, if the FIS type field 501 records "0x27", it indicates that the type of the information packet 51 is a Register-Host to Device FIS structure. Then, the memory control circuit 23 can determine the type of the first write instruction based on whether the information content of the FIS type field 501 and the command register field 502 is specified.

[0052] In one embodiment, in response to the FIS type field 501 recording "0x27" (i.e., the type of information packet 51 is Register-Host to Device FIS), the memory control circuit 23 can further confirm the information content of the instruction register field 502. If the FIS type field 501 records "0x27" (i.e., the type of information packet 51 is Register-Host to Device FIS) and the instruction register field 502 records "0x65", then the memory control circuit 23 can determine that the first write instruction is a first type of write instruction (e.g., an NCQ write instruction).

[0053] In one embodiment, if the FIS type field 501 records "0x27" (i.e., the type of information packet 51 is Register-Host to Device FIS), but the instruction register field 502 records "0xCA", then the memory control circuit 23 can determine that the first write instruction is a second type of write instruction (e.g., a DMA write instruction).

[0054] In one embodiment, the memory control circuit 23 may further obtain the tag value of the queue to which the first write instruction belongs. For example, this tag value may be recorded in the "feature" field of the information packet 51. Then, the memory control circuit 23 may determine the type of the first write instruction (i.e., whether the first write instruction is a first type write instruction or a second type write instruction) based on this tag value (or the tag value and the analysis result described above). For example, if the "feature" field in the information packet 51 contains a tag value (and this tag value conforms to the specification), the memory control circuit 23 may determine that the first write instruction is a first type write instruction (e.g., an NCQ write instruction). However, if the "feature" field in the information packet 51 does not contain a tag value (or this tag value does not conform to the specification), the memory control circuit 23 may determine that the first write instruction is a second type write instruction (e.g., a DMA write instruction).

[0055] It should be noted that the information content of each of the above fields and the specified content used to identify the type of the first write instruction can also be adjusted according to practical needs, and this invention does not impose any restrictions.

[0056] In one embodiment, in response to the host system 11 about to enter a sleep mode, the memory control circuit 23 may disable the write speed limit (also referred to as the first write speed limit) for the memory module 122. For example, the first write speed limit is used to limit the maximum value of the data write speed for the memory module 122.

[0057] It should be noted that when the first write speed limit is not disabled (i.e., enabled), the data write speed to the memory module 122 will be limited to no higher than this first write speed limit. However, when the first write speed limit is disabled, the data write speed to the memory module 122 may be allowed to be higher than this first write speed limit (i.e., this first write speed limit is ignored).

[0058] In one embodiment, when the first write speed limit is disabled, the memory control circuit 23 can write data (also referred to as target data) from the host system 11 into the memory module 122. In particular, when the first write speed limit is disabled, the memory control circuit 23 can write the target data into the memory module 122 based on a data write speed higher than the aforementioned first write speed limit.

[0059] In one embodiment, the target data includes data that is migrated from the buffer memory 112 of the host system 11 to the memory module 122 for storage (e.g., backup) before the host system 11 enters hibernation mode (or during the preparation period for the host system 11 to enter hibernation mode).

[0060] In one embodiment, the target data may reflect the operating state of the host system 11 before entering hibernation mode. For example, this operating state may include the current state of all running programs (e.g., browsers, documents, editors, games, etc.), all open files and unsaved edits, CPU state, register state (e.g., program counter state), operating system kernel state, driver state (e.g., data structures and code currently being used by the operating system kernel, hardware driver status information), and system processes and services (e.g., background system services, security software, updaters), etc., before the host system 11 enters hibernation mode and then resumes normal operation. In one embodiment, the target data can be used to quickly restore the operating state of the host system 11 before entering hibernation mode after the host system 11 has entered hibernation mode and then resumed normal operation.

[0061] In one embodiment, after the host system 11 enters hibernation mode, the data cached in the buffer memory 112 (i.e., the aforementioned target data) may be cleared due to power failure. In another embodiment, by migrating the target data to the memory module 122 before the host system 11 enters hibernation mode, the target data can be quickly reloaded from the memory module 122 to the buffer memory 112 after the host system 11 resumes normal operation. Subsequently, based on the target data from the memory module 122, the host system 11 can quickly return to its operating state before entering hibernation mode.

[0062] In one embodiment, after disabling the first write speed limit, target data can be stored in memory module 122 at a data write speed higher than the first write speed limit before the host system 11 actually enters hibernation mode. This speeds up the storage of target data in memory module 122, thereby reducing the waiting time before the host system 11 enters hibernation mode.

[0063] In one embodiment, after initially determining that the host system 11 is about to enter a hibernation mode (e.g., the write command from the host system 11 switches from a first type of write command to a second type of write command) and disabling the first write speed limit, the memory control circuit 23 continuously monitors the amount of data written to the memory module 122 during the execution of the write command. The memory control circuit 23 can then compare this amount of data with a data amount (also referred to as a preset data amount) to obtain a comparison result.

[0064] In one embodiment, if the comparison result reflects that the amount of data written is greater than the preset data amount, the memory control circuit 23 can determine that the host system 11 is not about to enter a hibernation mode (i.e., the previously determined judgment that the host system 11 is about to enter a hibernation mode is a misjudgment). The reason is that in some cases, such as when the host system 11 is continuously storing the contents of a large file, the host system 11 may actively switch to using a second type of write instruction (e.g., a DMA write instruction) to store data in order to speed up data storage efficiency. In this case, even if the write instruction from the host system 11 includes a second type of write instruction, the host system 11 is not about to enter a hibernation mode. In other words, if the comparison result reflects that the amount of data written is greater than the preset data amount, it means that the host system 11 may simply be continuously storing the contents of a large file, and therefore the memory control circuit 23 can overturn the previously determined judgment that the host system 11 is about to enter a hibernation mode.

[0065] On the other hand, if the comparison result shows that the amount of data written is not greater than the preset data amount, the memory control circuit 23 can maintain the previously determined judgment that the host system 11 is about to enter the hibernation mode. That is, if the comparison result shows that the amount of data written is not greater than the preset data amount, it means that the previously determined judgment that the host system 11 is about to enter the hibernation mode should be correct (i.e., the previously determined judgment that the host system 11 is about to enter the hibernation mode is not a misjudgment), and the memory control circuit 23 can maintain the previously determined judgment that the host system 11 is about to enter the hibernation mode.

[0066] In one embodiment, the memory control circuit 23 can determine the preset data amount based on the capacity of the buffer memory 112 inside the host system 11. For example, assuming the capacity of the buffer memory 112 is "8G", the preset data amount can be determined to be "8G" (i.e., the preset data amount can be the same as the capacity of the buffer memory 112). Alternatively, in one embodiment, the preset data amount can also be fine-tuned to be slightly higher or slightly lower than the capacity of the buffer memory 112, depending on practical needs.

[0067] In one embodiment, if the comparison result shows that the amount of data written is greater than a preset data amount (indicating that the previously determined judgment that the host system 11 is about to enter hibernation mode is a misjudgment), the memory control circuit 23 can re-enable the first write speed limit. After re-enabling the first write speed limit, the data write speed for the memory module 122 can be limited again to no higher than this first write speed limit. However, if the comparison result shows that the amount of data written is not greater than a preset data amount (indicating that the previously determined judgment that the host system 11 is about to enter hibernation mode is correct), the memory control circuit 23 can maintain the first write speed limit disabled.

[0068] In one embodiment, the memory control circuitry 23 may determine a first write speed limit based on internal data migrations previously performed on the memory module 122. For example, this internal data migration may include garbage collection (GC) operations, wear leveling (WL) operations, or other types of data migration.

[0069] In one embodiment, the memory control circuit 23 can determine the first write speed limit by calculating the total amount of data migrated and the duration of the internal data migration during a past internal data migration performed on the memory module 122. For example, the memory control circuit 23 can determine the first write speed limit according to the following formula (1).

[0070] VS=WT / TGC (1)

[0071] In formula (1), WT represents the total amount of data migrated during a previous internal data migration, TGC represents the duration of this internal data migration, and VS represents the first write speed limit. It should be noted that formula (1) can also be adjusted according to practical needs.

[0072] In one embodiment, after disabling the first write speed limit, the memory control circuit 23 can enable another write speed limit (also referred to as a second write speed limit) for the memory module 122. The second write speed limit can be higher than the first write speed limit. This second write speed limit can be used to limit the data write speed of the target data to the memory module 122 when the first write speed limit is disabled. For example, when the first write speed limit is disabled and the second write speed limit is enabled, the memory control circuit 23 can limit the data write speed of the target data to the memory module 122 to no higher than this second write speed limit. This avoids excessive write errors caused by performing data writes to the memory module 122 at an unlimited speed.

[0073] In one embodiment, the aforementioned operation of enabling the second write speed limit is automatically executed in response to the first write speed limit being disabled. This achieves the technical effect of automatically replacing the first write speed limit with the second write speed limit, thereby improving the operational stability of the storage device 12.

[0074] In one embodiment, before determining that the host system 11 is about to enter hibernation mode, in the initialization or idle state of the storage device 12, the memory control circuit 23 can actively detect the upper limit of the continuous write speed for the memory module 122 (also known as the peak continuous write speed). For example, this upper limit of the continuous write speed can reflect the maximum write speed when performing continuous writes on the memory module 122 in the initialization or idle state of the storage device 12, combined with the current operating environment (e.g., the current temperature of the memory module 122). Then, the memory control circuit 23 can determine the aforementioned second upper limit of the write speed based on this upper limit of the continuous write speed. For example, the memory control circuit 23 can set the second upper limit of the write speed to be the same as (or close to but with an error) the upper limit of the continuous write speed. Thus, it can be ensured that the operational stability of the storage device 12 can still be maintained while maximizing the acceleration of storing the target data.

[0075] In one embodiment, the memory control circuit 23 can also determine in real time whether the available capacity of the memory module 122 is less than a preset capacity. In response to the available capacity of the memory module 122 being less than this preset capacity, the memory control circuit 23 can perform a specific operation (also called a capacity release operation) on the memory module 122. This capacity release operation is used to increase the available capacity of the memory module 122 to at least the preset capacity before starting the aforementioned migration of the target data (e.g., migrating the target data from the buffer memory 112 to the memory module 122). This avoids delays in the migration of the target data due to insufficient available capacity of the memory module 122 when the host system 11 is about to enter hibernation mode.

[0076] In one embodiment, the memory control circuit 23 can determine this preset capacity based on the capacity of the buffer memory 112 inside the host system 11. For example, assuming the capacity of the buffer memory 112 is "8G", the preset capacity can be determined to be "8G" (i.e., the preset capacity can be the same as the capacity of the buffer memory 112). Alternatively, in one embodiment, the preset capacity can also be fine-tuned to be slightly higher or slightly lower than the capacity of the buffer memory 112, depending on practical needs.

[0077] In one embodiment, the available capacity of the aforementioned memory module 122 refers to the total capacity of the idle physical units in the memory module 122. For example, the memory control circuit 23 can statistically determine this capacity. Figure 3The total number of physical units in the idle area 32 is used to obtain the available capacity of the current memory module 122.

[0078] In one embodiment, if the available capacity of the aforementioned memory module 122 refers to the total capacity of idle physical units in the memory module 122, the memory control circuit 23 can increase the available capacity of the memory module 122 to no less than a preset capacity by performing a unit reclamation operation (i.e., a capacity release operation). For example, this unit reclamation operation is used to reclamate some non-idle physical units in the memory module 122 in advance. Here, non-idle physical units can refer to... Figure 3 Any entity unit belonging to data area 31.

[0079] It should be noted that the early reclamation of some non-idle physical units in memory module 122 here refers to the pre-triggering of the reclamation of some non-idle physical units in memory module 122 before the regular garbage collection operation for memory module 122 is triggered, without waiting for the regular garbage collection operation to be triggered before new idle physical units can be released.

[0080] In one embodiment, during a cell reclamation operation, the memory control circuit 23 can centrally migrate valid data from a portion of the non-idle physical cells to selected idle physical cells and reassociate these non-idle physical cells with... Figure 3 The idle area 32. Therefore, by performing a cell reclamation operation, new idle physical cells can be released, thereby increasing the available capacity of the memory module 122.

[0081] In one embodiment, the available capacity of the aforementioned memory module 122 may also refer to the total capacity of the available physical units operating in cache mode within the memory module 122. For example, the memory control circuit 23 can determine this by statistical analysis. Figure 3 The available capacity of the current memory module 122 is obtained by determining the total number of physical units currently operating in cache mode in the idle area 32.

[0082] In one embodiment, if the available capacity of the aforementioned memory module 122 refers to the total capacity of the available physical units operating in cache mode in the memory module 122, then the memory control circuit 23 can increase the available capacity of the memory module 122 to no less than a preset capacity by performing a mode switching operation (i.e., a capacity release operation). For example, this mode switching operation includes switching some physical units in the memory module 122 that operate in non-cache mode to operate in cache mode.

[0083] In one embodiment, during the mode switching operation, the memory control circuit 23 can switch some of the physical units in the memory module 122 that were originally operating in non-cache mode to operate in cache mode. This increases the total number of available physical units operating in cache mode in the memory module 122, thereby increasing the available capacity of the memory module 122.

[0084] In one embodiment, the data write speed of a physical unit operating in cache mode is higher than that of a physical unit operating in non-cache mode. In another embodiment, each storage unit in a physical unit operating in cache mode can store N bits, and each storage unit in a physical unit operating in non-cache mode can store M bits, where N is less than M. For example, N can be 1, and M can be 2, 3, or 4. For example, cache mode may include SLC mode, while non-cache mode may include MLC, TLC, or QLC mode. However, the mode types of cache mode and non-cache mode can also be adjusted according to practical needs.

[0085] In one embodiment, the memory control circuit 23 can limit or manage the increased available capacity so that it can only be used to receive target data transmitted before the host system 11 enters sleep mode. This ensures that the storage of target data can be performed quickly and stably before the host system 11 enters sleep mode.

[0086] Figure 6 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 6 The memory management method includes steps S601 to S604.

[0087] In step S601, a write command is obtained from the host system.

[0088] In step S602, based on the write command, it is determined whether the host system is about to enter hibernation mode.

[0089] In step S603, in response to the host system about to enter hibernation mode (i.e., the judgment result of step S602 is yes), the first write speed limit for the memory module is disabled.

[0090] In step S604, with the first write speed limit disabled, the target data from the host system is written to the memory module.

[0091] Furthermore, if the judgment result of step S602 is negative, then we can return to step S601.

[0092] However, Figure 6 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 6Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 6 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0093] In summary, the memory management method and storage device proposed in this invention can detect whether the host system is about to enter hibernation mode through a specially designed mechanism. After determining that the host system is about to enter hibernation mode, the waiting time before the host system enters hibernation mode can be shortened by relaxing the write speed limit. Furthermore, the memory management method and storage device proposed in this invention also perform secondary verification and misjudgment recovery for possible false judgments about whether the host system is about to enter hibernation mode. Therefore, the operating efficiency and stability of the storage device when switching between different operating modes can be effectively improved.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For use in a storage device, wherein the storage device includes a memory module, and the memory management method includes: Obtain write instructions from the host system; Based on the write command, determine whether the host system is about to enter hibernation mode; In response to the host system about to enter the hibernation mode, the first write speed limit for the memory module is disabled; and With the first write speed limit disabled, target data from the host system is written to the memory module; The step of determining whether the host system is about to enter the hibernation mode based on the write command includes: Parse the frame information structure packet from the host system containing the write instruction, and determine whether the write instruction has been switched from a first type of write instruction to a second type of write instruction, wherein the first type of write instruction includes native instruction queue write instructions, and the second type of write instruction includes direct memory access write instructions; and In response to the switch of the write instruction from the first type of write instruction to the second type of write instruction, it is determined that the host system is about to enter the hibernation mode.

2. The memory management method according to claim 1, wherein the write instruction includes a first write instruction, and the step of determining whether the write instruction is switched from the first type of write instruction to the second type of write instruction includes: Based on the frame information structure packet of the first write instruction, the parsing result is obtained; If the parsing result is a first type of result, then the first write instruction is determined to be a first type of write instruction; as well as If the parsing result is of the second type, then the first write instruction is determined to be the second type of write instruction.

3. The memory management method according to claim 1, wherein the step of determining whether the host system is about to enter the hibernation mode based on the write instruction includes: During the execution of the write instruction, the amount of data written to the memory module is monitored; as well as If the amount of data written is greater than the preset amount of data, it is determined that the host system is not about to enter the hibernation mode.

4. The memory management method according to claim 3 further includes: The preset data volume is determined based on the capacity of the buffer memory inside the host system.

5. The memory management method according to claim 1, wherein the step of disabling the first write speed limit for the memory module includes: In response to the first write speed limit being disabled, a second write speed limit for the memory module is automatically enabled, wherein the second write speed limit is higher than the first write speed limit.

6. The memory management method according to claim 5, further comprising: In the initialization state or idle state of the storage device, the upper limit of the continuous write speed for the memory module is detected; as well as The second write speed limit is determined based on the continuous write speed limit.

7. The memory management method according to claim 1, further comprising: Determine whether the available capacity of the memory module is less than the preset capacity; as well as In response to the available capacity being less than the preset capacity, a capacity release operation is performed on the memory module to increase the available capacity to be no less than the preset capacity before the migration of the target data begins.

8. The memory management method according to claim 7, wherein the capacity release operation includes at least one of a cell reclamation operation and a mode switching operation. The unit reclamation operation includes the early reclamation of some non-idle physical units in the memory module, and The mode switching operation includes switching some entity units in the memory module that operate in non-cache mode to operate in cache mode.

9. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to: Obtain write instructions from the host system; Based on the write command, determine whether the host system is about to enter hibernation mode; In response to the host system about to enter the hibernation mode, the first write speed limit for the memory module is disabled; as well as With the first write speed limit disabled, target data from the host system is written to the memory module; The operation of determining whether the host system is about to enter the hibernation mode based on the write command includes: Parse the frame information structure packet from the host system containing the write instruction, and determine whether the write instruction has been switched from a first type of write instruction to a second type of write instruction, wherein the first type of write instruction includes native instruction queue write instructions, and the second type of write instruction includes direct memory access write instructions; and In response to the switch of the write instruction from the first type of write instruction to the second type of write instruction, it is determined that the host system is about to enter the hibernation mode.

10. The storage device of claim 9, wherein the write instruction includes a first write instruction, and the operation of determining whether the write instruction is switched from the first type of write instruction to the second type of write instruction includes: Based on the frame information structure packet of the first write instruction, the parsing result is obtained; If the parsing result is a first type of result, then the first write instruction is determined to be a first type of write instruction; as well as If the parsing result is of the second type, then the first write instruction is determined to be the second type of write instruction.

11. The storage device of claim 9, wherein determining whether the host system is about to enter the hibernation mode based on the write instruction includes: During the execution of the write instruction, the amount of data written to the memory module is monitored; as well as If the amount of data written is greater than the preset amount of data, it is determined that the host system is not about to enter the hibernation mode.

12. The storage device of claim 11, wherein the memory controller is further configured to: The preset data volume is determined based on the capacity of the buffer memory inside the host system.

13. The storage device of claim 9, wherein disabling the first write speed limit for the memory module comprises: In response to the first write speed limit being disabled, a second write speed limit for the memory module is automatically enabled, wherein the second write speed limit is higher than the first write speed limit.

14. The storage device of claim 13, wherein the memory controller is further configured to: In the initialization or idle state of the storage device, the upper limit of the continuous write speed for the memory module is detected; and The second write speed limit is determined based on the continuous write speed limit.

15. The storage device of claim 9, wherein the memory controller is further configured to: Determine whether the available capacity of the memory module is less than a preset capacity; and In response to the available capacity being less than the preset capacity, a capacity release operation is performed on the memory module to increase the available capacity to be no less than the preset capacity before the migration of the target data begins.

16. The storage device of claim 15, wherein the capacity release operation includes at least one of a cell reclamation operation and a mode switching operation. The unit reclamation operation includes the early reclamation of some non-idle physical units in the memory module, and The mode switching operation includes switching some entity units in the memory module that operate in non-cache mode to operate in cache mode.

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