Memory controller, memory management method and valid data positioning circuit unit

Abstract

The present disclosure provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises: determining a plurality of candidate virtual blocks according to the effective data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, and determining a plurality of target virtual blocks based on the mapping table bitmap and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical addresses in the sub-mapping tables and the physical addresses contained in the target virtual blocks. The present disclosure uses hardware acceleration to perform secondary screening on the candidate objects of garbage collection, determine the optimal target combination, integrate the mapping relationship, obtain the physical addresses of the corresponding effective data, and thus make the effective data table to improve the efficiency of garbage collection operation and reduce the reading burden of the storage device.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a memory management method, memory controller, and effective data location circuit unit for garbage collection (GC). Background Technology

[0002] With the development of semiconductor technology, non-volatile storage devices such as solid-state drives (SSDs) have been widely used. In SSD operation, due to the "erase-before-write" physical characteristic of NAND flash memory, data updates are not overwritten in place; instead, new data is written to a new free location, and old data is marked as invalid. This process generates a large amount of invalid data that does not occupy logical address space but occupies physical space—i.e., data fragments. To reclaim this occupied physical space, the storage controller needs to perform garbage collection (GC) mechanisms.

[0003] In some low-cost or low-power storage device designs (e.g., DRAM-less SSDs), due to the lack of large-capacity dynamic random access memory (DRAM) to cache the complete logical-to-physical (L2P) address mapping table, this mapping table is typically divided into multiple smaller sub-mapping tables and stored in flash memory. During garbage collection, the controller first needs to determine the physical units to be reclaimed (e.g., virtual blocks), and then read all the sub-mapping tables associated with these virtual blocks into the limited on-chip static random access memory (SRAM) to construct a list of physical addresses for valid data. However, different virtual blocks may be associated with the same sub-mapping tables, and traditional garbage collection methods often repeatedly read the same sub-mapping table. This not only consumes valuable flash memory read bandwidth but also increases the processing burden on the controller, creating a performance bottleneck in the garbage collection process and reducing the overall efficiency of the storage device. Summary of the Invention

[0004] In view of this, existing technologies suffer from performance degradation due to repeated readings of sub-mapping tables when handling garbage collection of DRAM-less memory devices. This disclosure provides a memory management method, a memory controller, and an effective data location circuit unit, which, through hardware acceleration, performs secondary screening of candidate virtual blocks to determine the optimal combination of target virtual blocks and integrates their mapping relationships to reduce the number of sub-mapping table reads, thereby improving garbage collection efficiency.

[0005] This disclosure provides one or more embodiments of a memory management method applied in a memory controller, the memory controller controlling a storage device configured with a memory module. The method includes: instructing a valid data location circuit unit of the memory controller, via a processor of the memory controller, to perform a valid data table generation operation, including: acquiring a plurality of candidate virtual blocks from a plurality of virtual blocks; determining a plurality of target virtual blocks from the plurality of candidate virtual blocks based on a plurality of mapping table bitmaps corresponding to the plurality of candidate virtual blocks, via the valid data location circuit unit, and generating an integrated mapping table bitmap corresponding to the plurality of target virtual blocks; acquiring one or more sub-mapping tables from the memory module according to the integrated mapping table bitmap; and generating a valid data table based on a plurality of first physical addresses in the one or more sub-mapping tables and a plurality of second physical addresses contained in each of the plurality of target virtual blocks, wherein the valid data table is used to indicate a plurality of third physical addresses of valid data of the plurality of target virtual blocks.

[0006] This disclosure provides a memory controller in one or more embodiments for controlling a storage device configured with a memory module. The memory controller includes: a memory interface control circuit configured to be electrically connected to the memory module; a processor electrically connected to the memory interface control circuit; and a valid data location circuit unit electrically connected to the processor. The processor is configured to instruct the valid data location circuit unit to perform a valid data table generation operation, wherein the valid data location circuit unit or the processor is configured to obtain a plurality of candidate virtual blocks from a plurality of virtual blocks; wherein the valid data location circuit unit is further configured to determine a plurality of target virtual blocks from the plurality of candidate virtual blocks based on a plurality of mapping table bitmaps corresponding to the plurality of candidate virtual blocks, and generate an integrated mapping table bitmap corresponding to the plurality of target virtual blocks; wherein the valid data location circuit unit or the processor is further configured to obtain one or more sub-mapping tables from the memory module according to the integrated mapping table bitmap; and wherein the valid data location circuit unit is further configured to generate a valid data table based on a plurality of first physical addresses in the one or more sub-mapping tables and a plurality of second physical addresses contained in each of the plurality of target virtual blocks, wherein the valid data table is used to indicate a plurality of third physical addresses of valid data of the plurality of target virtual blocks.

[0007] This disclosure provides one or more embodiments of an effective data location circuit unit for a storage device configured with a memory module. The effective data location circuit unit includes: an effective data count management circuit unit configured to acquire effective data count values ​​for each of a plurality of virtual blocks; a mapping table bitmap management unit configured to manage the mapping table bitmap; a parallel address comparison circuit unit configured to compare physical addresses; and a control unit electrically connected to the effective data count management circuit unit, the mapping table bitmap management unit, and the parallel address comparison circuit unit. The control unit is configured to control the operation flow of the effective data location circuit unit. The control unit is further configured to perform an effective data table generation operation. In the effective data table generation operation, the mapping table bitmap management unit is further configured to: determine a plurality of target virtual blocks among the plurality of candidate virtual blocks based on the mapping table bitmap of each candidate virtual block, and generate a corresponding integrated mapping table bitmap, wherein the integrated mapping table bitmap is used to indicate one or more sub-mapping tables. The parallel address comparison circuit unit is also configured to generate a valid data table based on multiple first physical addresses in one or more sub-mapping tables and multiple second physical addresses contained in each of the multiple target virtual blocks, wherein the valid data table is used to indicate multiple third physical addresses of multiple valid data of the multiple target virtual blocks.

[0008] Based on the above, the memory management method, memory controller, and effective data location circuit unit provided in this disclosure can achieve the following beneficial effects:

[0009] The memory controller disclosed herein integrates a valid data location circuit unit, which can determine multiple candidate virtual blocks based on the valid data count values ​​of each virtual block. Specifically, this step offloads the preliminary screening task, traditionally performed by the processor firmware, to dedicated hardware, freeing up the processor's computing resources so that it can focus on higher-level system management tasks, thereby improving the parallel processing capability of the memory controller.

[0010] By introducing a secondary screening mechanism based on the similarity of the mapping table bitmap, this disclosure can intelligently group the virtual blocks with the highest overlap of the required sub-mapping tables from the multiple candidate virtual blocks initially selected, and determine them as the final target virtual blocks. This secondary screening strategy ensures that the subsequently generated integrated mapping table bitmap is optimized, that is, it contains the fewest effective bits, thereby fundamentally reducing the total number of sub-mapping tables that need to be read from the memory module and reducing the read amplification effect during garbage collection.

[0011] Furthermore, the valid data location circuit unit of this disclosure can generate a valid data table at high speed based on the acquired sub-mapping table and the physical address contained in the target virtual block. In one embodiment, this generation process can be implemented through parallel address comparison. Compared with the traditional firmware's method of comparing addresses one by one, this hardware parallel processing method can shorten the identification time of valid data and further accelerate the preprocessing process of garbage collection.

[0012] In summary, this disclosure effectively solves the performance bottleneck problem caused by repeated reading of sub-mapping tables in the prior art by combining hardware acceleration, secondary screening strategies and parallel processing. Without increasing hardware costs too much, it improves the overall performance and reliability of the storage device when performing garbage collection. Attached Figure Description

[0013] Figure 1 This is a block diagram of a host system and storage device according to embodiments of the present disclosure;

[0014] Figure 2 This is a flowchart illustrating a memory management method according to embodiments of the present disclosure;

[0015] Figure 3 A block diagram of an effective data positioning circuit unit shown according to an embodiment of the present disclosure;

[0016] Figure 4 A detailed flowchart of the secondary screening method shown in the embodiments of this disclosure;

[0017] Figure 5 This is a schematic diagram illustrating the determination of candidate virtual blocks and reference virtual blocks according to embodiments of the present disclosure;

[0018] Figure 6 This is a schematic diagram illustrating the calculation of map bitmap similarity according to an embodiment of the present disclosure;

[0019] Figure 7 This is a schematic diagram illustrating the working principle of a parallel address comparison circuit unit according to an embodiment of the present disclosure. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0021] Reference Figure 1 In one embodiment, this disclosure provides a data storage system including a host system 10 and a storage device 20. The host system 10 may be, for example, a personal computer, a laptop computer, a server, or any other form of computing device.

[0022] The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120 (also referred to as host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0023] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230.

[0024] Storage device 20 is electrically connected to data transmission interface circuit 130 of host system 10 via its connection interface circuit 230 for data access operations. For example, host system 10 can store data to storage device 20 or read data from storage device 20 via data transmission interface circuit 130.

[0025] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0026] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with a high-speed communication standard, such as the Peripheral Component Interconnect Express (PCIe) standard. Furthermore, data transmission between them can be performed using a communication protocol (e.g., Non-Volatile Memory Express, NVMe). However, this disclosure is not limited to this; other interface standards (e.g., SATA, USB) and communication protocols may also be applied. In another embodiment, the connection interface circuit 230 may be packaged in a single chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0027] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0028] The storage device 20 includes a memory controller 210, a memory module 220, and a connection interface circuit 230. The memory controller 210 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs corresponding data writing, reading, and erasing operations in the memory module 220 according to instructions from the host system 10. The memory module 220 is electrically connected to the memory controller 210 and is used for long-term storage of user data. In this embodiment, the memory module 220 may include one or more non-volatile memory chips (e.g., NAND flash memory chips).

[0029] Specifically, the memory controller 210 includes a processor 211, a data management circuit 212, a memory interface control circuit 213, a buffer memory 214, a valid data locating circuit unit 215, and a DMA circuit unit 216. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0030] The memory controller 210 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs corresponding data writing, data reading, and data erasure operations in the memory module 220 according to the instructions of the host system 10. In particular, the memory controller 210 executes a memory management method provided in this disclosure to build an efficient data table for garbage collection through hardware acceleration, thereby improving the operating efficiency of the storage device.

[0031] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0032] In this embodiment, the processor 211 is hardware with computing capabilities, used to control the overall operation of the memory controller 210, such as executing firmware to implement various management functions of the Flash Translation Layer (FTL), including address mapping, garbage collection, wear averaging, etc. The processor 110 and processor 211 may be, for example, a Central Processing Unit (CPU), a microprocessor, or other programmable processing units (processors), Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar circuit components; this disclosure is not limited to these.

[0033] Data management circuit 212 is electrically connected to processor 211, connection interface circuit 230, and other circuit units within memory controller 210. Data management circuit 212 manages the data flow path between host system 10 and storage device 20 under the control of processor 211. Memory interface control circuit 213 is electrically connected to processor 211 and memory module 220, and receives instructions from processor 211 to generate control signals and timing required for physical operations (e.g., write, read, erase) on memory module 220.

[0034] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform physical operations such as writing (also known as programming), reading, or erasing on the memory module 220.

[0035] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0036] Furthermore, the memory controller 210 establishes a Logical to Physical address mapping table (L2P) and a Physical to Logical address mapping table (P2L) to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the L2P mapping table (also called the L2P mapping table) to find the physical unit mapped to a logical unit (e.g., finding the physical page mapped to a logical page; finding the physical address mapped to a logical address), and the memory controller 210 can use the P2L mapping table (also called the P2L mapping table) to find the logical unit mapped to a physical unit (e.g., finding the logical page mapped to a physical page; finding the logical address mapped to a physical address).

[0037] In some embodiments, particularly in designs where the capacity of buffer memory 214 is limited, the complete logic-to-physical address mapping table may be too large to be fully loaded. Therefore, memory controller 210 may divide the logic-to-physical address mapping table into multiple sub-mapping tables. These sub-mapping tables are typically stored in memory module 220 and loaded into buffer memory 214 by processor 211 for querying when needed.

[0038] The buffer memory 214 is electrically connected to other circuit units within the processor 211 and the memory controller 210, such as static random access memory (SRAM), to temporarily store data from the host system 10, data from the memory module 220, and various system information for managing the storage device 20 (e.g., sub-mapped tables, valid data counts, valid data tables, mapping table bitmaps, integrated mapping table bitmaps, etc.).

[0039] In a core feature of this disclosure, the memory controller 210 further includes an effective data location circuit unit 215 and a DMA circuit unit 216. The effective data location circuit unit 215 is a dedicated hardware acceleration circuit electrically connected to the processor 211, configured to execute a method for constructing an effective data table corresponding to multiple virtual blocks provided in this disclosure. The DMA circuit unit 216 (Direct Memory Access circuit unit) is a data transfer circuit electrically connected to multiple circuit units within the memory controller 210 (e.g., processor 211, effective data location circuit unit 215, buffer memory 214, memory interface control circuit 213, etc.), configured to transfer data between different components without occupying the computing resources of the processor 211.

[0040] Specifically, the application scenarios of DMA circuit unit 216 may include, but are not limited to: (1) Controlling DMA circuit unit 216 via valid data positioning circuit unit 215 to transfer data between buffer memory 214 and valid data positioning circuit unit 215, for example, transferring valid data count values ​​or mapping table bitmaps prepared in advance by processor 211 from buffer memory 214 to valid data positioning circuit unit 215. (2) Controlling DMA circuit unit 216 via valid data positioning circuit unit 215 to directly read data (e.g., mapping table bitmaps or sub-mapping tables) from memory module 220 to valid data positioning circuit unit 215 or buffer memory 214 to achieve a higher degree of automated operation.

[0041] During the operation of storage device 20, processor 211 executes a garbage collection mechanism to reclaim the physical space occupied by invalid data. Specifically, through the memory management method, memory controller, and valid data location circuit unit provided in this disclosure, processor 211 can offload computationally intensive tasks in the garbage collection process to valid data location circuit unit 215. Specifically, valid data location circuit unit 215 is configured to determine the optimal set of target virtual blocks based on the valid data count values ​​of multiple virtual blocks using a secondary filtering strategy, and generate an integrated mapping table bitmap for batch reading of sub-mapping tables, ultimately generating a valid data table for data migration. This hardware acceleration method improves the execution efficiency of garbage collection and frees up processor 211 resources to handle other tasks. Furthermore, a DMA mechanism can be used to directly acquire and compare the physical addresses of target virtual blocks to generate the corresponding valid data table.

[0042] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. Each physical page contains multiple memory cells, which can be single-level memory cells (SLC) or multi-level memory cells (MLC, TLC, QLC, etc.).

[0043] The following diagrams illustrate the specific details of the effective data positioning circuit unit 215.

[0044] For ease of management, the memory controller 210 can logically combine one or more physical blocks into a virtual block (VB). The virtual block is the basic unit of garbage collection operations. By managing data in units of virtual blocks, the memory controller 210 can organize data more flexibly and optimize the efficiency of background management operations such as garbage collection.

[0045] Figure 2 This is a flowchart illustrating a memory management method according to embodiments of the present disclosure.

[0046] Reference Figure 2 In one embodiment, this disclosure provides a memory management method, which can be implemented by... Figure 1 The memory controller 210 shown performs this function to efficiently build a valid data table prior to garbage collection operations.

[0047] First, in step S210, the processor 211 of the memory controller 210 instructs the valid data location circuit unit 215 of the memory controller 210 to perform a valid data table generation operation. Specifically, when it is necessary to determine the valid data of a specific virtual block, the processor 211 can activate its internal valid data location circuit unit 215 to perform a valid data table generation operation. In one embodiment, the triggering scenario for the valid data table generation operation may include: when the processor 211 detects that the amount of free physical space in the storage device 20 is lower than a preset garbage collection threshold; or when the system is idle, it is initiated actively by a background maintenance program; or in response to a specific system instruction.

[0048] The main steps of generating a valid data table are explained below:

[0049] In step S220, multiple candidate virtual blocks are obtained from multiple virtual blocks.

[0050] In one embodiment, multiple candidate virtual blocks can be determined by multiple valid data count values ​​corresponding to multiple virtual blocks. The valid data count values ​​are dynamically maintained by the firmware of the processor 211 during routine write and update operations of the storage device 20. Specifically, when new data is written or old data is updated (i.e., becomes invalid), the processor 211 increases or decreases the valid data count value of the virtual block containing that data accordingly. These count values ​​are recorded in real time in a management table, which can be stored in a specific system area of ​​the buffer memory 214 or the memory module 220.

[0051] In one embodiment, the valid data location circuit unit 215 controls the DMA circuit unit 216 to directly obtain the valid data count values ​​of each of the multiple virtual blocks from the memory module 220.

[0052] In another embodiment, processor 211 can ensure that the latest valid data count value has been loaded into buffer memory 214 for access by valid data location circuit unit 215. For example, processor 211 can be configured to read the valid data count values ​​of each of a plurality of virtual blocks from memory module 220 and transmit the read valid data count values ​​to valid data location circuit unit 215. It should be noted that the valid data count value only indicates the quantity / size of valid data in the corresponding virtual block and does not record the specific physical address of the valid data.

[0053] In one embodiment, the valid data counting management circuit unit 320 within the valid data positioning circuit unit 215 may be configured to sort the valid data count values ​​of each of the multiple virtual blocks (e.g., from low to high) and determine those virtual blocks whose valid data count values ​​are lower than a preset threshold as multiple candidate virtual blocks for further screening.

[0054] In another embodiment, at least one candidate virtual block may be selected from a sorted plurality of virtual blocks by a processor 211 based on a preset threshold or other mechanism.

[0055] Figure 5 This is a schematic diagram illustrating the determination of candidate virtual blocks and reference virtual blocks according to embodiments of the present disclosure.

[0056] Reference Figure 5 For example, suppose there are multiple virtual blocks VB1 to VB5 in storage device 20, and their corresponding valid data count values ​​are VC1 to VC5 respectively. As shown in Table T51, the size relationship of these count values ​​at a certain moment is VC5 < VC4 < VC1 < VC2 < VC3.

[0057] When the valid data table generation operation is initiated, the valid data count management circuit unit 320 acquires these count values ​​and performs a sorting operation. As shown in Table T52, the valid data count management circuit unit 320 can sort these virtual blocks in ascending order according to their valid data count values, as indicated by arrow A51. In this sorting result, the virtual block VB5 with the lowest valid data count value will be placed first.

[0058] Next, the valid data count management circuit unit 320 can determine multiple candidate virtual blocks based on a preset threshold. Specifically, the valid data count management circuit unit 320 can be configured to identify multiple virtual blocks whose valid data count values ​​are lower than the preset threshold as multiple candidate virtual blocks. For example, if the preset threshold is set to be greater than VC3, then in Figure 5 In the example shown by the dashed box in Table T52, virtual blocks VB5, VB4, VB1, VB2, and VB3 are all identified as multiple candidate virtual blocks. This ensures that a smaller number of candidate virtual blocks have a higher chance of being recorded in the valid data table, allowing storage space to be reclaimed through subsequent garbage collection.

[0059] In another embodiment, the mechanism for determining candidate virtual blocks can also be based on other rules. For example, the filtering rule can be configured to directly select a fixed number of the top N virtual blocks (e.g., the top five virtual blocks) from the sorting results as candidate virtual blocks without comparison with a threshold. This approach ensures that the number of candidate virtual blocks is fixed each time an operation is performed.

[0060] In another embodiment, the mechanism for determining candidate virtual blocks can also be based on specific commands from processor 211. For example, processor 211 can issue control commands to control valid data positioning circuit unit 215 to determine a specific number of target virtual blocks from a specified plurality of candidate virtual blocks to generate a corresponding valid data table. Processor 211 can specify the number of candidate virtual blocks or directly specify which specific candidate virtual blocks to perform the processing.

[0061] Furthermore, for subsequent secondary screening, the valid data count management circuit unit 320 can also determine the virtual block with the fewest valid data count values ​​from these candidate virtual blocks as the reference virtual block. In this example, since virtual block VB5 has the lowest valid data count value VC5, virtual block VB5 is determined as the reference virtual block.

[0062] In another embodiment, the valid data counting management circuit unit 320 may be internally composed of multiple cascaded basic comparison units. Each basic comparison unit may include a comparator and a multiplexer (MUX). The comparator compares the magnitudes of two input valid data count values, and the multiplexer, based on the comparison result, selects the set of data with the smaller value (the count value and its corresponding virtual block index) to pass to the next level. Through this cascaded structure, the unit can efficiently perform sorting of a large number of count values ​​or minimum value search.

[0063] Back Figure 2 Next, in step S230, based on multiple mapping table bitmaps corresponding to multiple candidate virtual blocks, multiple target virtual blocks among the multiple candidate virtual blocks are determined, and an integrated mapping table bitmap corresponding to the multiple target virtual blocks is generated.

[0064] In one embodiment, the effective data positioning circuit unit 215 acquires a mapping table bitmap corresponding to each candidate virtual block, and based on the mapping table bitmap, determines multiple target virtual blocks among the multiple candidate virtual blocks, and generates an integrated mapping table bitmap corresponding to the multiple target virtual blocks.

[0065] Specifically, the mapping table bitmap uses multiple bits to indicate one or more sub-mapping tables associated with the data of a corresponding virtual block. Each bit's position (e.g., index) corresponds to a unique number of a sub-mapping table. When a bit's value is "1", it indicates that some or all of the data stored in the virtual block is recorded in the sub-mapping table corresponding to that bit's index. Conversely, a value of "0" indicates that the virtual block is not associated with the corresponding sub-mapping table. For example, if an 8-bit mapping table bitmap is "00001011", it means that the data of its corresponding virtual block is associated with sub-mapping tables 0, 1, and 3. Through this data structure, the storage controller 210 can efficiently record and query the complex mapping relationships between each virtual block and all sub-mapping tables.

[0066] The generation and storage mechanism of the mapping table bitmap is further explained below. Specifically, during a regular write operation of storage device 20, when processor 211 needs to write new user data to a specific virtual block, processor 211 calculates the sequence number of the sub-mapping table corresponding to the logical address of the data. Subsequently, processor 211 updates the mapping table bitmap of that specific virtual block, setting the bit corresponding to the sub-mapping table sequence number to "1". This updated mapping table bitmap, as metadata, is written and stored along with the user data in a reserved physical area of ​​the specific virtual block within memory module 220 (e.g., the last physical page of the virtual block). In this way, each virtual block carries its own index information of data distribution, providing a data basis for subsequent secondary filtering.

[0067] To further optimize the reading efficiency of the sub-mapping table, this disclosure introduces a secondary filtering strategy. Specifically, in one embodiment, the mapping table bitmap management unit 330 within the effective data location circuit unit 215 can be configured to execute this strategy. First, a baseline virtual block (e.g., a candidate virtual block with the fewest effective data count values) is determined from a plurality of candidate virtual blocks. Then, based on the mapping table bitmap of the baseline virtual block, the similarity between the mapping table bitmaps of the other candidate virtual blocks and the baseline mapping table bitmap is calculated. Finally, based on the calculated similarity, a plurality of virtual blocks most similar to the baseline virtual block are determined from the candidate virtual blocks as the final plurality of target virtual blocks, and a bitwise OR operation is performed on the mapping table bitmaps of these target virtual blocks to generate an integrated mapping table bitmap.

[0068] In another embodiment, the secondary screening and generation of the integrated mapping table bitmap in step S230 can also be performed by the processor 211 through firmware execution. Specifically, after determining multiple candidate virtual blocks, the processor 211 can read the respective mapping table bitmaps of these candidate virtual blocks from the memory module 220 or the buffer memory 214. Subsequently, the processor 211 executes its internal screening algorithm, for example, determining a baseline virtual block and determining similarity by iteratively calculating Hamming distance, ultimately determining multiple target virtual blocks. Finally, the processor 211 performs a bitwise OR operation on the mapping table bitmaps of all target virtual blocks through its arithmetic logic unit (ALU) to generate the integrated mapping table bitmap. Although this software implementation may be less efficient than dedicated hardware, it provides greater algorithmic flexibility, allowing for the deployment of different or more complex screening strategies through firmware updates.

[0069] Figure 4 This is a detailed flowchart of the secondary screening method shown in the embodiments of this disclosure.

[0070] Reference Figure 4In step S410, the mapping table bitmap management unit 330 first determines multiple candidate virtual blocks and their respective multiple mapping table bitmaps.

[0071] Specifically, in one embodiment, the method of acquiring the mapping table bitmap may differ. In one embodiment (e.g., mode A), the mapping table bitmap may be pre-read from the memory module 220 and stored in the buffer memory 214 by the processor 211. Subsequently, the mapping table bitmap management unit 330 may control the DMA circuit unit 216 to acquire these mapping table bitmaps from the buffer memory 214. In another preferred embodiment (e.g., mode B), to improve automation, the mapping table bitmap management unit 330 may be configured to directly control the DMA circuit unit 216 to directly read the corresponding mapping table bitmap from a specific area in the memory module 220 that stores the metadata of each candidate virtual block.

[0072] Next, in step S420, a reference virtual block and its corresponding reference mapping table bitmap are determined from a plurality of candidate virtual blocks. As mentioned above, the reference virtual block may be a candidate virtual block with the fewest valid data count values.

[0073] Specifically, in one embodiment, the mapping table bitmap management unit 330 can access the sorting results provided by the valid data count management circuit unit 320 and directly select the candidate virtual block that ranks first and has the fewest valid data count values ​​as the reference virtual block. The mapping table bitmap corresponding to the reference virtual block will be regarded as the reference mapping table bitmap.

[0074] Subsequently, in step S430, the similarity between the reference mapping table bitmap and the mapping table bitmaps of other candidate virtual blocks is calculated.

[0075] Figure 6 This is a schematic diagram illustrating the calculation of bitmap similarity according to an embodiment of the present disclosure.

[0076] Reference Figure 6 Specifically, in one embodiment, the mapping table bitmap management unit 330 calculates the Hamming distance between corresponding pairs of mapping table bitmaps to determine similarity by operating its internal logic circuitry (e.g., XOR gate arrays and counters). For example, this process includes performing a bitwise XOR operation on the reference mapping table bitmap and the mapping table bitmap of each other candidate virtual block, and calculating the total number of bits with a value of "1" in the result to obtain a quantized similarity metric.

[0077] In a specific instance, the continuation Figure 5For example, the value of the mapping table bitmap BP5 of the baseline virtual block VB5 is "10010110". The mapping table bitmap management unit 330 will select a candidate virtual block, such as VB4, whose mapping table bitmap BP4 value is "10010111". As shown by arrow A61, the mapping table bitmap management unit 330 takes these two mapping table bitmaps BP5 and BP4 as input to obtain their similarity ST54.

[0078] More specifically, the mapping table bitmap management unit 330 first performs a bitwise XOR operation on BP5 and BP4:

[0079] "10010110" XOR "10010111" = "00000001"

[0080] The result of the operation, "00000001", precisely indicates the location where the two bitmaps differ. Next, the bitmap management unit 330 calculates the Hamming distance of the XOR operation result, which is the total number of bits with a value of "1" in the result. In this example, the result "00000001" contains only one "1", therefore the calculated Hamming distance is 1. This Hamming distance of 1 is used as a measure of the similarity between the baseline virtual block VB5 and the candidate virtual block VB4. The bitmap management unit 330 repeats this process for all other candidate virtual blocks to find the target virtual block most similar to the baseline virtual block VB5. These target virtual blocks most similar to the baseline virtual block VB5 effectively reduce the number of all loaded sub-maps.

[0081] In another embodiment, similarity can also be determined based on a direct calculation of the "overlap" in the mapping table bitmap. Specifically, the mapping table bitmap management unit 330 can be configured to perform a bitwise AND operation on the base mapping table bitmap and the mapping table bitmap of a candidate virtual block. The result of this operation will precisely indicate the sub-mapping tables commonly required by the two virtual blocks. Subsequently, an "overlap count value" can be obtained by calculating the Hamming distance of the bitwise AND operation result (i.e., the total number of bits with a value of "1" in the statistical result). In this embodiment, a higher overlap count value indicates that the two virtual blocks share more sub-mapping tables, i.e., a higher similarity.

[0082] In another embodiment, similarity can also be determined based on a direct assessment of the "total cost after integration." Specifically, the mapping table bitmap management unit 330 can be configured to perform a bitwise OR operation on the base mapping table bitmap and the mapping table bitmap of a candidate virtual block to pre-calculate the integrated mapping table bitmap after integrating the two virtual blocks. Subsequently, by calculating the Hamming distance of the integration result, a "total cost value" can be obtained, which represents the total number of sub-mapping tables required to process the two virtual blocks. In this embodiment, the lower the total cost value, the higher the efficiency of combining the candidate virtual block with the base virtual block, i.e., the higher the similarity.

[0083] Back Figure 4 After calculating all similarities, in step S440, multiple target virtual blocks are determined based on the multiple similarities. Specifically, the mapping table bitmap management unit 330 can select a predetermined number of candidate virtual blocks that have the highest similarity to the reference virtual block (e.g., the smallest Hamming distance) to form multiple target virtual blocks together with the reference virtual block.

[0084] Specifically, in one embodiment, the mapping table bitmap management unit 330 sorts all similarity metrics (e.g., Hamming distance) calculated in step S430. Then, based on a predetermined number (e.g., selecting N with the smallest Hamming distance), it determines a group of virtual blocks from the candidate virtual blocks that are most similar to the baseline virtual block, and determines them together with the baseline virtual block as the final multiple target virtual blocks.

[0085] However, in another, more optimized embodiment, in order to more directly address the physical constraint of limited buffer memory capacity, the strategy for determining the target virtual block can no longer be based solely on the pairwise similarity with the baseline virtual block, but rather on the "total cost after integration" of the target virtual block set as the selection criterion.

[0086] Specifically, in this embodiment, after determining the baseline virtual block, the mapping table bitmap management unit 330 uses an iterative selection method to determine other target virtual blocks. First, the baseline virtual block is used as the initial target virtual block group, and its mapping table bitmap is used as the initial integrated mapping table bitmap. Next, the mapping table bitmap management unit 330 traverses the remaining candidate virtual blocks and calculates a "marginal cost" for each candidate virtual block. This marginal cost quantifies the number of "new sub-mapping tables" that will be added to the integrated mapping table bitmap after adding the candidate virtual block to the current target virtual block group.

[0087] Subsequently, the mapping table bitmap management unit 330 selects the candidate virtual block with the lowest "marginal cost", adds it to the target virtual block group, and updates the integrated mapping table bitmap.

[0088] For example, if candidate virtual block A is selected as the new target virtual block, in addition to the multiple sub-mapping tables of the currently determined target virtual block, one new sub-mapping table needs to be added to match all the physical addresses of candidate virtual block A. In this case, the marginal cost of the corresponding sub-mapping table of candidate virtual block A is 1. As another example, if candidate virtual block B is selected as the new target virtual block, in addition to the multiple sub-mapping tables of the currently determined target virtual block, three new sub-mapping tables need to be added to match all the physical addresses of candidate virtual block B. In this case, the marginal cost of the corresponding sub-mapping table of candidate virtual block B is 3. In this scenario, the mapping table bitmap management unit 330 will use candidate virtual block A as the new target virtual block to update the current integrated mapping table bitmap based on its mapping table bitmap.

[0089] This iterative process continues until a preset termination condition is met. The termination condition may be, for example, that a predetermined number of target virtual blocks have been selected; or that the total number of sub-mapping tables indicated in the integrated mapping table bitmap has reached the upper limit threshold that the buffer memory 214 can accommodate.

[0090] This total cost optimization-based screening strategy ensures that, with limited buffer memory resources, the maximum number of target virtual blocks that can be efficiently processed at once from a number of known candidate virtual blocks are selected, thereby maximizing the benefits of garbage collection. It is especially suitable for application scenarios with strict limitations on buffer memory resources.

[0091] It is worth mentioning that, in other embodiments, the processor 211 may also participate in the decision-making of the target virtual block.

[0092] For example, in another embodiment, the effective data location circuit unit 215 of this disclosure also provides an "instruction mode" completely dominated by the processor 211. In this mode, the processor 211 can completely bypass the filtering logic within the effective data location circuit unit 215 and directly determine a set of target virtual blocks based on higher-level strategy considerations (e.g., combining wear averaging, data hot / cold analysis, or preventative error handling). Specifically, the processor 211 can issue an instruction containing a pre-determined list of target virtual blocks to the effective data location circuit unit 215 through the configuration register 360. Upon receiving this instruction, the effective data location circuit unit 215 will skip the steps of determining candidate virtual blocks and target virtual blocks (e.g., the flow of step S220) and directly perform subsequent operations such as generating an integrated mapping table bitmap, obtaining sub-mapping tables, and generating effective data tables based on the target virtual blocks specified in the instruction. This mode gives the processor 211 the highest control flexibility to cope with complex or urgent system management tasks.

[0093] In another embodiment, this disclosure also provides a "guided screening mode" in which the processor 211 and the effective data positioning circuit unit 215 work together. In this mode, the processor 211 first determines only one most critical virtual block as the "baseline virtual block" based on its global strategy, and transmits the specified baseline virtual block and a target number N to the effective data positioning circuit unit 215 through the configuration register 360. After receiving the instruction, the effective data positioning circuit unit 215 skips the step of autonomously determining the baseline virtual block and directly adopts the baseline virtual block specified by the processor 211. Subsequently, the effective data positioning circuit unit 215 leverages its high-speed computing capabilities to traverse all other candidate virtual blocks, calculate their similarity to the specified baseline, and find the N most similar virtual blocks. Finally, the "specified baseline virtual block" and the found "N most similar virtual blocks" together form multiple target virtual blocks for subsequent operations. This mode combines the processor's flexibility in strategic decision-making with the hardware's speed advantage in tactical computing. It should be noted that in other extended embodiments, the number of "reference virtual blocks" may be greater than one, so that the effective data positioning circuit unit 215 can find "N most similar virtual blocks" corresponding to multiple "specified reference virtual blocks" to obtain multiple target virtual blocks.

[0094] Finally, in step S450, an integrated mapping table bitmap is generated based on the multiple target mapping table bitmaps corresponding to the multiple target virtual blocks. In one embodiment, this step is accomplished by performing a bitwise OR operation on all target mapping table bitmaps. The generated integrated mapping table bitmap will be used in subsequent sub-mapping table acquisition steps.

[0095] Specifically, in one embodiment, the bitmap management unit 330 takes all determined target bitmaps as input and performs a bitwise OR operation on all corresponding bits of these bitmaps using its internal logic circuitry (e.g., multiple parallel bitwise OR gates). This internal logic circuitry can also be referred to as the first logic calculation unit. The final result of the operation is the integrated bitmap, which will be output to the control unit 310 or directly used to control the DMA circuit unit 216 for subsequent sub-map acquisition.

[0096] For example, in a specific instance, suppose that after two rounds of filtering, the final target virtual block group is {VB5, VB4, VB3}. Their mapping table diagrams are as follows:

[0097] Bitmap_VB5 = 10010110

[0098] Bitmap_VB4 = 10010111

[0099] Bitmap_VB3 = 10011110

[0100] The mapping table bitmap management unit 330 takes these three bitmaps as input and performs a bitwise OR operation on them:

[0101] “10010110” OR “10010111” OR “10011110” = “10011111”

[0102] The final result of the above calculation, "10011111", is the integrated mapping table bitmap. This result indicates that, in order to process all valid data in the three target virtual blocks VB5, VB4, and VB3, the storage controller 210 only needs to read six sub-mapping tables (numbers 0, 1, 2, 3, 4, and 7) from the memory module 220. In this way, repeated readings of sub-mapping tables (e.g., numbers 1, 4, and 7) commonly needed by these three virtual blocks are avoided.

[0103] Back Figure 2 The above steps S410 to S450 detail a specific implementation of step S230. After step S230 is completed and the integrated mapping table bitmap is generated, the method then executes step S240, in which one or more sub-mapping tables are obtained from memory module 220 according to the integrated mapping table bitmap. The integrated mapping table bitmap can be regarded as a mask that precisely indicates the set of all sub-mapping tables required to process the current set of target virtual blocks.

[0104] Specifically, in one embodiment, the effective data location circuit unit 215 can control the DMA circuit unit 216 to automatically read one or more required sub-mapping tables from the memory module 220 into the buffer memory 214 in batches according to the sub-mapping table sequence number indicated by the integrated mapping table bitmap.

[0105] In other embodiments, the valid data location circuit unit 215 sends an integrated mapping table bitmap to the processor 211, so that the processor 211 reads one or more sub-mapping tables from the memory module 220 according to the integrated mapping table bitmap, and transmits one or more sub-mapping tables to the valid data location circuit unit 215.

[0106] After step S240 is completed, i.e., the required one or more sub-mapping tables are obtained, step S250 is then executed. In step S250, a valid data table is generated based on the multiple first physical addresses in the one or more sub-mapping tables and the multiple second physical addresses contained in each of the multiple target virtual blocks.

[0107] In one embodiment, the valid data location circuit unit 215 selects one (selected first physical address) from a plurality of first physical addresses for comparison, and compares in parallel a plurality of second physical addresses of each of the plurality of target virtual blocks to locate a third physical address that matches the selected first physical address. The address among the plurality of second physical addresses that matches the selected first physical address is regarded as the third physical address and is recorded in the valid data table.

[0108] Specifically, the parallel address comparison circuit unit 340 within the valid data location circuit unit 215 can be configured to perform this step.

[0109] In one embodiment, the parallel address comparison circuit unit 340 includes multiple comparators, each corresponding to a different target virtual block. When a first physical address is selected from the sub-mapping table, the first physical address is simultaneously transmitted to all comparators.

[0110] In one embodiment, the data structure of the first physical address is specially designed to improve comparison efficiency. Specifically, the first physical address includes virtual block information and storage address information. The virtual block information (e.g., a bit field of a specific length) is used to uniquely identify the virtual block to which the first physical address belongs. The storage address information is used to indicate the specific physical location of the address in the memory module 220 (e.g., block, page, or a finer-grained address).

[0111] During the comparison, each comparator first extracts and compares only the virtual block information in the first physical address, matching it with the identifier of its corresponding pre-defined target virtual block. Only when the virtual block information matches successfully is the comparator activated to further compare the complete memory address information, thereby determining whether a completely matching third physical address exists. By utilizing this embedded virtual block information field for rapid preliminary filtering, unnecessary full address comparisons can be reduced, significantly lowering the power consumption and complexity of the comparison operation.

[0112] Each comparator performs this comparison process in parallel. When any comparator locates a matching third physical address, that third physical address is ultimately recorded to generate a valid data table, which indicates multiple third physical addresses of multiple valid data for multiple target virtual blocks. The following utilizes... Figure 7 Let me explain further.

[0113] Figure 7 This is a schematic diagram illustrating the working principle of a parallel address comparison circuit unit according to an embodiment of the present disclosure.

[0114] Reference Figure 7In a specific example, suppose the current target virtual block group includes target virtual block 1, target virtual block 2, target virtual block 3, and target virtual block 4. The parallel address comparison circuit unit 340 is therefore configured with four comparators 711, 712, 713, and 714, corresponding to these four target virtual blocks respectively. It should be noted that in other embodiments, the parallel address comparison circuit unit 340 can determine the total number of comparators activated based on the number of target virtual blocks.

[0115] In one embodiment, before the operation begins, each comparator (711-714) has preloaded multiple second physical addresses contained in its respective target virtual block (e.g., data streams A72, A73, A74, A75).

[0116] In another embodiment, the acquisition of multiple second physical addresses (A72-A75) loaded into each comparator (711-714) can be more efficient. Since the physical location of one or more physical blocks mapped to each target virtual block is known under the management of the memory controller 210, the range of physical addresses that the target virtual block can contain is also predetermined. Accordingly, the parallel address comparison circuit unit 340 can, before the start of operation, directly calculate the complete set of second physical addresses corresponding to each target virtual block through its internal address generation logic without actually reading the memory module 220, and load this set into the corresponding comparator. This method avoids additional data reading of the target virtual block before generating a valid data table, further improving operational efficiency.

[0117] When the valid data table generation operation is in progress, the control unit 310 selects a first physical address one by one from the multiple sub-mapping tables SMP that have been loaded into the buffer 350 (e.g., operation A71). The selected first physical address is simultaneously broadcast to all four comparators 711, 712, 713 and 714.

[0118] Each comparator performs comparison operations in parallel. For example, comparator 711 compares the received first physical address with multiple second physical addresses of the target virtual block 1; at the same time, comparator 712 compares the same first physical address with multiple second physical addresses of the target virtual block 2, and so on.

[0119] In this instance, suppose the selected first physical address exactly matches a second physical address contained in the target virtual block 2. This match means that the second physical address stores valid data recorded in the mapping table.

[0120] At this point, comparator 712 will output a match success signal containing a match flag and the first physical address that was matched. Result generator 720, coupled to the outputs of all comparators, captures and extracts the first physical address contained in the signal after detecting a valid match flag from comparator 712, and outputs this address as the third physical address (as shown in data stream A76). Result generator 720 can be implemented as a combinational logic circuit or a sequential logic circuit, coupled to the outputs of all comparators, and configured to latch and output the corresponding physical address information when a valid match flag is detected from any comparator output.

[0121] The matched third physical address (e.g., PCA1, PCA2, etc.) is then recorded in the valid data table T71. This process is repeated for all first physical addresses selected from the sub-mapping table SMP until all addresses have been matched, ultimately generating a complete valid data table T71, which contains the physical addresses of the valid data for all target virtual blocks.

[0122] Another beneficial effect of this disclosure is that it optimizes the efficiency of using the buffer memory 214 (SRAM). In situations where the buffer memory 214 has limited capacity, it is impossible to load all sub-mapping tables at once. Traditional methods may require repeatedly loading and releasing the same sub-mapping table when processing different virtual blocks, leading to inefficiency.

[0123] In the embodiments of this disclosure, since the effective data location circuit unit 215 has pre-generated an integrated mapping table bitmap, the processor 211 has already fully understood "which sub-mapping table" is associated with "which target virtual blocks" before it begins acquiring sub-mapping tables. Accordingly, the processor 211 can execute an intelligent processing sequence. For example, after the processor 211 loads the first required sub-mapping table from the memory module 220 into the buffer memory 214, it instructs the effective data location circuit unit 215 to use this table to complete the address comparison of all associated target virtual blocks at once. Only after all related processing is completed will the processor 211 release the space occupied by the sub-mapping table in the buffer memory 214 to load the next required sub-mapping table. Through this optimized processing flow, this disclosure avoids repeated loading of sub-mapping tables, further improving the overall performance of garbage collection.

[0124] In one embodiment, after generating the valid data table, the valid data location circuit unit 215 outputs the valid data table to the processor 211. After receiving the valid data table generated by the valid data location circuit unit 215, the processor 211 can perform subsequent valid data transfer operations according to the contents of the table to complete the entire garbage collection operation.

[0125] In one embodiment, the application of the valid data table can be more flexible. For example, after receiving the valid data table, the processor 211 may not immediately perform data movement, but instead temporarily store it in the system area of ​​the buffer memory 214 or the memory module 220. This approach is suitable for time-sharing garbage collection strategies, that is, the valid data table is pre-built when the system load is low, and the actual data movement is performed at a more suitable time (e.g., when the system is completely idle), thereby minimizing the impact of garbage collection on the user's foreground operations.

[0126] In another embodiment, the valid data table can also be used by the processor 211 for more advanced garbage collection decisions. For example, the processor 211 can generate valid data tables for multiple different target virtual block groups and perform a comprehensive evaluation based on the contents of these tables (e.g., the total size of valid data, the dispersion of data, etc.). By comparing the "recycling benefits" (freed space) and "recycling costs" (the amount of data to be moved) of different combinations, the processor 211 can make more refined garbage collection plans, such as prioritizing the virtual block group with the highest "benefit-cost ratio" to achieve smarter storage space management.

[0127] Specifically, the original valid data table indicates "which data is valid" and "how much valid data there is," while further analysis of its distribution pattern can reveal the deeper meaning of "how this valid data is stored." Based on this, this disclosure can also perform different optimization applications based on the valid data table.

[0128] [Optimize waste handling strategies]

[0129] In another embodiment, processor 211 may be configured to analyze the distribution of multiple third physical addresses contained in the valid data table T71 to optimize the cost of garbage collection and handling operations. Specifically, processor 211 may examine the physical contiguity of these third physical addresses in memory module 220.

[0130] If the processor 211 analyzes and determines that the multiple third physical addresses corresponding to the valid data of a target virtual block are physically highly contiguous (e.g., concentrated in a few adjacent physical pages), the processor 211 can mark this garbage collection operation as "low-cost". This is because reading this contiguously distributed data can be accomplished through one or more efficient sequential read commands, thereby shortening the time required for data migration. In this case, when the system has high performance requirements, the processor 211 can prioritize garbage collection of such "low-cost" target virtual blocks to release physical space in the shortest possible time while minimizing the performance impact on foreground user operations.

[0131] Conversely, if analysis reveals that the multiple third physical addresses corresponding to valid data are physically highly discrete (e.g., scattered across multiple non-adjacent physical pages), processor 211 can mark this garbage collection operation as "high-cost" because reading this data requires initiating multiple independent random read commands. In this case, processor 211 can choose to process such "high-cost" target virtual blocks when the system load is low or during a background maintenance window.

[0132] [Feedback to hot and cold data placement strategy]

[0133] In another embodiment, the distribution of physical addresses in the effective data table can also be used by the processor 211 as historical information to provide feedback and optimize its hot and cold data separation placement strategy. In one embodiment, the processor 211 may maintain a management table for tracking the "hotness" of virtual blocks.

[0134] After a garbage collection operation is completed, the processor 211 can analyze the physical address distribution of the reclaimed virtual blocks when generating their valid data tables. If the valid data of a virtual block exhibits a highly discrete distribution, it indicates that the data within the virtual block has undergone frequent updates (i.e., some data has been invalidated) since its initial write, which is a typical characteristic of "hot data." The processor 211 can then increase the "hotness value" of the virtual block or its region accordingly.

[0135] When a new host write command is subsequently received, the processor 211 can prioritize placing the new write data in areas identified as "hot" based on its maintained "hotness" management table. Through this adaptive learning mechanism based on garbage collection results, the storage controller 210 can continuously optimize the accuracy of its hot and cold data placement, thereby reducing the generation of invalid data and lowering the frequency of future garbage collection and write amplification.

[0136] [Performance Prediction and Quality of Service (QoS) Assurance]

[0137] In another embodiment of this disclosure, the valid data table can be used by processor 211 to accurately predict the execution time of garbage collection operations to ensure the system's Quality of Service (QoS). The total latency of a garbage collection operation depends primarily on the time required to read all valid data and the time required to rewrite that data.

[0138] Specifically, processor 211 can accurately calculate the total time required to rewrite data based on the total number of third physical addresses in the valid data table. Simultaneously, processor 211 can estimate the total time required to read this data based on the distribution pattern (continuous or discrete) of these addresses. By adding these two times, processor 211 can obtain a reliable prediction of the total latency of this garbage collection operation.

[0139] Upon receiving a garbage collection trigger signal, processor 211 can first generate a valid data table for multiple candidate target virtual block groups and perform latency prediction. If the predicted latency exceeds the upper limit allowed by the current quality of service policy, and the system is under high load, processor 211 can decide to postpone or cancel this garbage collection and instead perform other space management operations with lower overhead. Conversely, if the predicted latency is very short, processor 211 can perform garbage collection opportunistically without affecting the user experience.

[0140] [Auxiliary Data Refresh Strategy]

[0141] In another embodiment, the distribution pattern of physical addresses in the effective data table can also be used by the processor 211 as an auxiliary indicator to determine the "age" of data, thereby assisting in the execution of the data refresh strategy. Data in NAND flash memory is at risk of being damaged due to charge leakage and needs to be refreshed periodically.

[0142] In one embodiment, the processor 211 can track the write pattern of each virtual block. For virtual blocks that use a sequential write method, the memory cells with lower internal physical addresses typically correspond to data written earlier. When the processor 211 analyzes the valid data table of such a virtual block, if it finds that its valid data (i.e., the third physical address) is highly concentrated in the starting region of the physical address of the virtual block, and the virtual block has not been written to or reclaimed for a period of time, the processor 211 can infer that this part of the data is "stale" cold data that has not been accessed for a long time.

[0143] Based on this judgment, even if the valid data count of the virtual block is still high (not meeting the conditions for garbage collection), the processor 211 can add it to a "pending refresh" queue. When the system is idle, the processor 211 can proactively initiate data refresh operations (i.e., read and rewrite to a new physical location) for the virtual blocks in these queues, thereby improving the reliability of long-term stored data without affecting the normal garbage collection process.

[0144] [Active Data Migration Based on Temperature Recognition]

[0145] In another embodiment of this disclosure, the distribution pattern of physical addresses in the effective data table is not only used for historical information feedback, but can also be used by the processor 211 to perform active data migration based on data "temperature" (i.e. hot and cold attributes) in the current garbage collection operation to match the storage characteristics of different physical areas in the memory module 220.

[0146] In one embodiment, the memory module 220 may include different types of storage regions. For example, a portion of the physical blocks may be configured as SLC (Single-Level Cell), which has a higher erase / write lifetime and a faster write speed, making it suitable for storing frequently updated "hot data"; while another portion of the physical blocks may be configured as TLC / QLC (Triple / Quad-Level Cell), which has a higher storage density but a shorter lifetime, making it suitable for storing long-term unchanging "cold data".

[0147] When the processor 211 analyzes the physical address distribution of the effective data table of a target virtual block and determines that the effective data inside it exhibits highly discrete characteristics, the processor 211 can classify this batch of effective data as "hot data".

[0148] When performing subsequent data migration operations, the processor 211 no longer randomly writes this data to arbitrary free blocks. Instead, it strategically queries and selects a currently available physical block configured in SLC mode as the target unit. Subsequently, the processor 211 actively and centrally migrates this valid data, which is identified as "hot data," to this SLC mode block, which is more suitable for frequent erasure and rewriting.

[0149] By employing this proactive data migration strategy based on data temperature recognition, this disclosure enables the simultaneous achievement of space reclamation and data layout optimization within a single garbage collection operation. This not only improves the write performance and durability of hot data but also physically isolates cold data areas from hot data areas. Consequently, in future garbage collections, updates to a small amount of hot data can prevent the entire cold data block from being affected, significantly reducing write amplification and extending the overall lifespan of the storage device.

[0150] The following uses Figure 3 This section details the relevant aspects of the effective data positioning circuit unit.

[0151] Figure 3 This is a block diagram of an effective data positioning circuit unit shown according to an embodiment of the present disclosure.

[0152] Reference Figure 3In one embodiment, the valid data location circuit unit 215 includes a control unit 310, a valid data counting management circuit unit 320, a mapping table bitmap management unit 330, a parallel address comparison circuit unit 340, a buffer 350, a configuration register 360, a result register 370, and a status register 380.

[0153] The control unit 310 is the core coordination module of the effective data positioning circuit unit 215, and it is electrically connected to all other internal functional units. The control unit 310 is configured to parse instructions from the processor 211 and, according to the instruction content and a preset logical timing sequence, precisely control the start-up, stop-up, and data flow between each functional unit.

[0154] In terms of specific hardware implementation, the control unit 310 can be implemented using a variety of different technical paths according to design requirements.

[0155] For example, in one embodiment, the control unit 310 can be implemented as a finite state machine (FSM). This FSM includes multiple preset states (e.g., "idle state," "waiting for count value state," "performing secondary filtering state," "waiting for sub-mapping table state," "performing parallel comparison state," "complete state," etc.). When the control unit 310 receives a trigger instruction from the processor 211 from the configuration register 360, the FSM starts from the "idle state" and, based on an internal counter, completion signals from other functional units, and feedback from the status register 380, transitions between these states sequentially according to a predetermined logical order. In each state, the FSM outputs a specific set of control signals to precisely enable or disable the corresponding functional unit (e.g., the valid data count management circuit unit 320), or control the flow of data in the buffer 350. This FSM-based implementation is simple in structure, has a fast response speed, and is suitable for efficient control of fixed processes.

[0156] For example, in another embodiment, to provide greater flexibility, the control unit 310 can be implemented as a micro-coded controller. In this architecture, the complex operation of the effective data positioning circuit unit 215 is pre-programmed into a series of micro-instructions and stored in an internal read-only memory (ROM) or programmable memory. The control unit 310 internally includes a micro-sequencer, which is responsible for retrieving the corresponding micro-instruction sequence from memory and executing it one by one according to external instructions from the configuration register 360. Each micro-instruction defines the control signals for all other functional units within one clock cycle. By updating the microcode in memory, the operation of the effective data positioning circuit unit 215 can be easily modified or upgraded, and even new functions (e.g., the "P2L parsing mode" discussed later) can be added without modifying the hardware circuitry itself. This implementation provides this disclosure with high configurability and future scalability.

[0157] Configuration register 360, result register 370 and status register 380 constitute the main communication interface between valid data positioning circuit unit 215 and processor 211.

[0158] Specifically, in one embodiment, configuration register 360 is configured to receive trigger instructions and operation data from processor 211. The trigger instructions are used to initiate valid data positioning circuit unit 215 to perform a specific operation (e.g., to start a valid data table generation operation).

[0159] In one embodiment, to provide design flexibility, the operational data may include the data itself or storage address information indicating the location of the data in external memory (e.g., buffer memory 214 or memory module 220). For example, operational data that processor 211 can write to configuration register 360 may include one or more of the following: multiple valid data count values ​​themselves, or storage address information of a list recording these count values; multiple mapping table bitmaps themselves, or storage address information of these bitmaps; or multiple sub-mapping tables themselves, or storage address information of these sub-mapping tables.

[0160] In one embodiment, status register 380 is configured to report the processing status of the current operation to processor 211. For example, status register 380 may include specific status bits to record and indicate whether the valid data location circuit unit 215 is currently in a state such as "idle," "busy," "operation completed successfully," or "operation error." In some embodiments, status register 380 may also be used to report processing results, such as the total number of valid physical addresses contained in the final generated valid data table.

[0161] In other implementation examples, the status register 380 can also use a specific algorithm to determine further information such as the effective data ratio and the degree of effective data dispersion for the corresponding multiple target virtual blocks.

[0162] For example, in another embodiment, the status register 380 may also be configured to report statistics related to the processing results, such as the valid data ratio.

[0163] Specifically, during the process of generating the valid data table by the parallel address comparison circuit unit 340, the control unit 310 can not only count the total number of valid physical addresses (i.e., the number of processing results), but also obtain the total size (e.g., the total number of pages) of the multiple target virtual blocks for this operation from the processor 211 or the configuration register 360. After the operation is completed, the control unit 310 can perform a division operation to calculate the ratio between the "total number of valid physical addresses" and the "total size of the target virtual blocks", which is the valid data ratio.

[0164] The effective data percentage is then written to a specific field in the status register 380. When reading the status, the processor 211 not only knows whether the operation is complete, but also directly obtains the "space reclamation efficiency" of this garbage collection. For example, a lower effective data percentage (such as 10%) means that this GC operation can free up a large amount of physical space, making it a highly efficient reclamation. The processor 211 can use this information to evaluate the effectiveness of its GC strategy and make dynamic adjustments.

[0165] For example, in yet another embodiment, the status register 380 may also be configured to report the degree of dispersion of valid data.

[0166] Specifically, when the parallel address comparison circuit unit 340 locates a matching third physical address, its internal logic circuitry can perform a preliminary analysis of the physical continuity of these addresses. For example, the control unit 310 can maintain a counter to count whether the valid data hit when reading consecutive sub-mapping table entries is also located on consecutive physical pages. If there are consecutive hits, the counter is not incremented; if an address jump occurs, the counter is incremented. The final count value is a "fragmentation index" that quantifies the degree of dispersion of valid data.

[0167] The fragmentation index is written to status register 380 after the operation is completed. By reading this index, processor 211 can quickly understand the physical layout of the valid data in the target virtual block. A high fragmentation index means that the data is highly discrete, and reading this data requires high cost (as described in the previous embodiments). Processor 211 can use this information to trigger more advanced management operations, such as marking the virtual block as a "hot data" area, or defragmenting it when the system is idle.

[0168] In one embodiment, the result register 370 is configured to store information related to the final output of the operation. In one embodiment, after the valid data location circuit unit 215 generates a valid data table, the table is temporarily stored in its internal buffer 350. At this time, the result register 370 can be configured to store the address information of the valid data table in the buffer 350. After the processor 211 learns from the status register 380 that the operation is complete, it can read the result register 370 to obtain the address information and arrange for the DMA circuit unit 216 to retrieve the final result from the buffer 350 accordingly.

[0169] In one embodiment, buffer 350 is a high-speed data buffer within valid data positioning circuit unit 215, electrically connected to control unit 310, various data processing units, and external DMA circuit unit 216. Buffer 350 is configured to temporarily store data transferred between valid data positioning circuit unit 215 and external memory (e.g., buffer memory 214) via DMA circuit unit 216.

[0170] The valid data counting management circuit unit 320, the mapping table bitmap management unit 330, and the parallel address comparison circuit unit 340 are functional modules that perform core data processing tasks.

[0171] In one embodiment, when a valid data table generation operation is initiated, the control unit 310 first activates the valid data count management circuit unit 320. The valid data count management circuit unit 320 obtains the valid data count values ​​of multiple virtual blocks from the buffer 350 and sorts them to determine multiple candidate virtual blocks.

[0172] Next, in one embodiment, the control unit 310 activates the mapping table bitmap management unit 330. The mapping table bitmap management unit 330 retrieves multiple mapping table bitmaps corresponding to candidate virtual blocks from the buffer 350 and performs a secondary filtering operation. This operation includes determining a baseline virtual block, calculating similarity, determining the final multiple target virtual blocks, and generating an integrated mapping table bitmap. The generated integrated mapping table bitmap can be written back to the buffer 350 for use by the control unit 310 or processor 211 for subsequent sub-mapping table retrieval.

[0173] In one embodiment, after one or more required sub-mapping tables are acquired and loaded into buffer 350, control unit 310 finally activates parallel address comparison circuit unit 340. Parallel address comparison circuit unit 340 reads the first physical address and the second physical address of the target virtual block from the sub-mapping table in buffer 350 and performs parallel comparison operations to generate the final valid data table. The generated valid data table is temporarily stored in buffer 350, and after the operation is completed, control unit 310 updates status register 380 and result register 370 to notify processor 211 that the task has been completed and the result can be read.

[0174] In the embodiments of this disclosure, the effective data positioning circuit unit 215 is a dedicated hardware acceleration module, which can be physically integrated into the chip of the storage controller 210 in various ways.

[0175] In one embodiment, the valid data location circuit unit 215 can be implemented as an application-specific integrated circuit (ASIC) module. Specifically, all its internal functional units, including the control unit 310, the valid data count management circuit unit 320, the mapping table bitmap management unit 330, the parallel address comparison circuit unit 340, and related registers and buffers, can be designed using a hardware description language (HDL, such as Verilog or VHDL). Subsequently, through standard semiconductor design flows (e.g., logic synthesis, place and route), this design is transformed into a specific physical circuit layout composed of standard logic gates, flip-flops, and memory units. Ultimately, this circuit layout will be fabricated on the same silicon wafer as part of the memory controller 210 chip design, along with other modules (such as the processor 211, DMA circuit unit 216, etc.).

[0176] In another embodiment, for rapid prototyping in the early stages of product development, or for applications requiring field-programmable capabilities, the functionality of the effective data location circuitry unit 215 can be implemented on a programmable logic device (PLD). For example, the hardware description language code describing the functionality of the effective data location circuitry unit 215 can be synthesized and downloaded into a field-programmable gate array (FPGA) chip. This FPGA chip can be integrated on the same circuit board as a general-purpose processor core to simulate the full functionality of the memory controller 210.

[0177] It should be noted that those skilled in the art will understand that other architectural implementations can be derived based on the core idea of ​​accelerating garbage collection by optimizing mapping relationships disclosed in this disclosure. For example, in another embodiment, instead of using a globally shared sub-mapping table architecture, a dedicated, local mapping table can be configured for each virtual block (or a small group of virtual blocks), and this local mapping table is stored together with its corresponding virtual block. Under this architecture, when performing garbage collection, there is no need for complex secondary filtering and bitmap integration; it is only necessary to directly read the local mapping table that comes with the target virtual block. Although this architecture may require the introduction of additional high-level indexes to handle regular read and write operations, it provides another feasible technical path to solve the garbage collection efficiency problem.

[0178] In one embodiment, this technical approach can be embodied as an improved effective data table construction method, which includes: after determining one or more target virtual blocks based on the effective data count value, for each target virtual block, obtaining the P2L sub-mapping table corresponding to the target virtual block from the memory module 220; parsing multiple entries in the P2L sub-mapping table to identify all effective entries mapped to effective logical addresses; and extracting the physical addresses of each of the effective entries to generate an effective data table. Specifically, in one embodiment, the global P2L mapping table can be divided according to multiple virtual blocks to form multiple P2L sub-mapping tables by means of a Physical-to-Logical (P2L) address mapping mechanism. Each P2L sub-mapping table records only the mapping information from all physical addresses within a corresponding virtual block to its mapped logical addresses, and is stored together with the virtual block. In a normal write operation, the processor 211 updates the global L2P mapping table and simultaneously updates the P2L sub-mapping table related to the write operation.

[0179] After performing garbage collection and identifying the target virtual block, the processor 211 can issue a special instruction to the valid data location circuit unit 215 to switch to a P2L-based fast location mode. In this mode, the control unit 310 directly controls the DMA circuit unit 216 to read the P2L sub-mapping table specific to the target virtual block from the memory module 220 into the buffer 350.

[0180] Subsequently, the control unit 310 activates the parallel address comparison circuit unit 340. In this P2L mode, the function of the parallel address comparison circuit unit 340 is reconfigured. It no longer performs a "comparison" operation between the two address lists, but instead performs a "validity resolution" operation. Specifically, the parallel address comparison circuit unit 340 traverses each entry in the P2L sub-mapping table. According to the definition of the P2L mapping table, as long as a physical address entry maps to a valid logical address (e.g., an invalid flag that is not all F), it indicates that the data stored at that physical address is valid data. The parallel address comparison circuit unit 340 is configured to identify all these valid entries and directly extract their physical address portion as a third physical address, recording it in the valid data table.

[0181] This P2L region mapping table-based approach simplifies the time-consuming step of "building a valid data table" in garbage collection from a complex process that requires reading multiple L2P tables and performing large-scale address comparisons into a direct, local P2L sub-mapping table read and parsing operation, greatly improving the efficiency of locating valid data.

[0182] In a specific hardware embodiment, the "validity resolution" operation can be implemented by reusing and extending the result generator 720 inside the parallel address comparison circuit unit 340.

[0183] Specifically, when the control unit 310 switches to P2L mode, the multiple comparators (711-714) inside the parallel address comparison circuit unit 340 can be bypassed or placed in an inactive state. The data stream of the P2L sub-map table read from the buffer 350 will be directly directed to the result generator 720.

[0184] At this point, the internal logic of the result generator 720 switches from its regular "wait for match signal" mode to "P2L parsing mode". In this mode, the result generator 720 is configured to check each entry in the P2L sub-map table one by one in a pipeline manner. For each entry, its internal simple logic circuitry (e.g., a wide-bit comparator) checks whether the logical address portion of the entry is equal to a preset "invalid flag value" (e.g., all 1s or all 0s).

[0185] If the logical address portion of an entry is not equal to the invalid flag value, the result generator 720 determines that the entry is valid and immediately captures the physical address portion of the entry, outputting it as the third physical address to the valid data table T71.

[0186] If the logical address portion of an entry is equal to an invalid flag value, the result generator 720 will discard the entry and continue processing the next entry.

[0187] By adding this "P2L parsing mode" to the result generator 720, this disclosure can efficiently reuse existing circuit resources without introducing additional large hardware units, and achieve fast parsing of P2L sub-map tables at extremely low hardware cost, further enhancing the practicality and flexibility of this disclosure.

[0188] This embodiment also provides a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0189] In summary, the memory management method, memory controller, and effective data location circuit unit proposed in this disclosure effectively solve the performance bottleneck problem caused by repeated reading of sub-mapping tables during garbage collection, especially in storage devices with limited buffer memory capacity.

[0190] By setting up a dedicated effective data location circuit unit, this disclosure can offload the computationally intensive screening and comparison tasks in the garbage collection process from the processor. Specifically, through an innovative two-stage screening strategy, the circuit unit first quickly identifies multiple candidate virtual blocks based on the effective data count, and then intelligently determines the optimal set of target virtual blocks based on the similarity between the mapping table bitmaps of these candidate virtual blocks. An integrated mapping table bitmap is generated based on this optimal set of target virtual blocks, thereby minimizing the number of sub-mapping tables that need to be read, fundamentally reducing the read load on the memory module. Finally, through parallel hardware address comparison, the final effective data table is quickly constructed.

[0191] Therefore, this disclosure not only improves the preprocessing efficiency of garbage collection operations and shortens operation latency, but also reduces read amplification by reducing unnecessary background read operations and frees up processor resources to respond to user foreground requests, ultimately improving the overall performance, response speed and service quality of the storage device.

[0192] Furthermore, this disclosure also reveals various implementation methods, including different levels of collaborative working modes such as processor-led, hardware semi-automatic, and fully automatic modes, as well as alternative implementation paths based on P2L sub-mapping tables, demonstrating the broad applicability and flexibility of the core ideas of this disclosure. Based on the teachings of this disclosure, those skilled in the art can also utilize the generated effective data tables and their physical address distribution to implement more advanced storage management strategies, such as optimizing data migration, adaptive placement of hot and cold data, performance prediction, and assisted data refresh, further extending the lifespan of the storage device and improving data reliability.

[0193] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and not to limit them; although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method, applied in a memory controller, wherein the memory controller controls a storage device configured with a memory module, characterized in that, The method includes: The processor of the memory controller instructs the valid data location circuit unit of the memory controller to perform a valid data table generation operation, including: Retrieve multiple candidate virtual blocks from a set of virtual blocks; The effective data positioning circuit unit determines multiple target virtual blocks among the multiple candidate virtual blocks based on multiple mapping table bitmaps corresponding to the multiple candidate virtual blocks, and generates an integrated mapping table bitmap corresponding to the multiple target virtual blocks. According to the integrated mapping table bitmap, one or more sub-mapping tables are obtained from the memory module; and A valid data table is generated based on multiple first physical addresses in one or more sub-mapping tables and multiple second physical addresses contained in each of the multiple target virtual blocks, wherein the valid data table is used to indicate multiple third physical addresses of multiple valid data of the multiple target virtual blocks.

2. The memory management method according to claim 1, characterized in that, The valid data positioning circuit unit includes a valid data counting and management circuit unit, and the step of acquiring the plurality of candidate virtual blocks from the plurality of virtual blocks includes: The valid data count management circuit unit sorts the valid data count values ​​of each of the plurality of virtual blocks to generate sorting information; and Based on the sorting information, multiple virtual blocks with valid data counts below a preset threshold are identified as the multiple candidate virtual blocks.

3. The memory management method according to claim 1, characterized in that, The effective data positioning circuit unit includes a mapping table bitmap management unit, and the method further includes: The mapping table bitmap is obtained via the mapping table bitmap management unit, wherein the mapping table bitmap uses multiple bits to indicate one or more sub-mapping tables associated with the data of the corresponding virtual block.

4. The memory management method according to claim 3, characterized in that, The method further includes: The target virtual blocks are determined from the candidate virtual blocks by the mapping table bitmap management unit based on the similarity between their respective mapping table bitmaps; and The mapping table bitmap management unit performs a bitwise OR operation on the mapping table bitmaps of the plurality of target virtual blocks to generate the integrated mapping table bitmap.

5. The memory management method according to claim 4, characterized in that, The method further includes: From the plurality of candidate virtual blocks, the candidate virtual block with the fewest valid data count values ​​is selected as the reference virtual block; and The similarity between other mapping tabletop maps and the reference mapping tabletop map is calculated by the mapping tabletop map management unit based on the reference mapping tabletop map corresponding to the reference virtual block.

6. The memory management method according to claim 1, characterized in that, The effective data location circuit unit includes a parallel address comparison circuit unit, and the method further includes: The parallel address comparison circuit unit compares the plurality of second physical addresses of each of the plurality of target virtual blocks in parallel, based on a selected first physical address, to locate a third physical address that matches the selected first physical address; and Record the third physical address into the valid data table.

7. The memory management method according to claim 6, characterized in that, The parallel address comparison circuit unit includes multiple comparators, each of which corresponds to a different target virtual block. The method further includes: The selected first physical address is received simultaneously via the plurality of comparators, and the selected first physical address is compared with the plurality of second physical addresses of the corresponding target virtual block to determine whether there is a matching third physical address.

8. The memory management method according to claim 7, characterized in that, The first physical address includes: Virtual block information, used to indicate the virtual block to which the first physical address belongs; and Storage address information is used to indicate the physical address of the storage unit to which the first physical address belongs.

9. The memory management method according to claim 1, characterized in that, The effective data positioning circuit unit further includes: A buffer is configured to cache data. One or more configuration registers are configured to receive trigger instructions and operation data from the processor, wherein the operation data includes one or more of the following: Valid data count value or the storage address information of the valid data count value; The mapping table bitmap or the storage address information of the mapping table bitmap; and The one or more sub-mapping tables or the storage address information of the one or more sub-mapping tables; One or more status registers are configured to record the processing status of the operation; and One or more result registers are configured to store the address information of the valid data table in the buffer.

10. The memory management method according to claim 1, characterized in that, The method further includes: The processor of the memory controller reads the valid data count values ​​of each of the plurality of virtual blocks from the memory module, and transmits the read valid data count values ​​to the valid data positioning circuit unit. The process of obtaining the one or more sub-mapping tables from the memory module according to the integrated mapping table bitmap includes: The integrated mapping table bitmap is sent to the processor via the effective data positioning circuit unit; and The processor reads one or more sub-mapping tables from the memory module according to the integrated mapping table bitmap and transmits the one or more sub-mapping tables to the valid data positioning circuit unit.

11. A memory controller for controlling a storage device configured with a memory module, characterized in that, The memory controller includes: A memory interface control circuit is configured to be electrically connected to the memory module; The processor is electrically connected to the memory interface control circuit; and The effective data positioning circuit unit is electrically connected to the processor. The processor is configured to instruct the valid data location circuit unit to perform a valid data table generation operation. The effective data positioning circuit unit or the processor is configured to acquire multiple candidate virtual blocks from a plurality of virtual blocks; The effective data positioning circuit unit is further configured to determine multiple target virtual blocks among the multiple candidate virtual blocks based on multiple mapping table bitmaps corresponding to the multiple candidate virtual blocks respectively, and generate an integrated mapping table bitmap corresponding to the multiple target virtual blocks; The effective data location circuit unit or the processor is further configured to obtain one or more sub-mapping tables from the memory module according to the integrated mapping table bitmap; and The effective data location circuit unit is further configured to generate an effective data table based on a plurality of first physical addresses in one or more sub-mapping tables and a plurality of second physical addresses contained in each of the plurality of target virtual blocks, wherein the effective data table is used to indicate a plurality of third physical addresses of a plurality of effective data of the plurality of target virtual blocks.

12. The memory controller according to claim 11, characterized in that, The effective data positioning circuit unit includes an effective data counting management circuit unit, which is configured to sort the effective data count values ​​of each of the multiple virtual blocks and determine the multiple virtual blocks with effective data count values ​​lower than a preset threshold as the multiple candidate virtual blocks.

13. The memory controller according to claim 11, characterized in that, The effective data location circuit unit includes a mapping table bitmap management unit, wherein the mapping table bitmap uses multiple bits to indicate one or more sub-mapping tables associated with the data of the corresponding virtual block.

14. The memory controller according to claim 13, characterized in that, The mapping table bitmap management unit is also configured to: Based on the similarity between the respective mapping table bitmaps of the multiple candidate virtual blocks, the multiple target virtual blocks are determined from the multiple candidate virtual blocks; as well as A bitwise OR operation is performed on the mapping table bitmap of the plurality of target virtual blocks to generate the integrated mapping table bitmap.

15. The memory controller according to claim 14, characterized in that, The mapping table bitmap management unit is also configured to: From the plurality of candidate virtual blocks, the candidate virtual block with the fewest valid data count values ​​is selected as the reference virtual block; as well as The similarity between other mapping tabletop maps and the benchmark mapping tabletop map is calculated based on the benchmark mapping tabletop map corresponding to the benchmark virtual block.

16. The memory controller according to claim 11, characterized in that, The effective data location circuit unit includes a parallel address comparison circuit unit, which is configured to compare the plurality of second physical addresses of the plurality of target virtual blocks in parallel based on a selected first physical address, so as to locate a third physical address that matches the selected first physical address, and record the third physical address to the effective data table.

17. The memory controller according to claim 16, characterized in that, The parallel address comparison circuit unit includes multiple comparators, each of which corresponds to a different target virtual block. Each comparator is configured to simultaneously receive the selected first physical address and compare the selected first physical address with multiple second physical addresses of the corresponding target virtual block.

18. The memory controller according to claim 17, characterized in that, The first physical address includes: Virtual block information, used to indicate the virtual block to which the first physical address belongs; and Storage address information is used to indicate the physical address of the storage unit to which the first physical address belongs.

19. The memory controller according to claim 11, characterized in that, The processor is also configured to: The valid data count values ​​of each of the plurality of virtual blocks are read from the memory module, and the read valid data count values ​​are transmitted to the valid data positioning circuit unit. as well as The integrated mapping table bitmap is received from the effective data positioning circuit unit, and one or more sub-mapping tables are read from the memory module according to the integrated mapping table bitmap.

20. An effective data positioning circuit unit for a storage device configured with a memory module, characterized in that, The effective data positioning circuit unit includes a mapping table bitmap management unit. The mapping table bitmap management unit includes several first logical calculation units, which are configured to input multiple mapping table bitmaps corresponding to the target virtual block and output a corresponding integrated mapping table bitmap; wherein the integrated mapping table bitmap covers the sub-mapping tables indicated by the multiple mapping table bitmaps corresponding to the target virtual block.

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