An upgrade method and system for CPLD whiteboards

Abstract

This invention discloses an upgrade method and system for CPLD whiteboards, relating to the field of communication technology. The upgrade steps are as follows: S1, file transfer to the main control memory: CPLD upgrade files for all types of whiteboards are transferred to the non-volatile memory of the main control disk via the network port; S2, setting CPLD pin levels: Different types of whiteboards correspond to four-digit model numbers. The model numbers are converted to hexadecimal numbers, and the pin levels are controlled to combine into hexadecimal numbers consistent with the model numbers; S3, setting pins to input mode: An AJE format file for setting CPLD pins to input mode is written, transferred to the main control disk memory, loaded into the target CPLD, and all pins are changed to input mode. Internal pull-up and pull-down resistors are dynamically adjusted. This invention optimizes the model using historical data, forms a closed loop with user participation, standardizes operations, reduces maintenance costs and technical barriers, and improves upgrade efficiency and reliability through multi-dimensional advantages, making it suitable for large-scale applications and long-term maintenance.

Description

Technical Field

[0001] This invention relates to the field of communication technology, specifically to an upgrade method and system for a CPLD whiteboard. Background Technology

[0002] A CPLD consists of multiple logic blocks and programmable interconnects, enabling complex logic functions and is widely used in communication equipment. Since factory upgrades of blank CPLDs are required during equipment production, current upgrade methods typically involve online upgrades and wired programming. Online upgrades require the board type to be identified to match the appropriate upgrade file. Because the CPLD is pre-programmed, the system cannot obtain the board type from the CPLD registers, necessitating manual identification of the board type and selection of the upgrade file via a JTAG programming cable. This significantly reduces efficiency, increases the risk of errors, and can easily lead to production accidents. When encountering new or customized CPLDs, the system cannot automatically recognize them, requiring developers to manually add drivers or configuration files. This results in long response times and high maintenance costs. During the upgrade process, issues such as missing files, unstable pin levels, or communication interruptions can easily lead to CPLD program corruption, requiring factory repair and increasing after-sales costs. In response, we propose an upgrade method and system for CPLD whiteboards. Summary of the Invention

[0003] To solve the above-mentioned technical problems, an upgrade method and system for CPLD whiteboards are provided. This technical solution solves the aforementioned problems.

[0004] To achieve the above objectives, the technical solution adopted by this invention is: an upgrade method for a CPLD whiteboard, the upgrade steps of which are as follows: S1. File transfer to main control memory: Transfer the CPLD upgrade files of all types of whiteboards to the non-volatile memory of the main control disk via the network port. S2. Set the CPLD pin level. Different types of whiteboards correspond to four-digit model numbers. Convert the model number to a hexadecimal number and control the pin level so that the pin level combination forms a hexadecimal number consistent with the model number. S3. Set the pins to input mode, write an AJE format file to set the CPLD pins to input mode, transfer it to the main control disk memory, load the file into the target CPLD, change all pins to input mode, and dynamically adjust the internal pull-up and pull-down resistors. S4. Read pin levels, write an AJE format file for reading CPLD pin levels, import it into the main control disk memory, read CPLD pin levels and transmit them to the CPU; S5. Parse the device model information. Extract 16 pin levels containing the board model information from the read pin levels, combine them into a hexadecimal number, and parse out the specific model information. S6. Match and upgrade file. Based on the parsed model, match the corresponding upgrade file name in the program. If the file exists in the main control disk storage, load the file into cpld through the CPU emulating the JTAG protocol to complete the upgrade; if the file does not exist, exit and report an error. S7. When an unknown hexadecimal code is detected, the user enters the model name through the UI interface. The system automatically associates the code with the model and stores it. Based on historical identification data, a simple classification model is trained to predict possible models. When a perfect match fails, the system calculates the closest known model and recommends possible alternatives.

[0005] Preferably, in step S1, the CPLD upgrade files for all types of whiteboards are obtained based on big data, including those from the official website, the manufacturer's technical team, and the manufacturer's management software. After being transferred to the non-volatile memory of the main control disk, the file is verified using a hash value method. If the verification fails, the file is upgraded and retransmitted. If the verification passes, the file is stored in a designated area.

[0006] Preferably, the file verification steps using the hash value method are as follows: Confirm compatibility with the verification tool, generate and record the original hash value after downloading the file; Before transmission, use a tool to generate a hash value for the local file and compare it with the original value; During transmission, data transmission is guaranteed based on the TCP protocol; After the transfer, log in to the main control disk, generate the hash value again through the command line and graphical tools, and compare it with the original value again. If they match, the verification is successful; otherwise, the file needs to be transferred again. The method for comparing hash values ​​with the original values ​​is to compare them character by character.

[0007] Preferably, in step S2, the model number is converted to a hexadecimal number using a bitwise decomposition method; The steps to control the pin level are as follows: Based on CPLD, the pins of each digit of the hexadecimal number are explicitly indicated; Write logic code using the VHDL hardware description language and define input and output ports; Based on hexadecimal values, set the corresponding pins to high / low levels to match the model values; The code is compiled using the CPLD development tool, syntax errors are checked, a download file is generated, and the download file is written to the CPLD chip using the download tool. By observing the pin levels with a logic analyzer and oscilloscope, it can be verified whether the output is consistent with the expected hexadecimal number.

[0008] Preferably, the step of dynamically adjusting the internal pull-up and pull-down resistors in step S3 is as follows: Determine the target pin, declare the model using the AJE format file, and set the pin as an input; Upon power-on initialization, the default pull-down is applied, and after a delay, the configuration is checked and updated pin by pin, with periodic evaluation and handling of abnormal changes. The detection cycle and stable determination time were optimized based on the actual scenario through monitoring and verification by a logic analyzer.

[0009] Preferably, the periodic evaluation is implemented using a time window detection algorithm, the framework of which is as follows: Upon power-up, all pins are configured to pull-down mode by default to avoid floating interference and wait for the external circuit to stabilize. After the delay ends, read the current level value of each pin in sequence, open the status sampling window, and continuously monitor whether there is a level transition on the pin. If the voltage level is stable within the window, the system enters a state determination phase; if a transition occurs, the sampling window is reset and monitoring continues. The register is updated based on a stable level state; the pull-up resistor is enabled when the level is high, and the pull-down resistor is maintained when the level is low. Record the current configuration status and periodically evaluate the status; A global evaluation is triggered every 10ms, and the detection-determination-configuration process is re-executed for all pins.

[0010] Preferably, the step of matching the corresponding upgrade file name in the program in step S6 is as follows: Build an index table by naming upgrade files according to specifications, and scan the directory to generate an in-memory index; During matching, the parsed model numbers are searched for and matched, and similarity is calculated based on the Euclidean formula. Extract version numbers from the matched files, sort the latest versions according to semantic rules, verify file integrity, and check compatibility information.

[0011] Preferably, the step of predicting possible model numbers in step S7 is as follows: Collect existing model-code association data, extract features, convert them into numerical features for model training, and augment the data; The model is trained by dividing the training set and the validation set, and the parameters are optimized based on the validation results. The feature distance between the unknown code and the known model is calculated based on cosine similarity. The classifier results are then fused to output a predicted model with confidence.

[0012] Preferably, in step S7, possible alternatives are recommended by presenting the selected candidate models in a list format, with each candidate model labeled with a similarity score, recommendation reason, and risk warning; after the user confirms the alternative, the system automatically adds the association between the model and the code to the index.

[0013] An upgrade system for a CPLD whiteboard includes: The file transfer module transfers the CPLD upgrade file to the non-volatile memory of the main control disk via the network port; The model encoding module converts the four-digit model number on the whiteboard into a hexadecimal number and controls the CPLD pin level combination to form the corresponding code; The pin configuration module sets the cpld pin to input mode via an AJE file and dynamically adjusts the internal pull-up / pull-down resistors. The level reading module reads the CPLD pin levels from the AJE file and transmits them to the CPU for parsing. The model parsing module extracts hexadecimal codes from the 16 pin levels and parses them into specific model information; The upgrade matching module matches the upgrade file based on the parsed model and completes the CPLD upgrade via the JTAG protocol; The self-learning module handles unknown model codes and expands the model library through machine learning and user interaction.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention stores all upgrade files in the main control memory, with the entire process controlled by a program. It eliminates the need for manual file selection, simplifying the upgrade process and improving efficiency. Model identification based on hardware characteristic level combinations ensures accurate file-device matching. A self-learning mechanism expands the supported device types, offering flexible hardware configuration and dynamic pin resistance adjustment to adapt to different electrical characteristics. A robust error handling mechanism optimizes the model using historical data, allowing for user participation in a closed-loop process. Standardized operation reduces maintenance costs and lowers technical barriers. Through these multi-dimensional advantages, it enhances upgrade efficiency and reliability, making it suitable for large-scale applications and long-term maintenance. Attached Figure Description

[0015] Figure 1 This is a flowchart of the upgrade steps of the present invention; Figure 2 This is a system framework diagram for the upgrade of this invention. Detailed Implementation

[0016] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0017] Reference Figure 1As shown, an upgrade method for a CPLD whiteboard is described, and the upgrade steps are as follows: S1. File transfer to main control memory: Transfer the CPLD upgrade files of all types of whiteboards to the non-volatile memory of the main control disk via the network port. S2. Set the CPLD pin level. Different types of whiteboards correspond to four-digit model numbers. Convert the model number to a hexadecimal number and control the pin level so that the pin level combination forms a hexadecimal number consistent with the model number. S3. Set the pins to input mode, write an AJE format file to set the CPLD pins to input mode, transfer it to the main control disk memory, load the file into the target CPLD, change all pins to input mode, and dynamically adjust the internal pull-up and pull-down resistors. S4. Read pin levels, write an AJE format file for reading CPLD pin levels, import it into the main control disk memory, read CPLD pin levels and transmit them to the CPU; S5. Parse the device model information. Extract 16 pin levels containing the board model information from the read pin levels, combine them into a hexadecimal number, and parse out the specific model information. S6. Match and upgrade file. Based on the parsed model, match the corresponding upgrade file name in the program. If the file exists in the main control disk storage, load the file into cpld through the CPU emulating the JTAG protocol to complete the upgrade; if the file does not exist, exit and report an error. S7. When an unknown hexadecimal code is detected, the user enters the model name through the UI interface. The system automatically associates the code with the model and stores it. Based on historical identification data, a simple classification model is trained to predict possible models. When a perfect match fails, the system calculates the closest known model and recommends possible alternatives.

[0018] This application boasts a high degree of automation, storing all upgrade files in the main control memory. The entire process is program-controlled, eliminating the need for manual file selection, simplifying the upgrade process, and improving efficiency. It offers accurate model identification and strong compatibility, using hardware-characteristic level combinations to identify models, ensuring precise matching between files and devices. Furthermore, it can expand supported device types through a self-learning mechanism. The hardware configuration is flexible, dynamically adjusting pin resistance to adapt to different electrical characteristics. It simulates the JTAG protocol for compatibility with mainstream CPLDs, and features a robust error handling mechanism. Files are verified before upgrades, and there is fault tolerance for unknown models, enhancing reliability. Its scalability and intelligence are outstanding, capable of optimizing models through historical data, with user participation forming a closed loop. This method requires no specialized tools, standardizes operations, and reduces maintenance costs and technical barriers. Through multiple advantages, it improves upgrade efficiency and reliability, making it suitable for large-scale applications and long-term maintenance.

[0019] In step S1, the CPLD upgrade files for all types of whiteboards are obtained based on big data, including those from the official website, the manufacturer's technical team, and the manufacturer's management software. After being transferred to the non-volatile memory of the main control disk, the file is verified using a hash value method. If the verification fails, the file is upgraded and retransmitted. If the verification passes, the file is stored in the designated area.

[0020] This application obtains upgrade files from multiple channels, including official websites, manufacturer technical teams, and manufacturer management software, covering both public and private resources. Compared to a single source, this method can more comprehensively collect upgrade files for various CPLD whiteboards, avoiding the inability to upgrade specific models due to missing files. This greatly improves the system's compatibility and coverage. The big data acquisition method can track the dynamics of each channel in real time and obtain the latest released upgrade files promptly. When manufacturers release new CPLD firmware to fix vulnerabilities on their official websites, the system can quickly obtain them, ensuring timely upgrades for whiteboards, guaranteeing device operational security and performance stability, and avoiding potential risks caused by using older firmware versions. The underlying hash value verification is implemented through binary data operations using hardware accelerators (such as SHA256 accelerators) or firmware-level algorithms. The logic is as follows: Hash value pre-stored: The standard hash value (such as SHA256 value) of the upgrade file is pre-stored in a fixed storage area (such as OTP partition) of the main control disk as a verification benchmark; Data extraction: The main controller reads the transmitted file data segment by segment from the non-volatile memory and transfers it to the hash operation buffer through DMA (direct memory access) technology, reducing CPU intervention.

[0021] Hash operation: The hardware accelerator iteratively operates on the buffer data according to a hash algorithm (such as SHA256). After processing each segment of data, the intermediate hash value is updated until all data is processed and the target hash value is generated.

[0022] Comparison and judgment: The target hash value is compared bit by bit with the pre-stored standard hash value through hardware logic gate circuits. If all bits are consistent, the "verification passed" signal (high level) is triggered; otherwise, the "verification failed" signal (low level) is triggered.

[0023] The steps for file verification using the hash value method are as follows: Confirm the appropriate verification tool. This type of tool should support the hash algorithm corresponding to the target file, be able to stably read the binary data stream of the file and generate a unique identifier. After the file is downloaded, immediately use the tool to process the original file, generate the original hash value and record it in text form. This original value is like the digital fingerprint of the file and is the benchmark for all subsequent verification operations. The generation process must ensure the stability of the tool's operating environment to avoid numerical deviations caused by memory fluctuations or process interference. Local verification before file transfer is a crucial preliminary step. During the operation, the same verification tool is used to regenerate the hash value of the local file to be transferred. The generated value needs to be compared with the original hash value recorded earlier. The comparison process is strictly performed character by character, starting from the first character and checking sequentially until the last character. If all characters are completely consistent, it means that the local file has not been tampered with or damaged, and the transfer process can proceed. If any character mismatch occurs, the file needs to be retrieved again to rule out any possible errors or data corruption during local storage. During transmission, the characteristics of the TCP protocol ensure data integrity. The TCP protocol establishes a reliable connection through a three-way handshake. Each data packet is numbered during data transmission. The receiving end verifies the order and integrity of the data packets. If packet loss or out-of-order transmission is detected, the sending end is immediately requested to retransmit. This underlying transmission mechanism ensures the continuous transmission of file data, reduces the risk of hash value changes caused by network fluctuations, and ensures that the transmitted file data is consistent with the local file to be transmitted. After the file transfer is complete, a final verification must be performed by logging into the main control disk. The login process uses a preset permission verification mechanism to ensure operational security. Then, a hash value is generated for the file on the main control disk using both a command-line tool and a graphical tool. The command-line tool calls the underlying hash algorithm by inputting specific commands, directly reading the binary data of the file in the storage medium for calculation. The graphical tool presents the calculation process through a visual interface. Its underlying logic is the same as that of the command-line tool, only the interaction method is different. The hash values ​​generated by the two tools must be compared character by character with the original hash value. Only when all comparison results show that the characters are completely consistent can the verification be considered successful, and the file can be used for subsequent operations. If any comparison shows a character mismatch, it means that there is data distortion during the transmission process. The file must be retransmitted, and the above verification process must be repeated until the verification is successful. In step S2, the model number is converted to hexadecimal using a bitwise decomposition method; The steps to control the pin level are as follows: Based on CPLD, the pins of each digit of the hexadecimal number are explicitly indicated; Write logic code using the VHDL hardware description language and define input and output ports; Based on hexadecimal values, set the corresponding pins to high / low levels to match the model values; The code is compiled using the CPLD development tool, syntax errors are checked, a download file is generated, and the download file is written to the CPLD chip using the download tool. By observing the pin levels with a logic analyzer and oscilloscope, it can be verified whether the output is consistent with the expected hexadecimal number.

[0024] The pins of a CPLD chip are physically connected to the internal logic units via metal wires. Each pin corresponds to a specific I / O buffer (including output drivers and input receivers). Each bit (4 binary bits) of a hexadecimal number needs to establish a fixed mapping relationship with a group of pins. The underlying logic is as follows: by querying the chip datasheet to find the physical number of the pin and the connection relationship with the internal logic resources, it is determined which pins are configured as output mode (output driver enabled). Bits 0 to 3 and bits 4 to 7 of the hexadecimal number are grouped and bound to the corresponding pin physical channels. The least significant bit of the hexadecimal number (bit 0 in 0x01) may correspond to pin 12, and the next least significant bit (bit 1) may correspond to pin 13. This mapping relationship is fixed by the chip's pin constraint file (the underlying layer is register configuration instructions) to ensure that logic signals can be accurately transmitted to physical pins. Implementation of VHDL code The essence of the VHDL language is to describe the logical relationships of hardware circuits. After compilation, its code is transformed into the connection methods of logic gate circuits (such as AND gates, OR gates, and flip-flops) inside the CPLD. The underlying logic of the input and output port definitions is as follows: The input port corresponds to the external signal receiving path. The underlying layer latches the external level signal (high level corresponds to logic 1, low level corresponds to logic 0) through the input register of the I / O buffer and passes the signal to the internal combinational logic or sequential logic unit. The output port corresponds to the output path of the internal signal. The underlying layer stores the result of the internal logic operation through the output register, and then the output driver amplifies the signal driving capability to convert the logic level into a physical level that conforms to the pin electrical specifications (such as 3.3V high level and 0V low level). Logical statements in the code (such as IF-ELSE and CASE statements) will be converted into corresponding logic gate combinations by the synthesis tool. For example, the description "when the input is 0x03, pin A is high" will be converted into a series circuit of NAND gates and OR gates for the input signal to ensure that a high-level drive signal is generated at the output when the condition is met. Low-level operation matching pin level with hexadecimal value The process of converting hexadecimal values ​​to pin levels is achieved through level mapping implemented by combinational logic circuits within the CPLD. The underlying logic is as follows: The hexadecimal number is first broken down into a binary bit stream (e.g., 0x0A is broken down into 1010), and each binary bit corresponds to a logical state (1 or 0). The internal logic circuit converts the logic state of each binary bit into the control signal of the corresponding pin according to the preset mapping relationship: when the logic state is 1, the PMOS transistor of the output driver is turned on and the NMOS transistor is turned off, and the pin outputs a high level through the pull-up circuit; when the logic state is 0, the NMOS transistor is turned on and the PMOS transistor is turned off, and the pin outputs a low level through the pull-down circuit. This process is achieved through the instantaneous response of the hardware circuit, without any software delay. As long as the input hexadecimal value is determined, the corresponding pin level combination will be stably output within nanoseconds, ensuring real-time matching with the model value. During compilation, the development tool performs syntax parsing on the VHDL code, generates a gate-level netlist (describing the connection relationships between logic gates), and then uses timing analysis tools to verify whether the delay of the logic circuit meets the timing requirements of pin level switching (such as setup time and hold time). Finally, a binary configuration file (such as a JED file) is generated. This file is essentially a set of configuration data that controls the connection status of the programmable logic units (such as LUTs and flip-flops) inside the CPLD. The download process is implemented through a programmer (such as a JTAG programmer). The underlying layer sends configuration instructions to the CPLD through the TCK (clock), TMS (mode select), and TDI (data input) pins of the JTAG interface, and writes the binary configuration file bit by bit into the chip's configuration memory (such as SRAM). The configuration data is transmitted to each logic unit through the internal bus, and its connection status is changed in real time, completing the mapping from logic description to physical circuit. The essence of observation using logic analyzers and oscilloscopes is to acquire the physical level signals of the pins through probes and convert them into observable waveforms or data; The logic analyzer connects to the target pin through a high-impedance probe, converting continuous analog level signals into discrete digital signals (high level is recorded as 1, low level as 0), capturing level changes according to a preset sampling frequency (such as 100MHz), splicing them into a binary sequence, and then converting them into hexadecimal numbers for comparison with the expected value. The oscilloscope uses an analog signal acquisition circuit to display the voltage change waveform of the pin level in real time. The observer can verify whether the level switching meets the timing requirements (such as whether there are glitches or whether the delay exceeds the standard) by measuring the duration of the high and low levels and the transition time of the waveform, and ensure that the output level signal is consistent with the expected electrical characteristics.

[0025] The steps for dynamically adjusting the internal pull-up and pull-down resistors in step S3 are as follows: Determine the target pin, declare the model using the AJE format file, and set the pin as an input; Upon power-on initialization, the default pull-down is applied, and after a delay, the configuration is checked and updated pin by pin, with periodic evaluation and handling of abnormal changes. The detection cycle and stable determination time were optimized based on the actual scenario through monitoring and verification by a logic analyzer.

[0026] This application targets pin configuration. The AJE format file declares the chip model and specifies the resistor hardware resources. Pins are set as inputs via the configuration mode register, and the output driver is disabled. At this time, the pull-up / pull-down resistor switches are off by default. Next, power-on initialization and dynamic adjustment are performed. After power-on, the initialization program reads the default configuration, activates the pull-down resistor switch to ground the pin, and waits for the signal to stabilize before checking each pin individually: an internal comparator monitors the level; if it is higher than a threshold, pull-up is triggered; otherwise, pull-down is maintained. The configuration is updated via the pin control register. Periodic evaluation relies on timer interrupts, checking the pin status at preset intervals. If an anomaly occurs, the configuration is reset and retesting is performed. Monitoring, verification, and parameter optimization: The logic analyzer collects level signals, converts them into digital quantities, records the trajectory, and compares the waveforms to determine the resistance noise reduction effect; the model is declared and pins are set as inputs using AJE format files, eliminating the need to manually configure each pin one by one, greatly reducing manual operation; the default pull-down is initialized upon power-on and automatically detects and updates, which can quickly complete the resistance configuration of a large number of pins, especially suitable for multi-pin CPLD whiteboards, significantly improving the work efficiency in the upgrade preparation stage and saving time and costs.

[0027] The periodic evaluation is implemented using a time window detection algorithm, the framework of which is as follows: Upon power-up, all pins are configured to pull-down mode by default to avoid floating interference and wait for the external circuit to stabilize. After the delay ends, read the current level value of each pin in sequence, open the status sampling window, and continuously monitor whether there is a level transition on the pin. If the voltage level is stable within the window, the system enters a state determination phase; if a transition occurs, the sampling window is reset and monitoring continues. The register is updated based on a stable level state; the pull-up resistor is enabled when the level is high, and the pull-down resistor is maintained when the level is low. Record the current configuration status and periodically evaluate the status; A global evaluation is triggered every 10ms, and the detection-determination-configuration process is re-executed for all pins.

[0028] After power-on, the power monitoring module triggers a configuration register write instruction, enabling all pins to be configured in pull-down mode by activating the NMOS switch to avoid floating interference. The delay phase is controlled by a timer, waiting for the external circuit to stabilize. After the delay ends, the timer interrupt triggers the pin scanning circuit, selecting pins in sequence. The ADC sampling is started momentarily when the pull-down resistor is turned off. The status sampling window is opened by the timer count cycle, sampling once every 100μs and temporarily storing the result. If a level transition occurs, the hardware state machine resets the counter and resets the window. If stable, the determination circuit verifies and triggers a register update. A high level enables the pull-up, and a low level maintains the pull-down. The status is stored in a non-volatile register. A global evaluation is triggered every 10ms by a timer interrupt. The scanning circuit re-detects all pins, compares the current configuration with the new sampled state, and repeats the configuration detection process if they are inconsistent. Interrupt priority control is used to ensure timing stability. The time window detection algorithm is used to periodically evaluate pin levels, forming a closed-loop guarantee from initialization to dynamic adjustment. The default pull-down mode upon power-on avoids floating interference, laying the foundation for stable detection. Pin-by-pin monitoring combined with a window reset mechanism accurately filters noise and prevents level misjudgment. Resistors are dynamically configured according to stable levels to adapt to different hardware requirements and enhance compatibility. A 10ms global evaluation provides real-time response to environmental changes, ensuring continuous system stability. The algorithm logic is simple and the parameters are adjustable, reducing resource consumption and facilitating optimization and expansion for different models, comprehensively improving the reliability and flexibility of pin level management during CPLD whiteboard upgrades.

[0029] The step in step S6 that matches the corresponding upgrade file name in the program is as follows: Upgrade files must be named according to a unified standard, typically including core information such as chip model, hardware version, and release date. The format should be "model, hardware version, and release date in bin" to ensure that the filename itself can intuitively reflect the file attributes. The index table is built based on this standardized naming and is achieved by scanning the storage directory: the underlying layer traverses all files in the directory through the file system interface, extracts key fields (model, version, etc.) from the filename, and stores metadata such as filename, storage path, and file size according to a preset data structure (such as a hash table or linked list) to generate an in-memory index. The in-memory index will be synchronized with directory changes in real time. When a file is added or deleted, the index table is dynamically updated through an interrupt mechanism to ensure that the index information is consistent with the actual file status, laying the foundation for subsequent fast lookup. During the model parsing phase, the model string extracted from external input or the device to be upgraded is converted into a feature vector, mapping each character to an ASCII code value to form a set of numerical sequences. During matching, the model feature vectors corresponding to all files are retrieved from the memory index table, and the spatial distance between the two is calculated using the Euclidean formula: the smaller the distance, the higher the model similarity. When calculating the distance between the target model CPLD100A and CPLD100 in the index, since only the last character is different, the distance value is small, and it is judged as a high match; while the distance value with FPGA200 is large, so it is directly excluded. This algorithm is implemented by a hardware acceleration unit (such as a vector processor) and can complete batch matching in microseconds, improving search efficiency. The version number extracted from the matched file must conform to semantic rules. The underlying layer uses a string splitting algorithm to decompose the version number into a numerical array. When sorting, the major version number, minor version number, and revision number are compared in order of priority, and the largest value is determined to be the latest version. File integrity verification follows the hash value comparison logic, calculating the hash value of the latest version of the file and comparing it with the pre-stored value to ensure that the file has not been tampered with. Compatibility information check is performed by parsing the metadata block in the file header to extract information such as supported hardware models and minimum firmware versions, and matching them field by field with the current device parameters. If a conflict exists, a compatibility error message is triggered and the upgrade process is terminated; otherwise, the file is confirmed to be usable and the upgrade process continues. This application names upgrade files according to specifications and constructs an index table. It scans the directory to generate an in-memory index, which can structure scattered file information and enable fast retrieval. When the system needs to match upgrade files for a specific model, the in-memory index can directly locate the target file range, avoiding traversing all files and significantly shortening the retrieval time. It calculates the spatial distance of the model string (i.e., the square root of the sum of the squares of the differences between the corresponding positions of each character) using the Euclidean formula, quantifying the similarity between different models. Even if there are slight differences between the input model and the file name (such as spelling errors or different version suffixes), it can still match the closest file, reducing matching failures caused by non-strict naming and improving system compatibility.

[0030] The step in step S7 for predicting possible model numbers is as follows: Collect existing model-code association data, extract features, convert them into numerical features for model training, and augment the data; The model is trained by dividing the training set and the validation set, and the parameters are optimized based on the validation results. The feature distance between the unknown code and the known model is calculated based on cosine similarity. The classifier results are then fused to output a predicted model with confidence.

[0031] This application divides the model into training and validation sets for training and optimizes the parameters based on the validation results, which can effectively avoid the problems of overfitting or underfitting the model. This scientific training process ensures that the model can stably and accurately predict the model type in practical applications, reduce the risk of misjudgment caused by model defects, and provide reliable technical support for the identification of unknown models. It can quantify the similarity between unknown codes and known models, and at the same time fuse classifier results and output predicted models with confidence scores. It not only provides possible model suggestions, but also intuitively reflects the reliability of the prediction through the confidence score index.

[0032] In step S7, possible alternatives are recommended by presenting the filtered candidate models in a list format. Each candidate model is labeled with a similarity score, the reason for recommendation, and a risk warning. After the user confirms the alternative, the system automatically adds the association between the model and the code to the index.

[0033] This application presents candidate models in a list format, annotating similarity scores, reasons for recommendation, and risk warnings. This provides users with intuitive and comprehensive information for reference. Users can quickly determine the degree of matching between candidate models and unknown devices through similarity scores. Combined with reasons for recommendation (such as similar functional characteristics) and risk warnings (such as possible incompatibility of some functions), users can make more scientific decisions, avoid upgrade failures caused by blind selection, and save time and costs.

[0034] An upgrade system for a CPLD whiteboard includes: The file transfer module transfers the CPLD upgrade file to the non-volatile memory of the main control disk via the network port; The model encoding module converts the four-digit model number on the whiteboard into a hexadecimal number and controls the CPLD pin level combination to form the corresponding code; The pin configuration module sets the cpld pin to input mode via an AJE file and dynamically adjusts the internal pull-up / pull-down resistors. The level reading module reads the CPLD pin levels from the AJE file and transmits them to the CPU for parsing. The model parsing module extracts hexadecimal codes from the 16 pin levels and parses them into specific model information; The upgrade matching module matches the upgrade file based on the parsed model and completes the CPLD upgrade via the JTAG protocol; The self-learning module handles unknown model codes and expands the model library through machine learning and user interaction.

[0035] Specific Cases A large educational institution deployed a batch of different models of CPLD whiteboards for multimedia teaching. During the upgrade process, technicians used dedicated file transfer software via the network port to batch transfer the upgrade files for all CPLD models collected from the official website, the manufacturer's technical team, and the manufacturer's management software to the non-volatile memory on the main control disk. For a batch of 30 different whiteboards, the technicians completed the transfer of all upgrade files in less than 10 minutes. During the transfer, the files were verified using hash values ​​to ensure their integrity, laying the foundation for the smooth progress of subsequent upgrade work.

[0036] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A method for upgrading a CPLD whiteboard, characterized in that, The upgrade steps are as follows: S1. File transfer to main control memory: Transfer the CPLD upgrade files of all types of whiteboards to the non-volatile memory of the main control disk via the network port. S2. Set the CPLD pin level. Different types of whiteboards correspond to four-digit model numbers. Convert the model number to a hexadecimal number and control the pin level so that the pin level combination forms a hexadecimal number consistent with the model number. S3. Set the pins to input mode, write an AJE format file to set the CPLD pins to input mode, transfer it to the main control disk memory, load the file into the target CPLD, change all pins to input mode, and dynamically adjust the internal pull-up and pull-down resistors. S4. Read pin levels, write an AJE format file for reading CPLD pin levels, import it into the main control disk memory, read CPLD pin levels and transmit them to the CPU; S5. Parse the device model information. Extract 16 pin levels containing the board model information from the read pin levels, combine them into a hexadecimal number, and parse out the specific model information. S6. Match and upgrade file. Based on the parsed model, match the corresponding upgrade file name in the program. If the file exists in the main control disk storage, load the file into cpld through the CPU emulating the JTAG protocol to complete the upgrade. If the file does not exist, the program will exit and display an error message. S7. When an unknown hexadecimal code is detected, the user enters the model name through the UI interface. The system automatically associates the code with the model and stores it. Based on historical identification data, a simple classification model is trained to predict possible models. When a perfect match fails, the system calculates the closest known model and recommends possible alternatives.

2. The upgrade method for a CPLD whiteboard according to claim 1, characterized in that, In step S1, the CPLD upgrade files for all types of whiteboards are obtained based on big data, including those from the official website, the manufacturer's technical team, and the manufacturer's management software. After being transferred to the non-volatile memory of the main control disk, the file is verified using a hash value method. If the verification fails, the file is upgraded and retransmitted. If the verification passes, the file is stored in the designated area.

3. The upgrade method for a CPLD whiteboard according to claim 2, characterized in that, The steps for file verification using the hash value method are as follows: Confirm compatibility with the verification tool, generate and record the original hash value after downloading the file; Before transmission, use a tool to generate a hash value for the local file and compare it with the original value; During transmission, data transmission is guaranteed based on the TCP protocol; After the transfer, log in to the main control disk, generate the hash value again through the command line and graphical tools, and compare it with the original value again. If they match, the verification is successful; otherwise, the file needs to be transferred again. The method for comparing hash values ​​with the original values ​​is to compare them character by character.

4. The upgrade method for a CPLD whiteboard according to claim 1, characterized in that, In step S2, the model number is converted to hexadecimal using a bitwise decomposition method; The steps to control the pin level are as follows: Based on cpld, the pins of each digit of the hexadecimal number are clearly indicated; Write logic code using the VHDL hardware description language and define input and output ports; Based on hexadecimal values, set the corresponding pins to high / low levels to match the model values; The code is compiled using the CPLD development tool, syntax errors are checked, a download file is generated, and the download file is written to the CPLD chip using the download tool. By observing the pin levels with a logic analyzer and oscilloscope, it can be verified whether the output is consistent with the expected hexadecimal number.

5. The upgrade method for a CPLD whiteboard according to claim 1, characterized in that, The steps for dynamically adjusting the internal pull-up and pull-down resistors in step S3 are as follows: Determine the target pin, declare the model using the AJE format file, and set the pin as an input; Upon power-on initialization, the default pull-down is applied, and after a delay, the configuration is checked and updated pin by pin. Abnormal changes are periodically evaluated and handled. The detection cycle and stable determination time were optimized based on the actual scenario through monitoring and verification by a logic analyzer.

6. The upgrade method for a CPLD whiteboard according to claim 5, characterized in that, The periodic evaluation is implemented using a time window detection algorithm, the framework of which is as follows: Upon power-up, all pins are configured to pull-down mode by default to avoid floating interference and wait for the external circuit to stabilize. After the delay ends, read the current level value of each pin in sequence, open the status sampling window, and continuously monitor whether there is a level transition on the pin; If the voltage level is stable within the window, the system enters a state determination phase. If a transition occurs, the sampling window is reset and monitoring continues. The register is updated based on a stable level state; the pull-up resistor is enabled when the level is high, and the pull-down resistor is maintained when the level is low. Record the current configuration status and periodically evaluate the status; A global evaluation is triggered every 10ms, and the detection-determination-configuration process is re-executed for all pins.

7. The upgrade method for a CPLD whiteboard according to claim 1, characterized in that, The step in step S6 that matches the corresponding upgrade file name in the program is as follows: Build an index table by naming upgrade files according to specifications, and scan the directory to generate an in-memory index; During matching, the parsed model numbers are searched for and matched, and similarity is calculated based on the Euclidean formula. Extract version numbers from the matched files, sort the latest versions according to semantic rules, verify file integrity, and check compatibility information.

8. The method for upgrading a CPLD whiteboard according to claim 1, characterized in that, The step in step S7 for predicting possible model numbers is as follows: Collect existing model-code association data, extract features, convert them into numerical features for model training, and augment the data; The model is trained by dividing the training set and the validation set, and the parameters are optimized based on the validation results. The feature distance between the unknown code and the known model is calculated based on cosine similarity. The classifier results are then fused to output a predicted model with confidence.

9. The method for upgrading a CPLD whiteboard according to claim 1, characterized in that, In step S7, possible alternatives are recommended by presenting the filtered candidate models in a list format. Each candidate model is labeled with a similarity score, the reason for recommendation, and a risk warning. After the user confirms the alternative, the system automatically adds the association between the model and the code to the index.

10. An upgrade system for a CPLD whiteboard, characterized in that, include: The file transfer module transfers the CPLD upgrade file to the non-volatile memory of the main control disk via the network port; The model encoding module converts the four-digit model number on the whiteboard into a hexadecimal number and controls the CPLD pin level combination to form the corresponding code; The pin configuration module sets the cpld pin to input mode via an AJE file and dynamically adjusts the internal pull-up / pull-down resistors. The level reading module reads the CPLD pin levels from the AJE file and transmits them to the CPU for parsing. The model parsing module extracts hexadecimal codes from the 16 pin levels and parses them into specific model information; The upgrade matching module matches the upgrade file based on the parsed model and completes the CPLD upgrade via the JTAG protocol; The self-learning module handles unknown model codes and expands the model library through machine learning and user interaction.

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