A transmitting device, a receiving device, a die, a chip, and a communication system

Abstract

The embodiment of the present application discloses a sending device, a receiving device, a crystal grain, a chip and a communication system, relates to the integrated circuit technical field, and can reduce transmission delay of parallel data transmission of a multi-physical layer circuit interface module between different crystal grains. The sending device is arranged in a first crystal grain; the sending device comprises a plurality of first physical layer circuit interface modules, wherein each first physical layer circuit interface module is configured to send a plurality of data signals to a second crystal grain; each first physical layer circuit interface module comprises a sending delay submodule, and the sending delay submodule is configured to delay the sending of the plurality of data signals according to a sending delay parameter determined in data transmission training, so that the absolute value of the time difference between the arrival time of the data signal of a first target path of each first physical layer circuit interface module at the second crystal grain is less than a first threshold value. The present application is suitable for inter-crystal grain communication.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a transmitting device, a receiving device, a die, a chip, and a communication system. Background Technology

[0002] To meet the demands of faster data processing and advanced AI / machine learning workloads, many chip designs are shifting towards a multi-chip interconnect architecture (Chiplet).

[0003] In a multi-die interconnect architecture, different dies can transmit signals in parallel through multiple physical layer circuit interface modules (PHYs), and each PHY module can contain multiple data transmission paths. Due to differences in physical routing, data misalignment often occurs between different PHY modules and between different data transmission paths within the same PHY module.

[0004] To address this, in related technologies, the data receiver typically uses a first-in-first-out (FIFO) buffer to read and write data, synchronizing multiple data streams within the same physical layer circuit interface module. Then, by waiting for several clock cycles, data alignment is performed between the physical layer circuit interface modules. However, while this data alignment method achieves data alignment, it generates significant data latency. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a transmitting device, a receiving device, a die, a chip, and a communication system, which can greatly reduce the transmission delay of data transmission in parallel between multi-physical layer circuit interface modules of different dies.

[0006] In a first aspect, embodiments of the present invention provide a transmitting device disposed on a first die; the transmitting device includes a plurality of first physical layer circuit interface modules, wherein each first physical layer circuit interface module is configured to transmit multiple data signals to a second die; each first physical layer circuit interface module includes a transmission delay submodule, the transmission delay submodule being configured to delay the transmission of the multiple data signals according to transmission delay parameters determined in data transmission training, such that the absolute value of the time difference between the arrival times of the data signals of the first target path of each first physical layer circuit interface module at the second die is less than a first threshold; the second die is configured to delay the transmission of the data signal of the second target path among the received multiple data signals according to the reception delay parameters determined in the data transmission training, such that the absolute value of the phase difference between the delayed data signal of the second target path and the data signal of the first target path is less than a second threshold, wherein the data signal of the second target path is the data signal of other paths among the multiple data signals besides the data signal of the first target path.

[0007] In one embodiment, the first physical layer circuit interface module further includes: at least one data transmission submodule, each of the at least one data transmission submodule being configured to transmit one data signal to the second die under the triggering of a first clock signal; the transmission delay submodule includes a first transmission delay unit, one end of the first transmission delay unit being coupled to the signal source of the first clock signal, and the other end being coupled to the clock input terminal of the at least one data transmission submodule, and being configured to delay the first clock signal according to the transmission delay parameter.

[0008] In one embodiment, the first physical layer circuit interface module further includes: an accompanying clock transmission submodule, configured to transmit a second clock signal to the second die when the data transmission submodule transmits the data signal to the second die, so that the second die receives the data signal according to the second clock signal, wherein the second clock signal has the same frequency and a different phase from the first clock signal; the transmission delay submodule further includes a second transmission delay unit, one end of the second transmission delay unit is coupled to the signal source of the second clock signal, and the other end is coupled to the accompanying clock transmission submodule, configured to delay the second clock signal according to the transmission delay parameters.

[0009] In one implementation, the delay durations of the first transmission delay unit and the second transmission delay unit are equal.

[0010] In one embodiment, the first physical layer circuit interface module further includes a phase-locked loop (PLL), the input of which is coupled to a preset clock source; the first output of which serves as the signal source of the first clock signal and is coupled to the first transmission delay unit; and the second output of which is connected in series with a preset phase adjustment element and serves as the signal source of the second clock signal and is coupled to the second transmission delay unit.

[0011] In one embodiment, the transmission delay submodule is used to compensate for the difference in physical trace delay when the signal is transmitted from the preset clock source to the input terminal of the phase-locked loop in each of the first physical layer circuit interface modules, and / or to compensate for the difference in substrate trace delay when the signal is transmitted from the output terminal of the accompanying clock transmission submodule of each of the first physical layer circuit interface modules to the input terminal of the second die.

[0012] In one embodiment, each of the first physical layer circuit interface modules is configured to send multiple preset data signals to the second die during data transmission training, wherein each preset data signal is identical to the others; the transmission delay submodule is further configured to adjust the transmission delay of the multiple data signals during data transmission training to determine the transmission delay parameter, wherein the transmission delay parameter is the delay duration corresponding to the transmission delay submodule when the absolute value of the difference between the arrival times of the preset data signals of the first target path of each of the first physical layer circuit interface modules to the second die is less than a first threshold.

[0013] Secondly, embodiments of the present invention also provide a receiving device disposed on a second die; the receiving device includes a plurality of second physical layer circuit interface modules, wherein each second physical layer circuit interface module is configured to receive multiple data signals transmitted by a first die; each second physical layer circuit interface module includes a receiving delay submodule, the receiving delay submodule being configured to delay the transmission of a second target path data signal among the multiple data signals received by the second physical layer circuit interface module according to a receiving delay parameter determined in data transmission training, so that the absolute value of the phase difference between the delayed second target path data signal and the first target path data signal is less than a second threshold; wherein, each first target path data signal is a data signal whose absolute value of the time difference between arriving at the corresponding second physical layer circuit interface module is less than a first threshold; the second target path data signal is the data signal of other paths among the multiple data signals besides the first target path data signal.

[0014] In one embodiment, the second physical layer circuit interface module further includes: a clock-in-circuit receiving submodule configured to receive a second clock signal transmitted by a first die, wherein the second clock signal has the same frequency but a different phase than the first clock signal used by the first die to transmit the data signal; at least one data receiving submodule, each of the at least one data receiving submodule configured to receive one channel of the data signal transmitted by the first die under the triggering of the second clock signal; at least one flip-flop, each flip-flop corresponding to one of the data receiving submodules; the data input terminal of each flip-flop is coupled to the output terminal of the corresponding data receiving submodule; and the clock input terminal of each flip-flop is coupled to the output terminal of the clock-in-circuit receiving submodule. In one embodiment, the receiving delay submodule is configured to: delay the transmission of the data signal of the second target path between the output terminal of the data receiving submodule and the data input terminal of the corresponding trigger; and / or delay the transmission of the second clock signal between the output terminal of the accompanying clock receiving submodule and the clock input terminal of the corresponding trigger.

[0015] In one embodiment, the receiving delay submodule includes at least one receiving delay unit, which corresponds one-to-one with the at least one data receiving submodule; each receiving delay unit is coupled between the output terminal of the corresponding data receiving submodule and the data input terminal of the corresponding flip-flop, and / or, coupled between the output terminal of the accompanying clock receiving submodule and the clock input terminal of the corresponding flip-flop.

[0016] In one embodiment, the receiving device further includes: a data buffer array module comprising a plurality of buffer chains, wherein each buffer chain includes a multi-level register connected in series; the plurality of buffer chains correspond one-to-one with at least one flip-flop in each of the second physical layer circuit interface modules; the input terminal of each buffer chain is coupled to the data output terminal of a corresponding flip-flop; the accompanying clock receiving submodule is further configured to generate a buffer enable signal in response to receiving the second clock signal; the data buffer array module is configured to receive and buffer the data signals output by each of the flip-flops according to the buffer enable signal and the second clock signal.

[0017] In one embodiment, each of the second physical layer circuit interface modules is configured to receive multiple preset data signals sent by the first die during data transmission training, wherein each preset data signal is identical to the others; the receiving device further includes a detection module coupled to the data cache array module, configured to compare the preset data signals stored in each cache chain during data transmission training, and determine whether the data transmission training has ended based on the comparison result.

[0018] In one embodiment, the detection module is configured to: during data transmission training, read data from the registers at the same level of each of the buffer chains once every preset number of clock cycles of the second clock signal to obtain a set of detection data; wherein, when the multiple preset data signals are received triggered by a single edge of the second clock signal, the number of the preset number of clock cycles is equal to the number of bits contained in each register, or, when the multiple preset data signals are received triggered by both edges of the second clock signal, the number of the preset number of clock cycles is equal to half the number of bits contained in each register; in response to the detection data in each set of detection data being identical to each other, determine that the preset data signals are aligned and end the data transmission training; or, in response to at least two detection data in at least one set of detection data being different from each other, determine that the preset data signals are not aligned and continue the data transmission training.

[0019] In one embodiment, the accompanying clock receiving submodule is further configured to output a preset level signal in response to receiving the second clock signal to obtain the buffer control signal; the receiving device further includes a counting module coupled to the accompanying clock receiving submodule, configured to start counting the clock cycles of the second clock signal after receiving the buffer control signal, and output the buffer enable signal to the data buffer array module in response to counting N clock cycles, where N is a positive integer.

[0020] In one embodiment, each of the second physical layer circuit interface modules is configured to receive multiple preset data signals sent by the first die during data transmission training, wherein each preset data signal is identical to the others; the receiving delay submodule is further configured to perform delay adjustment on the transmission of the received preset data signal of the second target path during data transmission training to determine the receiving delay parameter, wherein the receiving delay parameter is the delay duration corresponding to the receiving delay submodule when the absolute value of the phase difference between the preset data signal of the second target path and the preset data signal of the first target path after the delay is less than a second threshold.

[0021] Thirdly, embodiments of the present invention also provide a die, the die comprising any of the transmitting devices provided in embodiments of the present invention, and / or any of the receiving devices provided in embodiments of the present invention.

[0022] Fourthly, embodiments of the present invention also provide a chip comprising at least two dies, the at least two dies comprising a first die and a second die coupled to each other, wherein the first die is any die provided in embodiments of the present invention, and the second die is any die provided in embodiments of the present invention.

[0023] Fifthly, embodiments of the present invention also provide a communication system, including a transmitting device and a receiving device; the transmitting device is used to transmit information to the receiving device; the receiving device is used to receive information transmitted by the transmitting device; wherein the transmitting device is any of the transmitting devices provided in the embodiments of the present invention, and the receiving device is any of the receiving devices provided in the embodiments of the present invention.

[0024] The embodiments of the present invention provide a transmitting device, a receiving device, a die, a chip, and a communication system. Each first physical layer circuit interface module can transmit multiple data signals to a second die. Furthermore, the transmission delay submodule of each first physical layer circuit interface module can delay the transmission of the multiple data signals according to transmission delay parameters determined during data transmission training. This delay ensures that the absolute value of the time difference between the arrival times of the data signals of the first target path in each first physical layer circuit interface module at the second die is less than a first threshold. Thus, when the first threshold is sufficiently small, the data signals of the first target path in different first physical layer circuit interface modules can arrive at the second die almost simultaneously. This allows for the alignment of some data signals between the first physical layer circuit interface modules and enables the second die to use the data signals of the first target path as a reference for... The received delay parameters determined during data transmission training are further used to delay the data signal of the second target path among the multiple data signals. Since the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than the second threshold, and the data signals of the first target paths in each first physical layer circuit interface module have been aligned with each other, in this way, when the second threshold is small enough, the multiple data signals in multiple first physical layer circuit interface modules can be fully aligned in the second die, without having to synchronize the multiple data within the same physical layer circuit interface module through read and write operations on the first-in-first-out buffer, as in the prior art, and then wait for several clock cycles to align the data of each physical layer circuit interface module. Therefore, the transmission delay of multiple physical layer circuit interface modules transmitting data in parallel between different dies can be greatly reduced. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of a transmitting device provided for an embodiment of the present invention; Figure 2 A schematic diagram of a first physical layer circuit interface module in a transmitting device provided in an embodiment of the present invention; Figure 3 Another schematic diagram of the first physical layer circuit interface module in the transmitting device provided for an embodiment of the present invention; Figure 4 Another schematic diagram of the first physical layer circuit interface module in the transmitting device provided for an embodiment of the present invention; Figure 5 A schematic diagram of a receiving device provided for an embodiment of the present invention; Figure 6 A schematic diagram of a second physical layer circuit interface module in a receiving device provided in an embodiment of the present invention; Figure 7 A schematic diagram of a second physical layer circuit interface module in a receiving device provided in an embodiment of the present invention; Figure 8 Another schematic diagram of the receiving device provided in the embodiments of the present invention; Figure 9 A schematic diagram of a grain structure provided for an embodiment of the present invention; Figure 10 A schematic diagram of a chip structure provided for an embodiment of the present invention; Figure 11 A schematic diagram of a communication system provided for an embodiment of the present invention; Figure 12 A detailed structural diagram of a communication system provided for an embodiment of the present invention. Detailed Implementation

[0027] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0028] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0029] In a first aspect, embodiments of the present invention provide a transmitting device that can significantly reduce the transmission delay of data transmission between multi-physical layer circuit interface modules of different chips in parallel.

[0030] like Figure 1As shown, an embodiment of the present invention provides a transmitting device 10 disposed on a first die 1. The transmitting device 10 may include a plurality of first physical layer circuit interface modules 11, wherein each first physical layer circuit interface module 11 is configured to transmit multiple data signals to a second die 2. Each first physical layer circuit interface module 11 may include a transmitting delay submodule 111, which may be configured to delay the transmission of the multiple data signals according to a transmitting delay parameter determined in data transmission training, so that the absolute value of the time difference between the arrival times of the data signals of the first target path in each first physical layer circuit interface module at the second die is less than a first threshold. The second die 2 may be configured to delay the transmission of the data signal of the second target path among the received multiple data signals according to the receiving delay parameter determined in the data transmission training, so that the absolute value of the phase difference between the delayed data signal of the second target path and the data signal of the first target path is less than a second threshold, wherein the data signal of the second target path is the data signal of other paths among the multiple data signals besides the data signal of the first target path.

[0031] In the transmitting device 10 provided in the embodiments of the present invention, each first physical layer circuit interface module 11 can transmit multiple data signals to the second die 2. Furthermore, the transmission delay submodule 111 of each first physical layer circuit interface module 11 can delay the transmission of the multiple data signals according to the transmission delay parameters determined in the data transmission training, so that the absolute value of the time difference between the arrival times of the data signals of the first target path in each first physical layer circuit interface module 11 at the second die 2 is less than a first threshold. Thus, when the first threshold is sufficiently small, the data signals of the first target path in different first physical layer circuit interface modules 11 can arrive at the second die almost simultaneously. This allows some data signals between each first physical layer circuit interface module 11 to be aligned with each other, and also allows the second die 2 to use the data signals of the first target path as a reference to transmit data signals. The received delay parameters determined during transmission training are further used to delay the data signal of the second target path among the multiple data signals. Since the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than the second threshold, and the data signals of the first target paths in each first physical layer circuit interface module 11 have been aligned with each other, in this way, when the second threshold is small enough, the multiple data signals in multiple first physical layer circuit interface modules can be fully aligned in the second die, without having to synchronize the multiple data within the same physical layer circuit interface module through read and write operations on the first-in-first-out buffer, as in the prior art, and then wait for several clock cycles to align the data of each physical layer circuit interface module. Therefore, the transmission delay of multiple physical layer circuit interface modules transmitting data in parallel between different dies can be greatly reduced.

[0032] In embodiments of the present invention, the transmission delay submodule 111 of each first physical layer circuit interface module 11 can delay the transmission of the multiple data signals within the first physical layer circuit interface module 11 according to the transmission delay parameters determined in the data transmission training, so that the absolute value of the difference in the time when the data signals of the first target path in each first physical layer circuit interface module 11 arrive at the second die 2 is less than a first threshold.

[0033] Here, the first threshold can be a very small time period, specifically determined based on the clock period of the second clock signal and the data alignment accuracy requirements during data transmission. For example, in one example, the first threshold can be 5% to 50% of the clock period of the second clock signal, such as 10%. Thus, if the absolute value of the time difference between the arrival times of the data signals of the first target paths in each first physical layer circuit interface module 11 and the arrival times of the data signals of the first target paths in each first physical layer circuit interface module 11 are less than the first threshold, it can be considered that the data signals of the first target paths in each first physical layer circuit interface module 11 arrive at the second die almost simultaneously. In this way, after each data signal from each first physical layer circuit interface module 11 is transmitted to the second die, the second die can use the data signals of the first target paths in each first physical layer circuit interface module 11 as a reference to further delay each data signal within the same first physical layer circuit interface module, so that the absolute value of the phase difference between the delayed second target path data signal and the first target path data signal is less than the second threshold. The second threshold can be a very small phase difference, which can be determined based on the phase difference of one clock cycle of the second clock signal and the requirements for data alignment accuracy in data transmission. For example, in one case, the second threshold can be 5% to 50% of the phase difference of one clock cycle of the second clock signal, such as 10%.

[0034] Because the external circuit environments of each first physical layer circuit interface module differ, the arrival times of data signals from different first physical layer circuit interface modules to the second die will also differ. Therefore, in one embodiment, a transmission delay submodule 111 can be used to delay the transmission of each data signal in the corresponding first physical layer circuit interface module 11, thereby compensating for this difference. The specific delay duration can be determined by the transmission delay parameters determined through data transmission training.

[0035] Furthermore, in some embodiments, the internal circuit environment of each data signal within each first physical layer circuit interface module is different, which may cause the arrival time of each data signal within the same physical layer circuit interface module to be different. Therefore, the transmission delay parameter of each transmission delay submodule 111 can be determined based on the data signal of a portion of the corresponding first physical layer circuit interface module, which is the data signal of the first target path.

[0036] For example, in one scenario, the first physical layer interface module PHY2 has three data paths (ch21, ch22, and ch23) that send three data signals to the second die. These three data signals arrive at the second die at different times. The first physical layer interface module PHY3 has four data paths that send four data signals to the second die. The data signals from each of the three data paths (ch31, ch32, ch33, and ch34) arrive at the second die at the same time. Therefore, the transmit delay submodule in PHY2 can delay the data signals sent by PHY2 based on any one of the three data paths (e.g., ch21). Similarly, the transmit delay submodule in PHY3 can delay the data signals sent by PHY3 based on any one of the three data paths (e.g., ch22), so that the delayed data paths ch21 and ch32 arrive at the second die almost simultaneously.

[0037] In embodiments of the present invention, a first target path can be determined as needed. The embodiments of the present invention do not limit this. For example, in one example, the data signal of the first target path can be the data signal that arrives at the second die latest in the first physical layer circuit interface module.

[0038] Optionally, in embodiments of the present invention, the data signal of the first target path can be either a single data signal or multiple data signals, and the embodiments of the present invention do not limit this. When the data signal of the first target path is multiple data signals, the internal circuit environment of these multiple data signals within the first physical layer circuit interface module can be relatively similar, so that these multiple data signals can reach the second die almost simultaneously.

[0039] like Figure 2As shown, in one embodiment of the present invention, the first physical layer circuit interface module 11 may include at least one data transmission submodule 112 in addition to the transmission delay submodule 111. Each of the at least one data transmission submodule 112 may be configured to transmit one data signal to the second die 2 under the triggering of the first clock signal. Optionally, in the embodiments of the present invention, the data signal may be triggered by a single edge (e.g., rising edge) of the first clock signal or by two double edges (e.g., rising edge and falling edge) of the first clock signal. The embodiments of the present invention do not limit this. The transmission delay submodule 111 may specifically include a first transmission delay unit 1111. One end of the first transmission delay unit 1111 is coupled to the signal source of the first clock signal, and the other end is coupled to the clock input terminal of at least one data transmission submodule 112, and is configured to delay the first clock signal according to the transmission delay parameters.

[0040] In this embodiment, each data signal of the first physical layer circuit interface module 11 is transmitted by a corresponding data transmission submodule 112, and each data transmission submodule 112 in the same first physical layer circuit interface module 11 transmits data signals under the drive of the first clock signal. Therefore, the first transmission delay unit 1111 of the transmission delay submodule in each first physical layer circuit interface module 11 can be located between the signal source of the first clock signal and the clock input terminal of each data transmission submodule 112, and the delay of the first clock signal is used to delay multiple data signals.

[0041] Furthermore, such as Figure 3 As shown, in another embodiment of the present invention, the first physical layer circuit interface module 11 may further include an accompanying clock transmission submodule 113, configured to transmit a second clock signal to the second die 2 when the data transmission submodule 112 transmits the data signal to the second die 2, so that the second die 2 receives the data signal according to the second clock signal, wherein the second clock signal has the same frequency and a different phase from the first clock signal. Based on this, the transmission delay submodule 111 may further include a second transmission delay unit 1112, one end of which is coupled to the signal source of the second clock signal, and the other end is coupled to the accompanying clock transmission submodule 113, configured to delay the second clock signal according to the transmission delay parameters.

[0042] In other words, in this embodiment, in addition to sending multiple data signals to the second chip 2, the transmitting device can also send a second clock signal that accompanies the multiple data signals to the second chip 2, so that after receiving the second clock signal, the second chip can receive the data signals sent by the transmitting device under the drive of the second clock signal.

[0043] It should be noted that in order to ensure that the second chip can correctly receive the data signal, the data signal and the second clock signal can maintain a good phase relationship (for example, the trigger edge of the second clock signal can be in the middle of the valid period of the data signal). The relative phase relationship between the second clock signal and the data signal can be trained using existing training methods, which will not be elaborated here.

[0044] In an embodiment of the present invention, since the second chip receives the data signal under the drive of the second clock signal, after the data signal is delayed by the first transmission delay unit, the second clock signal can also be delayed accordingly so that the data signal can be correctly received by the second chip.

[0045] For example, in one instance, if the second chip can correctly receive the various data signals sent by the transmitting device under the drive of the second clock signal before the data signal is delayed by the transmission delay submodule, it indicates that the data signal and the second clock signal already have a relatively good relative phase relationship. In order to maintain the relative phase relationship between the two, the delay durations of the first transmission delay unit 1111 and the second transmission delay unit 1112 can be equal, so that the relative phase relationship between the delayed data signal and the second clock signal remains unchanged.

[0046] In embodiments of the present invention, the first clock signal and the second clock signal have the same frequency but different phases. To obtain such a first clock signal and a second clock signal, as follows: Figure 4 As shown, in one embodiment, the first physical layer circuit interface module 11 may further include a phase-locked loop 114. The input terminal of the phase-locked loop 114 can be used to couple with a preset clock source. The first output terminal of the phase-locked loop 114 can be used as the signal source of the first clock signal and is coupled with the first transmission delay unit 1111. The second output terminal of the phase-locked loop 114, after being connected in series with a preset phase adjustment element (the phase adjustment unit can be used for data transmission training in the prior art to maintain a relatively good phase relationship between the data signal and the second clock signal), can be used as the signal source of the second clock signal and is coupled with the second transmission delay unit 1112.

[0047] In one embodiment of the present invention, the phase-locked loops 114 of each first physical layer circuit interface module 11 all use a preset clock source as the input signal. However, due to the different physical locations of each first physical layer circuit interface module 11, the physical trace delay from the preset clock source to the input terminal of the phase-locked loop 114 of each first physical layer circuit interface module 11 will also be different. Similarly, the substrate trace delay from the output terminal of the accompanying clock transmission submodule 113 of each first physical layer circuit interface module to the input terminal of the second die 2 will also be different. Therefore, the delay of the first clock signal and the second clock signal by different transmission delay submodules 111 in different first physical layer circuit interface modules 11 can be used to compensate for the difference in the physical trace delay of the signal from the preset clock source to the input terminal of the phase-locked loop in each first physical layer circuit interface module, and / or to compensate for the difference in the substrate trace delay of the signal from the output terminal of the accompanying clock transmission submodule of each first physical layer circuit interface module to the input terminal of the second die, thereby compensating for the influence of the difference in the external environment of each first physical layer circuit interface module on the data signal delay.

[0048] In the foregoing embodiments, the transmission delay submodule 111 can delay the transmission of each data signal according to the transmission delay parameters determined in the data transmission training, thereby affecting the transmission time of each data signal. However, the embodiments of the present invention are not limited to this. In other embodiments of the present invention, if the transmitting device has not yet undergone data transmission training, or if there have been new changes since the last data transmission training (e.g., changes in ambient temperature), data transmission training can also be performed.

[0049] Specifically, in one embodiment of the present invention, each first physical layer circuit interface module 11 can be configured to send multiple preset data signals to the second die 2 during data transmission training, wherein each preset data signal is identical to the others; here, the preset data signal can be existing data. In one example, the preset data signal can be a data signal with multiple bytes, and each byte is different from the others, so as to identify different bytes; the embodiments of the present invention do not limit this. For example, in one example, it can be the hexadecimal number F581, that is, the value of each of the multiple data signals sent by the first physical layer circuit interface module 11 is F581. In another example, it can be the hexadecimal number 665544332211, that is, the value of each of the multiple data signals sent by the first physical layer circuit interface module 11 is 665544332211.

[0050] Based on this, the transmission delay submodule 111 can also be configured to adjust the delay of the first clock signal during data transmission training to determine the transmission delay parameter. The transmission delay parameter is the delay duration corresponding to the transmission delay submodule 111 when the absolute value of the difference between the arrival times of the preset data signals of the first target paths of each first physical layer circuit interface module 11 to the second die 2 is less than a first threshold. For example, during data transmission training, the transmission delay submodule 111 can adjust the delay duration multiple times. For instance, the delay duration may include 10 picoseconds, 20 picoseconds, 30 picoseconds, etc., with different delay durations causing differences in the arrival times of the data signals to the second die 2. If the delay duration of the first physical layer circuit interface module PHY7 is 30 picoseconds and the delay duration of the first physical layer circuit interface module PHY8 is 20 picoseconds, and the absolute value of the difference between the arrival time of the preset data signal of the first target path of the first physical layer circuit interface module PHY7 and the preset data signal of the first target path of the first physical layer circuit interface module PHY8 at the second crystal 2 is less than the first threshold of 5 picoseconds, then it can be determined that the transmission delay parameter of the transmission delay submodule of the first physical layer circuit interface module PHY7 is 30 picoseconds and the transmission delay parameter of the transmission delay submodule of the first physical layer circuit interface module PHY8 is 20 picoseconds.

[0051] Accordingly, in a second aspect, embodiments of the present invention also provide a receiving device that can greatly reduce the transmission delay of data transmission in parallel between multi-physical layer circuit interface modules of different chips.

[0052] like Figure 5 As shown, the receiving device 20 provided in the embodiment of the present invention is disposed on the second chip 2; the receiving device 20 may include a plurality of second physical layer circuit interface modules 21, wherein each second physical layer circuit interface module 21 may be configured to receive multiple data signals transmitted by the first chip 1; each second physical layer circuit interface module 21 may include a receiving delay submodule 211, which may be configured to delay the transmission of the data signal of the second target path among the multiple data signals received by the second physical layer circuit interface module according to the receiving delay parameters determined in the data transmission training, so that the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than a second threshold; wherein, the data signal of each first target path is a data signal whose absolute value of the time difference between arriving at the corresponding second physical layer circuit interface module 21 is less than a first threshold; the data signal of the second target path is the data signal of other paths among the multiple data signals besides the data signal of the first target path.

[0053] The receiving device 20 provided in the embodiments of the present invention can receive multiple data signals transmitted by the first chip 1 in each second physical layer circuit interface module 21. The receiving delay submodule 211 of each second physical layer circuit interface module 21 can delay the transmission of the data signal of the second target path in the multiple data signals received by the second physical layer circuit interface module 21 according to the receiving delay parameters determined in the data transmission training, so that the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than a second threshold. Since the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than the second threshold, and the absolute value of the time difference between the arrival times of the data signals of each of the first target paths at the corresponding second physical layer circuit interface modules 21 is also less than the first threshold, in this way, when the first threshold and the second threshold are sufficiently small, the multiple data signals received by the multiple second physical layer circuit interface modules 21 can be fully aligned in the second die. Unlike the prior art, it is not necessary to first synchronize the multiple data within the same physical layer circuit interface module through read and write operations on the first-in-first-out buffer, and then wait for several clock cycles to align the data between the physical layer circuit interface modules. Therefore, the transmission delay of multiple physical layer circuit interface modules transmitting data in parallel between different dies can be greatly reduced.

[0054] In embodiments of the present invention, the receiving delay submodule 211 of each second physical layer circuit interface module 21 can delay the transmission of the data signal of the second target path among the multiple data signals received by the second physical layer circuit interface module 21 according to the receiving delay parameters determined in the data transmission training, so that the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than the second threshold.

[0055] Here, the second threshold can be a very small phase difference, which can be determined based on the phase difference of one clock cycle of the second clock signal and the requirements for data alignment accuracy in data transmission. For example, in one case, the second threshold can be 5% to 50% of the phase difference of one clock cycle of the second clock signal, such as 10%.

[0056] Since the data signals received by the same second physical layer circuit interface module 21 have traveled through different transmission paths to reach the second die, the arrival times of the data signals received by the same second physical layer circuit interface module may also be different. Therefore, when the absolute value of the difference between the arrival times of the data signals of each first target path to the corresponding second physical layer circuit interface module 21 is less than the first threshold, the data signals of the second target path can be further delayed by the receiving delay submodule 211 based on the data signals of the first target path, so that the data signals of the second target path among the multiple data signals received by the same second physical layer circuit interface module 21 can be aligned with each other in the second die.

[0057] For example, in one instance, the second physical layer circuit interface module PHY6 has three data paths ch61, ch62, and ch63. The data signals from data paths ch61 and ch62 arrive at the second die at the same time, t5, while the data signal from data path ch63 arrives at t6. The different arrival times of data paths ch61 and ch63 mean that the phases of their data signals are also different; for example, the phase difference may be significant. If the data signal for the first target path is the data signal from data path ch61, and the data signal for the second target path is the data signal from data path ch63, then the receiving delay submodule 211 can delay the transmission of the data signal from data path ch63 according to the receiving delay parameters determined during data transmission training, so that the absolute value of the phase difference between the delayed data signal from data path ch63 and the data signal from data path ch61 is less than a second threshold.

[0058] like Figure 6 As shown, in one embodiment of the present invention, the second physical layer circuit interface module 21 may include, in addition to the receive delay submodule 211, a clock receiving submodule 212, at least one data receiving submodule 213 and at least one trigger 214.

[0059] The accompanying clock receiving submodule 212 can receive a second clock signal transmitted by the first chip 1. The second clock signal has the same frequency but a different phase than the first clock signal used by the first chip 1 to transmit the data signal. Each of the at least one data receiving submodule 213 can receive one channel of the data signal transmitted by the first chip 1 when triggered by the second clock signal. At least one flip-flop 214 can correspond one-to-one with a data receiving submodule 213; the data input terminal of each flip-flop 214 is coupled to the output terminal of the corresponding data receiving submodule 213; the clock input terminal of each flip-flop 214 is coupled to the output terminal of the accompanying clock receiving submodule 212.

[0060] Based on this, the receiving delay submodule 211 can specifically delay the transmission of the data signal of the second target path between the output terminal of the data receiving submodule 213 and the data input terminal of the corresponding flip-flop 214; and / or, the receiving delay submodule 211 can specifically delay the transmission of the second clock signal between the output terminal of the accompanying clock receiving submodule 212 and the clock input terminal of the corresponding flip-flop 214.

[0061] For example, see Figure 6 In one embodiment, the receive delay submodule 211 may include at least one receive delay unit 2110, with each receive delay unit 2110 corresponding to at least one data receive submodule 213. Each receive delay unit 2110 is coupled between the output terminal of the corresponding data receive submodule 213 and the data input terminal of the corresponding trigger 214, and / or, see [link to relevant documentation]. Figure 7 Each receiving delay unit 2110 can also be coupled between the output of the accompanying clock receiving submodule 212 and the clock input of the corresponding flip-flop 214.

[0062] In embodiments of the present invention, there may be phase deviations (or delay deviations) between the data signals received by the data receiving submodules 213 of the same second physical layer circuit interface module 12. By coupling the trigger 214 to the data receiving submodules 213 in a one-to-one correspondence, the data signals output by the data receiving submodules 213 can be transmitted down one level. In order to reduce or eliminate these phase deviations by controlling the transmission delay of the data signals by the trigger 214, the data signals can be aligned with each other.

[0063] Specifically, when controlling the transmission delay of the data signal by the trigger 214, the duration of the data signal transmission from the output of the data receiving submodule 213 to the data input of the trigger 214 can be controlled, as can the duration of the second clock signal transmission from the output of the accompanying clock receiving submodule 212 to the clock input of the trigger 214. Both durations can also be controlled, as long as the phase difference between the data signals output by the outputs of each trigger 214 is less than the second threshold. The embodiments of the present invention do not limit this.

[0064] The data signals output from the flip-flop 214 have been aligned with each other. In one embodiment of the present invention, the data signals output from the flip-flop 214 can also be stored so that the second die can utilize these data.

[0065] Specifically, such as Figure 8 As shown, in one embodiment, the receiving device 20 may further include: a data buffer array module 22, which may include a plurality of buffer chains 221, wherein each buffer chain 221 may include a multi-level register 2210 connected in series with each other; the plurality of buffer chains 221 correspond one-to-one with at least one flip-flop 214 in each second physical layer circuit interface module 21; the input terminal of each buffer chain 221 is coupled to the data output terminal of a corresponding flip-flop 214.

[0066] In embodiments of the present invention, each stage register 2210 may have multiple bits, thereby converting the serial data output by the flip-flop 214 into parallel data. When reading data from the data buffer array module 22, each bit in the flip-flop 214 can be read in parallel based on the local clock of the second die 2. The frequency of the local clock of the second die 2 can be 1 / M of the frequency of the second clock signal, where M is the number of bits contained in each stage register 2210. For example, in one example, each stage register 2210 contains 8 bits, then the frequency of the local clock of the second die 2 is 1 / 8 of the frequency of the second clock signal.

[0067] Based on this, the on-path clock receiving submodule 212 can also be configured to generate a buffer enable signal in response to receiving the second clock signal; the data buffer array module 22 is specifically configured to receive and buffer the data signals output by each trigger 214 according to the buffer enable signal and the second clock signal.

[0068] In this embodiment, the on-path clock receiving submodule 212, in addition to receiving the second clock signal, can also generate a buffer enable signal upon receiving the second clock signal. Since the second clock signal is an on-path clock, that is, a clock that accompanies the data signal, receiving the second clock signal indicates that a data signal has also been sent from the first die 1 and received by the second die 2. Therefore, the data signal can also be stored subsequently. The on-path clock receiving submodule 212 generating the buffer enable signal upon receiving the second clock signal enables the data buffer array module 22 to start, allowing for the storage of the data signal.

[0069] In one embodiment, the data cache array module 22 can store data under the trigger of a gated clock. Based on this, the cache enable signal can be used as the gate signal of the gated clock signal. When the cache enable signal is valid, the second clock signal can be transmitted to the clock input terminal of the data cache array module 22. When the cache enable signal is invalid, the second clock signal will not be transmitted to the clock input terminal of the data cache array module 22, thereby effectively reducing power consumption.

[0070] Furthermore, in one embodiment of the present invention, the accompanying clock receiving submodule 212 can also be configured to output a preset level signal in response to receiving the second clock signal to obtain the buffer enable signal; the receiving device 20 can also include a counting module 23, coupled to the accompanying clock receiving submodule 212, configured to start counting the clock cycles of the second clock signal after receiving the buffer control signal, and output the buffer enable signal to the data buffer array module 22 in response to counting N clock cycles, where N is a positive integer. In this way, when the frequency of the second clock signal is high, more time can be allowed for the level change of the buffer enable signal, effectively avoiding providing the buffer enable signal to the data buffer array module 22 before it reaches the preset level, thereby effectively improving the reliability of the circuit.

[0071] In the foregoing embodiments, the receiving delay submodule 211 can delay the transmission of the data signal of the second target path among the received multi-channel data signals according to the receiving delay parameters determined in the data transmission training. However, the embodiments of the present invention are not limited to this. In other embodiments of the present invention, if the receiving device has not yet undergone data transmission training, or if there have been new changes since the last data transmission training (e.g., changes in ambient temperature), then data transmission training can also be performed.

[0072] Specifically, in one embodiment of the present invention, each second physical layer circuit interface module 21 can be configured to receive multiple preset data signals sent by the first die 1 during data transmission training, wherein each preset data signal is identical to the others; here, the preset data signal can be existing data. In one example, the preset data signal can be a data signal with multiple bytes, and each byte is different from the others, so as to identify different bytes. The embodiments of the present invention do not limit this. For example, in one example, it can be the hexadecimal number F581, that is, the value of each data signal in the multiple data signals received by the second physical layer circuit interface module 21 is F581. In another example, it can be the hexadecimal number 665544332211, that is, the value of each data signal in the multiple data signals received by the second physical layer circuit interface module 11 is 665544332211.

[0073] Based on this, the receiving delay submodule 211 can also be configured to adjust the transmission delay of the received preset data signal of the second target path during data transmission training, so as to determine the receiving delay parameter. The receiving delay parameter is the delay duration corresponding to the receiving delay submodule 211 when the absolute value of the phase difference between the preset data signal of the second target path and the preset data signal of the first target path after the delay is less than a second threshold.

[0074] For example, during data transmission training, the receiving delay submodule 211 corresponding to the second target path data signal can adjust the delay duration multiple times. For instance, the delay duration can include 10 picoseconds, 20 picoseconds, 30 picoseconds, etc. Different delay durations result in different delays in the transmission of the data signal in the second chip 2. If, in the second physical layer circuit interface module PHY6, the receiving delay submodule R3 delays the data signal of the second target path datalane3 for 20 picoseconds, and the absolute value of the phase difference between the delayed second target path data signal and the first target path data signal is less than a second threshold, then the receiving delay parameter of the receiving delay submodule R3 of the second physical layer circuit interface module PHY6 can be determined to be 20 picoseconds.

[0075] In one embodiment of the present invention, during data transmission training, the receiving delay submodule 211 for receiving the data signal of the second target path can adjust the delay duration multiple times. After finding a delay duration that meets a preset condition, the data transmission training can be terminated. The preset condition may include: the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay of the specified delay duration is less than a second threshold. As mentioned earlier, when both the first and second thresholds are small, the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay of the specified delay duration is less than the second threshold, thus ensuring that the data signals received by each of the second physical layer circuit interface modules 21 are aligned with each other.

[0076] In one embodiment of the present invention, the alignment of the data signals received by each second physical layer circuit interface module 21 with each other can be determined by reading the data in the data buffer array module 22.

[0077] Specifically, in one embodiment, each second physical layer circuit interface module 21 can be configured to receive multiple preset data signals sent by the first die 1 during data transmission training, wherein each preset data signal is identical to the others; based on this, the receiving device 20 may further include: a detection module 24, coupled to the data buffer array module 22, configured to compare the preset data signals stored in each buffer chain 221 during data transmission training, and determine whether the data transmission training has ended based on the comparison result.

[0078] In one embodiment of the present invention, each data receiving submodule 213 can receive serial data sent by the first die 1 and send the received serial data to the data cache array module 22 via a trigger 214. Each cache chain 221 in the data cache array 22 may include multiple registers connected in series, and each register may contain multiple bits. Based on this, the detection module 24 can be configured as follows: during data transmission training, every preset number of clock cycles of the second clock signal, data is read once from the same level register of each buffer chain 221 to obtain a set of detection data; wherein, when the multiple preset data signals are received triggered by a single edge of the second clock signal, the number of preset number of clock cycles is equal to the number of bits contained in each register, or, when the multiple preset data signals are received triggered by both edges of the second clock signal, the number of preset number of clock cycles is equal to half the number of bits contained in each register; in response to the fact that each set of detection data is the same as the others, it is determined that the preset data signals are aligned with each other, and the data transmission training ends; or, in response to the fact that at least two sets of detection data are different from each other, it is determined that the preset data signals are not aligned with each other, and the data transmission training continues.

[0079] For example, in one embodiment of the present invention, when a register of each cache chain 221 is filled for the first time, the detection module 24 can read the register for the first time, and thereafter can read the register once every preset number of clock cycles of the second clock signal.

[0080] For example, the data buffer array module 22 includes four buffer chains 221, each of which includes 10 levels of registers connected in series. Each level of register contains 8 bits. The preset data signals are received triggered by a single edge of the second clock signal. The detection module 24 can read data from the same level register (e.g., the first level register along the data signal transmission direction) of these four buffer chains 221 every 8 clock cycles of the second clock signal to obtain a set of detection data (each set of detection data includes 4 data points). The 10 levels of registers can be read 10 times to obtain 10 sets of detection data. If all 4 data points in each of these 10 sets of detection data are the same, it can be determined that the preset data signals are aligned with each other, and the data transmission training ends. If, in at least one set (e.g., the 7th set), the second data point is different from the other three, it is determined that the preset data signals are not aligned with each other, and the data transmission training continues.

[0081] Thirdly, embodiments of the present invention also provide a die that can greatly reduce the transmission delay of data transmission between multi-physical layer circuit interface modules of different dies in parallel.

[0082] like Figure 9 As shown, the die 3 provided in the embodiments of the present invention may include any of the transmitting devices 10 and / or any of the receiving devices 20 provided in the foregoing embodiments. Therefore, the corresponding technical effects can also be achieved, as has been described in detail above, and will not be repeated here.

[0083] Fourthly, embodiments of the present invention also provide a chip that can greatly reduce the transmission delay of data transmission in parallel between multi-physical layer circuit interface modules of different chips.

[0084] like Figure 10 As shown, the chip 4 provided in the embodiments of the present invention may include at least two dies, which may include a first die 1 and a second die 2 coupled to each other. The first die 1 may be any of the dies provided in the foregoing embodiments, and the second die 2 may be any of the dies provided in the foregoing embodiments. Therefore, the corresponding technical effects can be achieved, as detailed above, and will not be repeated here.

[0085] Fifthly, embodiments of the present invention also provide a communication system that can greatly reduce the transmission delay of data transmission between multi-physical layer circuit interface modules of different chips in parallel.

[0086] like Figure 11 As shown, an embodiment of the present invention provides a communication system 5 that may include a transmitting device 10 and a receiving device 20; the transmitting device 10 is used to transmit information to the receiving device 20; the receiving device 20 is used to receive information transmitted by the transmitting device 10; wherein, the transmitting device 10 is any of the transmitting devices provided in the foregoing embodiments, and the receiving device 20 is any of the receiving devices provided in the foregoing embodiments. Therefore, the corresponding technical effects can also be achieved, as has been described in detail above, and will not be repeated here.

[0087] For example, a detailed structural diagram of the communication system provided in the embodiments of the present invention can be as follows: Figure 12 As shown.

[0088] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0089] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0090] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0091] For ease of description, the above apparatus is described by dividing it into various functional units / sub-modules. Of course, in implementing this invention, the functions of each unit / sub-module can be implemented in one or more software and / or hardware components.

[0092] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0093] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A transmitting device, characterized in that, Located in the first grain; The transmitting device includes a plurality of first physical layer circuit interface modules, wherein each first physical layer circuit interface module is configured to transmit multiple data signals to the second die; Each of the first physical layer circuit interface modules includes a transmission delay submodule, which is configured to delay the transmission of the multiple data signals according to the transmission delay parameters determined in the data transmission training, so that the absolute value of the difference between the arrival times of the data signals of the first target path of each of the first physical layer circuit interface modules at the second die is less than a first threshold. The second die is configured to delay the transmission of the data signal of the second target path among the received multiple data signals according to the reception delay parameter determined in the data transmission training, so that the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than a second threshold, wherein the data signal of the second target path is the data signal of other paths among the multiple data signals besides the data signal of the first target path.

2. The transmitting device according to claim 1, characterized in that, The first physical layer circuit interface module also includes: At least one data transmission submodule, each of the at least one data transmission submodules being configured to transmit one data signal to the second die upon triggering of a first clock signal; The transmission delay submodule includes a first transmission delay unit. One end of the first transmission delay unit is coupled to the signal source of the first clock signal, and the other end is coupled to the clock input terminal of the at least one data transmission submodule. It is configured to delay the first clock signal according to the transmission delay parameters.

3. The transmitting device according to claim 2, characterized in that, The first physical layer circuit interface module also includes: The accompanying clock transmission submodule is configured to transmit a second clock signal to the second chip when the data transmission submodule transmits the data signal to the second chip, so that the second chip receives the data signal according to the second clock signal, wherein the second clock signal has the same frequency and a different phase from the first clock signal; The transmission delay submodule further includes a second transmission delay unit. One end of the second transmission delay unit is coupled to the signal source of the second clock signal, and the other end is coupled to the accompanying clock transmission submodule. It is configured to delay the second clock signal according to the transmission delay parameters.

4. The transmitting device according to claim 3, characterized in that, The delay durations of the first transmission delay unit and the second transmission delay unit are equal.

5. The transmitting device according to claim 3, characterized in that, The first physical layer circuit interface module also includes a phase-locked loop, the input of which is used to be coupled to a preset clock source; The first output terminal of the phase-locked loop serves as the signal source of the first clock signal and is coupled to the first transmission delay unit; The second output terminal of the phase-locked loop is connected in series with a preset phase adjustment element to serve as the signal source of the second clock signal and is coupled to the second transmission delay unit.

6. The transmitting device according to claim 5, characterized in that, The transmission delay submodule is used to compensate for the difference in physical trace delay when the signal is transmitted from the preset clock source to the input terminal of the phase-locked loop in each of the first physical layer circuit interface modules, and / or to compensate for the difference in substrate trace delay when the signal is transmitted from the output terminal of the accompanying clock transmission submodule of each of the first physical layer circuit interface modules to the input terminal of the second die.

7. The transmitting device according to claim 1, characterized in that, Each of the first physical layer circuit interface modules is configured to send multiple preset data signals to the second die during data transmission training, wherein each preset data signal is identical to the others. The transmission delay submodule is further configured to adjust the transmission delay of the multiple data signals during data transmission training to determine the transmission delay parameter, wherein the transmission delay parameter is the delay duration corresponding to the transmission delay submodule when the absolute value of the difference between the arrival times of the preset data signals of the first target paths of each first physical layer circuit interface module to the second die is less than a first threshold.

8. A receiving device, characterized in that, Located in the second grain; The receiving device includes multiple second physical layer circuit interface modules, wherein each second physical layer circuit interface module is configured to receive multiple data signals transmitted by the first die; Each of the second physical layer circuit interface modules includes a receive delay submodule, which is configured to delay the transmission of the data signal of the second target path among the multiple data signals received by the second physical layer circuit interface module according to the receive delay parameters determined in the data transmission training, so that the absolute value of the phase difference between the data signal of the second target path and the data signal of the first target path after the delay is less than a second threshold. Wherein, the data signal of each first target path is a data signal whose absolute value of the time difference between arriving at the corresponding second physical layer circuit interface module is less than a first threshold; the data signal of the second target path is the data signal of the other paths among the multiple data signals besides the data signal of the first target path.

9. The receiving device according to claim 8, characterized in that, The second physical layer circuit interface module also includes: The accompanying clock receiving submodule is configured to receive a second clock signal sent by the first chip, wherein the second clock signal has the same frequency but a different phase than the first clock signal used by the first chip to send the data signal. At least one data receiving submodule, each of the at least one data receiving submodules being configured to receive one of the data signals transmitted by the first die upon triggering by the second clock signal; At least one trigger, each trigger corresponding to one of the data receiving submodules; the data input terminal of each trigger is coupled to the output terminal of the corresponding data receiving submodule; the clock input terminal of each trigger is coupled to the output terminal of the accompanying clock receiving submodule. The receiving delay submodule is configured as follows: The transmission of the data signal of the second target path is delayed between the output terminal of the data receiving submodule and the data input terminal of the corresponding trigger. and / or The transmission of the second clock signal is delayed between the output of the accompanying clock receiving submodule and the clock input of the corresponding trigger.

10. The receiving device according to claim 9, characterized in that, The receiving delay submodule includes at least one receiving delay unit, and the at least one receiving delay unit corresponds one-to-one with the at least one data receiving submodule; Each of the receiving delay units is coupled between the output of the corresponding data receiving submodule and the data input of the corresponding flip-flop, and / or is coupled between the output of the accompanying clock receiving submodule and the clock input of the corresponding flip-flop.

11. The receiving device according to claim 9, characterized in that, Also includes: The data cache array module includes multiple cache chains, each of which includes a series of multi-level registers; the multiple cache chains correspond one-to-one with at least one flip-flop in each of the second physical layer circuit interface modules; the input of each cache chain is coupled to the data output of a corresponding flip-flop. The accompanying clock receiving submodule is further configured to generate a buffer enable signal in response to receiving the second clock signal; The data cache array module is configured to receive and cache the data signals output by each of the triggers according to the cache enable signal and the second clock signal.

12. The receiving device according to claim 11, characterized in that, Each of the second physical layer circuit interface modules is configured to receive multiple preset data signals sent by the first die during data transmission training, wherein each preset data signal is identical to the others. The receiving device further includes: The detection module, coupled to the data cache array module, is configured to compare the preset data signals stored in each of the cache chains during data transmission training, and determine whether the data transmission training has ended based on the comparison results.

13. The receiving device according to claim 12, characterized in that, The detection module is configured as follows: In data transmission training, every preset number of clock cycles of the second clock signal, the registers at the same level of each of the buffer chains are read once to obtain a set of detection data; wherein, when the multiple preset data signals are received triggered by a single edge of the second clock signal, the number of preset number of clock cycles is equal to the number of bits contained in each register, or, when the multiple preset data signals are received triggered by both edges of the second clock signal, the number of preset number of clock cycles is equal to half the number of bits contained in each register; In response to the fact that each set of detection data is the same as the other, it is determined that each preset data signal is aligned with the other, and the data transmission training ends. or, In response to the existence of at least two different detection data in at least one set of detection data, it is determined that the preset data signals are not aligned with each other, and data transmission training continues.

14. The receiving device according to claim 11, characterized in that, The accompanying clock receiving submodule is further configured to output a preset level signal in response to receiving the second clock signal, thereby obtaining a buffer control signal; The receiving device further includes a counting module coupled to the accompanying clock receiving submodule, configured to start counting the clock cycles of the second clock signal after receiving the buffer control signal, and output the buffer enable signal to the data buffer array module in response to counting N clock cycles, where N is a positive integer.

15. The receiving device according to claim 8, characterized in that, Each of the second physical layer circuit interface modules is configured to receive multiple preset data signals sent by the first die during data transmission training, wherein each preset data signal is identical to the others. The receiving delay submodule is further configured to adjust the transmission delay of the received preset data signal of the second target path during data transmission training to determine the receiving delay parameter. The receiving delay parameter is the delay duration corresponding to the receiving delay submodule when the absolute value of the phase difference between the preset data signal of the second target path and the preset data signal of the first target path after the delay is less than a second threshold.

16. A type of grain, characterized in that, The die includes the transmitting device according to any one of claims 1-7, and / or the receiving device according to any one of claims 8-15.

17. A chip, characterized in that, It includes at least two grains, the at least two grains including a first grain and a second grain coupled to each other, wherein the first grain is any of the grains described in claim 16, and the second grain is any of the grains described in claim 16.

18. A communication system, characterized in that, Includes a transmitting device and a receiving device; The transmitting device is used to send information to the receiving device; The receiving device is used to receive information sent by the sending device; Wherein, the transmitting device is the transmitting device according to any one of claims 1-7, and the receiving device is the receiving device according to any one of claims 8-15.

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