Enhanced output failure sat elastic logic lock module, module variants, and applications

Abstract

The application discloses an SAT elastic logic locking module with improved output damage, a module variant and application, relates to the technical field of hardware security, and the SAT elastic logic locking module comprises an n-bit traveling wave carry adder, a controllable output damage unit and a first AND gate; the module variant of the SAT elastic logic locking module is provided with a comparator and a second AND gate on the basis of the SAT elastic logic locking module; the SAT elastic logic locking module or the module variant is integrated with an SFLL or an SARLock to form an integrated circuit, and can be applied in resisting deletion attacks, sensitization attacks, functional analysis attacks and AppSAT attacks. The application realizes effective resistance to SAT attacks, and provides a new technical inspiration for the development of SAT attack resistance technology.

Description

Technical Field

[0001] This invention relates to the field of hardware security technology, and more specifically, to a SAT resilient logic locking module, module variants, and applications for improving output damage mitigation. Background Technology

[0002] Integrated circuits (ICs) are the backbone of modern computing systems. Logic locking is a technique designed to protect outsourced IC designs from piracy and counterfeiting by untrusted foundries in the field of hardware security. The locked IC can only unlock the correct design function if and only if the correct key is provided. In the last decade, the security of logic locking has been threatened by an attack called Boolean satisfiability (SAT). For locking designs with a considerable number of key bits, this attack can decrypt the correct key for most logic locking schemes in just a few hours. The AppSAT attack (a variant of the SAT attack) simplifies a composite scheme into a simple low-output corruptible locking scheme by unlocking a high-output corruptible locking scheme within the composite scheme. The attacker believes that the scheme itself is a highly approximation of the original circuit. Therefore, it is necessary to design a SAT-resilient logic locking module with improved output corruption to ensure circuit security.

[0003] Logic locking modifies the design circuit to be protected by locking the original design using key input bits; the resulting protected design circuit is called a locked design. The locked design is functionally equivalent to the original design only when the correct key is applied to the key input. The correct key is stored in a secure, tamper-proof memory after manufacturing, the contents of which cannot be accessed or tampered with outside the chip. The locking process is conducted in a trusted design lab. After the locked design has passed through the manufacturing and testing phases at an untrusted foundry, it is returned to the designer or remotely controlled via a secure key exchange protocol to load the correct key, thereby activating the circuit. Without the correct key, attackers cannot obtain the original design; therefore, logic locking effectively prevents attackers from reverse engineering or overproducing circuit designs, thus protecting intellectual property (IP) security.

[0004] The SAT attack model consists of a locked gate-level netlist and an activation chip. The former can be obtained by reverse engineering the GDSII layout file from an untrusted foundry or by reverse engineering the manufacturing chip from an untrusted end user, while the latter can be purchased from the open market. The SAT attack reveals the correct key by iteratively eliminating all erroneous keys. It uses a carefully selected set of principal inputs and their correct outputs to identify and eliminate erroneous keys; the correct outputs are observed from the activation chip. These special input / output pairs are called Distinguishing Input / Output (DIO) pairs. Each DIO can identify a subset of all erroneous keys in the set; erroneous key elements may be repeated between any two subsets, but each subset must be distinct. When no more DIOs are found, it means all erroneous keys have been identified, and the SAT attack can solve for the correct key. To date, the SAT attack remains a very powerful attack technique, capable of breaking not only locking technologies such as RLL, LUT, SLL, and FLL, but its variant, AppSAT, can also effectively crack defense mechanisms such as SARLock, Anti-SAT, ATD, and TTLock. Existing technologies still struggle to effectively resist SAT attacks. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to provide a SAT resilience logic locking technique that improves output failure resilience, thereby maintaining SAT resilience even in the event of increased output failure.

[0006] To achieve the aforementioned technical objectives, a first aspect of the exemplary embodiments of this disclosure provides a SAT resilience logic locking module for improving output corruption, comprising: An n-bit ripple carry adder is used to subtract the key input K from the main input X. A controllable output damage unit is used to receive the subtraction output result, and to perform conditional constraints through controllable output damage m in order to generate a controllable output damage signal; The first AND gate is used to combine the output damaged signal with the carry-out of the highest bit of the n-bit ripple carry adder to form an overlapped logic output signal.

[0007] Preferably, the input terminal of the n-bit ripple carry adder includes the least significant carry input.

[0008] Preferably, the controllable output corruption unit is used to adjust the output corruption by controlling the size of m to ensure the number of errors under each key, wherein m is selected as a power of 2.

[0009] Preferably, the SAT elastic logic locking module is used to resist deletion attacks, sensitization attacks, functional analysis attacks, and AppSAT attacks.

[0010] Based on the same inventive concept, a second aspect of the exemplary embodiments of this disclosure provides a module variant of the SAT resilient logic locking module mentioned in the first aspect, which, based on the structure of the SAT resilient logic locking module, further includes: A comparator, connected to a first AND gate and a second AND gate, is used to control an n-bit ripple carry adder to the low g-bit key input, constrained to a Hamming distance of 0, by taking the high h-bit key input and the main input X, to construct an overlapping output corrupted signal.

[0011] Based on the same inventive concept, a third aspect of the exemplary embodiments of this disclosure provides an integrated circuit that is constructed by integrating a SAT flexible logic locking module and an SFLL as mentioned in the first aspect.

[0012] Based on the same inventive concept, the fourth aspect of the exemplary embodiments of this disclosure provides an integrated circuit that is integrated with SFLL via a module variant as mentioned in the second aspect.

[0013] Based on the same inventive concept, the fifth aspect of the exemplary embodiments of this disclosure provides an integrated circuit that is configured by integrating the SAT elastic logic locking module with SARLock as mentioned in the first aspect.

[0014] Based on the same inventive concept, a sixth aspect of the exemplary embodiments of this disclosure provides an integrated circuit that is integrated with SARLock via a module variant as mentioned in the second aspect.

[0015] Based on the same inventive concept, the seventh aspect of the exemplary embodiments of this disclosure provides an application of an integrated circuit, namely, the application of an integrated circuit provided by any one of the third, fourth, fifth, and sixth aspects in resisting deletion attacks, sensitization attacks, functional analysis attacks, and AppSAT attacks.

[0016] The present invention discloses the following technical effects: 1. Overlapping logic (OL) allows for flexible output corruption while maintaining SAT resilience. The implementation of OL introduces a ripple carry adder, which is structurally adjusted to meet design requirements, and this is mathematically proven.

[0017] 2. Block Overlapping Logic (COL), as a variant of OL, uses comparators to replace part of the adder structure to construct block overlapping output corruption, which can effectively reduce the hardware overhead caused by the implementation complexity of OL.

[0018] 3. Integrating OL and COL into SARLock and SFLL demonstrates good compatibility and SAT resilience. Furthermore, the damage characteristics of OL / COL help defenders resist deletion attacks, functional analysis attacks, and other attacks from a new perspective.

[0019] 4. Low hardware overhead. Compared with existing new locking solutions such as Anti-SAT, SFLL-HD, SKG-Lock and SKG-Lock+, the proposed OL / COL integrated solution incurs less hardware overhead. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the overlapping logic (OL) structure.

[0022] Figure 2 This is a schematic diagram of the structure of Block Overlapping Logic (COL).

[0023] Figure 3 Here is a Karnaugh map of overlapped logic (OL), where (a)m=2, (b)m=4, and (c)m=8.

[0024] Figure 4 Here is a Karnaugh map of the Block Overlapping Logic (COL), where (a) m=2, g=3, (b) m=2, g=2, and (c) m=4, g=3.

[0025] Figure 5 This is a schematic diagram of the proposed OL / COL integration scheme, where (a) is integrated with SARLock and (b) is integrated with SFLL. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] like Figures 1-5 As shown, this invention provides a SAT resilient logic locking technology to improve output corruption, mainly including two aspects of design: overlapped logic (OL) and block overlapped logic (COL), specifically including the following: like Figure 1 As shown, the overlapped logic (OL) of this invention first uses an n-bit ripple carry adder to subtract the key input K and the primary input X (primary input X refers to the functional input; in scan-based testability design, inputs are divided into primary input and pseudo-primary input. Pseudo-primary input corresponds to flip-flops, while primary input is the original input of the circuit, i.e., the "primary input X" mentioned in this invention is the functional input) from each other. Here, Cin is the least significant carry input, Sub_result is the subtraction output, Cout is the most significant carry output, and m represents controllable output corruption. In combinational logic, subtraction can be implemented through addition, i.e., KX = K + ~X + 1, where ~X is the inverse of X obtained by bitwise inversion. Then, conditional constraints are applied to Sub_result to achieve controllable output corruption, i.e., determining whether Sub_result is less than m. Finally, the output corruption signal, along with Cout, is passed through an AND gate to form the overlapped logic output signal. It is worth noting that an important premise for the proposed logic to implement KX is that K≥X. The existence of Cout can satisfy this premise with minimal overhead. The proof is as follows: Proof: To prove that Cout can determine K≥X, it suffices to prove that Cout is always 1 when K≥X, and 0 when K<X. For ease of understanding, assume K and X are 4-bit wide signals. When K≥X, ~X≥~K, K+~X≥K+~K=1111, then KX=K+~X+1≥10000, and the highest bit Cout is 1. When K<X, ~X<~K, K+~X<K+~K=1111, then KX=K+~X+1≤01111, and the highest bit Cout is 0. The conclusion is thus proven. OL simplifies the numerical comparator in the subtraction process into an AND gate, minimizing additional overhead.

[0029] The overlap logic (OL) of this invention adjusts output corruption by controlling the size of m to ensure the error count under each key. For ease of implementation, this invention always chooses m as a power of 2. It is worth mentioning that as the value of m increases, the complexity of implementing Sub_result < m will decrease. For example, assuming the bit width of Sub_result is 4, output corruption setting m=2 can be achieved by checking if Sub_result[3:1]=000, and output corruption setting m=4 can be achieved by checking if Sub_result[3:2]=00. The latter theoretically reduces the implementation complexity of Sub_result < m, which will manifest as reduced overhead in hardware implementation.

[0030] Analyzing the security of OL against SAT attacks, where Karnaugh maps of OL under different m(2, 4, 8) settings are shown below. Figure 3 As shown. Assume the SAT attack follows a sequential iteration (from X0 to...). Each primary input pattern can exclude m keys, where m-1 of the m keys identified by the DIP in the i-th iteration overlap with those in the (i+1)-th iteration. In this case, a SAT attack requires 2n-(m-1) DIPs to achieve the ideal number of iterations. Where Nop represents the number of DIPs searched in each iteration. Since actual SAT attacks do not follow a sequential iterative process, this invention assumes that the SAT attack eliminates m non-overlapping keys in each iteration, thus obtaining the minimum number of iterations, i.e. Based on the two assumptions above, it can be inferred that the security of OL is between... and between.

[0031] The structural diagram of the block overlap logic (COL) of the present invention is shown below. Figure 2 As shown, the Karnaugh maps of COL under different m and g settings are as follows: Figure 4 As shown. Considering both the sequential and non-sequential iterations of the SAT attack, the ideal number of iterations is obtained, i.e. and the minimum number of iterations, i.e. It is not difficult to see that OL can be regarded as an instance of COL when h=0, and the security of COL is also between... and between.

[0032] The block overlapped logic (COL) of this invention is constructed from comparators and adders. The comparators constrain the high h-bit key input and the main input to a Hamming distance of 0 (i.e., K[n-1:g] = X[n-1:g]). The adders are included in the OL that constructs an overlapped output corruption for the low g-bit input, where h + g = n. Analyzing the Karnaugh maps of the OL and COL, this invention summarizes two characteristics of the proposed logic, as described below.

[0033] (1) Continuous corruption characteristic: Under any set of key inputs, OL and COL will produce output corruption corresponding to m consecutive primary input patterns. Figure 3 (b) For example, m=4. Let the key input be K7, which corresponds to the output corruption of the four main input modes X4, X5, X6, and X7.

[0034] (2) Block corruption characteristic: When COL satisfies the condition K[n-1:g]=X[n-1:g], the data distribution of the Karnaugh map sub-blocks with overlapping output corruption constructed from the low g-bit inputs is the same. Figure 4 (c) For example, m=4, g=3. Let n=4. When K[3]=X[3]=0 / 1, the data distribution of the Karnaugh map sub-blocks with overlapping output corruption constructed from the lower 3 bits of input is the same, as shown in the two diagonally opposite sub-blocks. The above characteristics help defenders resist other attacks from new angles, such as deletion attacks, functional analysis attacks, etc.

[0035] The following details the integration solution built using OL and COL, such as... Figure 5 As shown.

[0036] (1) Integration with SATLock: This scheme replaces the equality comparator in SATLock with OL / COL, and then performs an AND operation on the outputs of the proposed logic and the mask logic to obtain the flip signal. The mask logic in traditional SATLock prevents output corruption by judging the correctness of the key input. Attackers can easily identify this "key-only logic", delete the logic structure, and build a new "key-only logic" to crack the correct function of the lock circuit.

[0037] This invention refers to the masking logic constructed solely from key inputs as vertical masking logic (V-Mask), and proposes a new masking logic constructed solely from the main inputs, referred to as horizontal masking logic (H-Mask). When the main inputs are certain patterns, H-Mask prevents output corruption. Since OL and COL exhibit sequential corruption characteristics, the number of input bits required for H-Mask to control decreases as m increases, while the number of input bits required for V-Mask to control is fixed at n. This makes H-Mask superior to V-Mask in terms of hardware overhead.

[0038] by Figure 3 (b) Taking m=4 as an example, assuming n=4 and the correct key is K7. H-Mask prevents output corruption when the main input patterns are X4, X5, X6, and X7 by controlling the two main inputs (x3, x2) = (0, 0); while V-Mask requires controlling the four key inputs (k3, k2, k1, k0) = (0, 1, 1, 1) to prevent output corruption. H-Mask has good applicability to both OL and COL, and the application of this logic will make attackers recognize it as part of the original design, thereby preventing deletion attacks.

[0039] (2) Integration with SFLL: This scheme constructs a function stripping circuit by damaging the output of input modes with a controllable number of damaged elements. This circuit is then XORed with the output of the proposed logic, which serves as a recovery unit, to obtain a locked output signal. The integrated scheme sets the output damage by controlling the value of m, where m is equivalent to h in SFLL-HD. However, unlike SFLL-HD, due to the continuous damage characteristic of the proposed logic, the function stripping unit in the integrated scheme can achieve stripping functionality by setting m consecutive main input modes as protected cubes. This design simplification manifests as a reduction in hardware overhead. Furthermore, due to the block damage characteristic of COL, the number of protected cubes in COL-SFLL remains variable when m is a fixed value.

[0040] by Figure 4 (c) For example, m=4, g=3. In the Karnaugh map sub-blocks with overlapping output corruption constructed from the low g-bit inputs, the corruption number in some key input modes always increases from 1 to m. When K0, K1, K2, and K3 are set as the correct keys, the number of protected cubes in COL-SFLL are 1, 2, 3, and 4, respectively. The number of such sub-blocks is 2n-g, which is exponential. Therefore, the defender can flexibly adjust the number of protected cubes with a fixed value for m by setting this special key input mode as the correct key, making it impossible for the attacker to launch a functional analysis attack on the integration scheme by determining the value of m.

[0041] Based on the detailed description of OL, COL and their integration scheme above, the proposed logic utilizes the m-1 overlapping error keys present in adjacent input modes to make it possible for the proposed OL / COL integration scheme to achieve the ideal number of iterations (i.e. This significantly weakens the trade-off between output corruption and SAT resilience. As the number of latching bits increases, the number of iterations required for the unlocking circuit exceeds the typical minimum number of iterations (i.e., The number of iterations increases exponentially, and the execution time follows the same growth pattern. When n=14 and m=2, the average number of iterations and average iteration time of the proposed OL / COL integration scheme range from 6275 to 9877 and 4720.72s to 8857.25s, respectively; when n=128, the required number of iterations and iteration time are almost immeasurable. Therefore, the proposed scheme is safe against SAT attacks (i.e., it achieves SAT resilience). Furthermore, since the proposed logic has a controllable high level of output corruption, the proposed scheme is also safe against AppSAT attacks.

[0042] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0043] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0044] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A SAT elastic logic lockout module for improving output damage, applied in a lockout circuit, characterized in that, include: An n-bit ripple carry adder is used to perform two's complement subtraction on key input K and main input X, where main input X represents the function input; A controllable output corruption unit is used to receive the output result of the two's complement subtraction. It uses controllable output corruption m to perform conditional constraints in order to generate a controllable output corruption signal, where m is a power of 2 and m≥2. The first AND gate is used to combine the output damaged signal with the highest bit carry output of the n-bit ripple carry adder to form an overlapped logic output signal.

2. The SAT resilient logic locking module for improving output failure as described in claim 1, characterized in that: The input of the n-bit ripple carry adder includes the least significant carry input.

3. The SAT resilient logic locking module for improving output failure as described in claim 2, characterized in that: The controllable output corruption unit is used to adjust the output corruption by controlling the size of m to ensure the number of errors under each key.

4. A module variant of the SAT resilient logic locking module for improving output failure as described in claim 1, characterized in that, Also includes: A comparator, connected to the first AND gate and then to the second AND gate, is used to control an n-bit ripple carry adder to input the low g-bit key, constraining the high h-bit key input and the main input X to a Hamming distance of 0, in order to construct an overlapping output corrupted signal.

5. An integrated circuit, characterized in that, It is constructed by integrating the SAT elastic logic locking module as described in claim 1 with SFLL.

6. An integrated circuit, characterized in that, It is constructed by integrating the module variant as described in claim 4 with SFLL.

7. An integrated circuit, characterized in that, It is constructed by integrating the SAT elastic logic locking module as described in claim 1 with SARLock.

8. An integrated circuit, characterized in that, It is constructed by integrating SARLock with the module variant as described in claim 4.

9. An application of an integrated circuit, characterized in that, The application of the integrated circuit as described in any one of claims 5-8 in resisting deletion attacks, sensitization attacks, functional analysis attacks, and AppSAT attacks.

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