Display panel and display device

Abstract

The application provides a display panel and a display device. The re-bonding connection is prepared by separating the light-emitting carrier plate provided with a sub-pixel from the silicon-based driving substrate, so that the sub-pixel does not need to be directly prepared on the silicon-based driving substrate, the influence of the evaporation process on the silicon-based driving substrate can be reduced, and then the loss caused by subsequent process errors can be reduced, and the manufacturing cost of the silicon-based driving substrate is reduced. The cathode layers of the sub-pixels are electrically connected to each other through the isolation structure, so that the whole cathode can be formed between the conductive part and the cathode layer; the conductive part is electrically connected to the silicon-based driving substrate, which can not only reduce the connection resistance between the cathode layers of the sub-pixels, thereby reducing the resistance of the whole cathode to improve the problem of voltage drop; and at least part of the cathode layers can be electrically connected to the silicon-based driving substrate through the conductive part, so as to reduce the transmission path of the cathode signal and further improve the problem of voltage drop, which is beneficial to improving the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Compared to traditional AMOLED (Active-matrix organic light-emitting diode) display technology, silicon-based OLED (Organic Light Emitting Display) microdisplays use single-crystal silicon chips as a substrate and leverage mature CMOS (Complementary Metal Oxide Semiconductor) technology to achieve smaller pixel sizes and higher integration, making them suitable for near-eye display products comparable to large-screen displays and thus attracting widespread attention.

[0003] However, the process of vaporizing sub-pixels can easily affect the silicon-based driving circuit layer. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a display panel and display device that solves the problem in the prior art where the process of vapor deposition of sub-pixels can easily affect the silicon-based driving circuit layer.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a display panel, comprising:

[0006] Silicon-based driving substrate;

[0007] The light-emitting carrier is bonded to the silicon-based driving substrate; the light-emitting carrier includes:

[0008] Glass substrate with cathode via;

[0009] A pixel definition layer is disposed on the side of the glass substrate away from the silicon-based driving substrate; the pixel definition layer has pixel openings and connection vias;

[0010] A sub-pixel is located at a pixel opening; a sub-pixel includes an anode layer, a light-emitting layer, and a cathode layer stacked sequentially.

[0011] An isolation structure protrudes from the pixel definition layer and is located on the side of the sub-pixel; the isolation structure includes a conductive part and a top structure stacked sequentially; the cathode layer overlaps with the conductive part to achieve mutual electrical connection between the cathode layers;

[0012] In this structure, at least a portion of the conductive parts of the isolation structure are electrically connected to the silicon-based driving substrate by means of connecting vias and cathode vias.

[0013] Each isolation structure corresponds to at least one connection through hole.

[0014] In this case, multiple isolation structures share the same connecting via.

[0015] The multiple isolation structures partially overlap each other and have a common overlapping area; the connecting through holes are located in the overlapping area.

[0016] In the direction parallel to the glass substrate, the sub-pixels are rectangular;

[0017] The connecting through hole is located on the side of the rectangle;

[0018] or,

[0019] The connecting through hole is located in the corner area of ​​the rectangle;

[0020] or,

[0021] One part of the connecting through hole is located on the side of the rectangle, and the other part of the connecting through hole is located in the corner area of ​​another rectangle.

[0022] The silicon-based driving substrate includes a silicon substrate and a driving circuit layer; the driving circuit layer is disposed on the side of the silicon substrate close to the light-emitting carrier.

[0023] The glass substrate also has an anode via spaced apart from the cathode via, and the anode layer is electrically connected to the silicon-based drive substrate through the anode via.

[0024] The anode through-holes are set one-to-one with the anode layer and are located close to the cathode through-holes.

[0025] in,

[0026] The light-emitting substrate also includes extended electrodes, which are located on the side of the glass substrate away from the isolation structure; the extended electrodes include an anode extended electrode and a cathode extended electrode;

[0027] The conductive part is electrically connected to the cathode extension electrode through the connecting through hole and the cathode through hole in sequence, and the cathode extension electrode is bonded to the cathode driving electrode of the silicon-based driving substrate.

[0028] The anode layer is electrically connected to the anode extension electrode through an anode via, and the anode extension electrode is bonded to the anode drive electrode of the silicon-based drive substrate.

[0029] In this structure, a conductive portion extends from the top structure in a direction parallel to the glass substrate; the orthographic projection of the conductive portion on the glass substrate covers the orthographic projection of the connecting through-hole on the glass substrate.

[0030] To solve the above-mentioned technical problems, the second technical solution provided in this application is: to provide a display device, which includes a motherboard and the above-mentioned display panel.

[0031] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a display panel and a display device. The display panel includes a silicon-based driving substrate and a light-emitting carrier. The light-emitting carrier is bonded to the silicon-based driving substrate. The light-emitting carrier includes a glass substrate, a pixel definition layer, sub-pixels, and an isolation structure. The glass substrate has cathode vias. The pixel definition layer is disposed on the side of the glass substrate away from the silicon-based driving substrate. The pixel definition layer has pixel openings and connection vias. Sub-pixels are disposed in the pixel openings. Each sub-pixel includes an anode layer, a light-emitting layer, and a cathode layer stacked sequentially. The isolation structure protrudes from the pixel definition layer and is disposed on the side of the sub-pixel. The isolation structure includes conductive portions and a top structure stacked sequentially. The cathode layer overlaps with the conductive portions to achieve mutual electrical connection between the cathode layers. At least a portion of the conductive portions of the isolation structure are electrically connected to the silicon-based driving substrate via connection vias and cathode vias. By separately fabricating and bonding the light-emitting substrate with sub-pixels to the silicon-based driving substrate, the sub-pixels do not need to be directly fabricated on the silicon-based driving substrate. This reduces the impact on the driving circuit layer in the silicon-based driving substrate during the sub-pixel deposition process, thereby reducing losses caused by subsequent process errors and lowering the manufacturing cost of the silicon-based driving substrate. By setting an isolation structure to electrically connect the cathode layers of the sub-pixels, a full-surface cathode can be formed between the conductive part and the cathode layer. Electrically connecting the conductive part to the silicon-based driving substrate not only increases the thickness of the conductive part to reduce the connection resistance between the cathode layers of the sub-pixels, thereby reducing the resistance of the full-surface cathode and improving the voltage drop problem, but also allows at least a portion of the cathode layer to be electrically connected to the silicon-based driving substrate through the conductive part, reducing the transmission path of the cathode signal and further improving the voltage drop problem, which is beneficial to improving the display effect of the display panel. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application;

[0034] Figure 2 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the first embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the second embodiment provided in this application;

[0036] Figure 4 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the third embodiment provided in this application;

[0037] Figure 5 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the fourth embodiment provided in this application;

[0038] Figure 6 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the fifth embodiment provided in this application;

[0039] Figure 7 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the sixth embodiment provided in this application;

[0040] Figure 8 This is a schematic diagram of an embodiment of the display device provided in this application.

[0041] Explanation of icon numbers:

[0042] 100. Display panel; 10. Light-emitting substrate; 11. Glass substrate; 111. Cathode via; 112. Anode via; 12. Pixel definition layer; 121. Pixel opening; 122. Connecting via; 13. Subpixel; 131. Anode layer; 132. Light-emitting layer; 133. Cathode layer; 14. Isolation structure; 141. Conductive part; 142. Top structure; 142A. Support structure; 142B. Eaves structure; 15. Extended electrode; 151. Cathode extended electrode; 152. Anode extended electrode; 16. Encapsulation layer; 161. First encapsulation layer; 162. Second encapsulation layer; 20. Silicon-based driving substrate; 21. Silicon substrate; 22. Driving circuit layer; 221. Cathode driving electrode; 222. Anode driving electrode; 200. Main board; 300. Display device. Detailed Implementation

[0043] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0044] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application.

[0049] This application provides a display panel 100. The display panel 100 includes a silicon-based driving substrate 20 and a light-emitting carrier 10. The light-emitting carrier 10 is bonded to the silicon-based driving substrate 20. The light-emitting carrier 10 includes a glass substrate 11, a pixel definition layer 12, sub-pixels 13, and an isolation structure 14. The glass substrate 11 has a cathode via 111. The pixel definition layer 12 is disposed on the side of the glass substrate 11 away from the silicon-based driving substrate 20. The pixel definition layer 12 has a pixel opening 121 and a connection via 122. The sub-pixel 13 is disposed in the pixel opening 121. The sub-pixel 13 includes an anode layer 131, a light-emitting layer 132, and a cathode layer 133 stacked sequentially. The isolation structure 14 protrudes from the pixel definition layer 12 and is disposed on the side of the sub-pixel 13. The isolation structure 14 includes a conductive portion 141 and a top structure 142 stacked sequentially. The cathode layer 133 overlaps with the conductive portion 141 to achieve mutual electrical connection between the cathode layers 133. In this embodiment, at least a portion of the conductive portion 141 of the isolation structure 14 is electrically connected to the silicon-based driving substrate 20 via a connecting via 122 and a cathode via 111.

[0050] By separately fabricating and bonding the light-emitting substrate 10 with sub-pixels 13 to the silicon-based driving substrate 20, the sub-pixels 13 do not need to be directly fabricated on the silicon-based driving substrate 20. This reduces the impact on the driving circuit layer 22 in the silicon-based driving substrate 20 during the deposition of the sub-pixels 13, thereby reducing losses caused by subsequent process errors and lowering the manufacturing cost of the silicon-based driving substrate 20. By providing an isolation structure 14 to electrically connect the cathode layers 133 of the sub-pixels 13, a full-surface cathode can be formed between the conductive portion 141 and the cathode layers 133. Electrically connecting the conductive portion 141 to the silicon-based driving substrate 20 not only increases the thickness of the conductive portion 141 to reduce the connection resistance between the cathode layers 133 of the sub-pixels 13, thereby reducing the resistance of the full-surface cathode and improving the voltage drop problem, but also allows at least a portion of the cathode layers 133 to be electrically connected to the silicon-based driving substrate 20 through the conductive portion 141, reducing the transmission path of the cathode signal and further improving the voltage drop problem, which is beneficial to improving the display effect of the display panel 100.

[0051] The silicon-based driving substrate 20 includes a silicon substrate 21 and a driving circuit layer 22, with the driving circuit layer 22 disposed on the side of the silicon substrate 21 near the light-emitting carrier 10. The silicon substrate 21 refers to a substrate based on monocrystalline silicon material. The driving circuit layer 22 includes active driving circuits (not shown) integrated on the silicon substrate 21 using CMOS technology.

[0052] The separate fabrication of the silicon-based driving substrate 20 and the light-emitting carrier 10 can improve production efficiency. Secondly, it can avoid the impact of the vapor deposition process on the silicon-based driving substrate 20, reducing losses. In other words, from a process perspective, separate fabrication of the silicon-based driving substrate 20 and the light-emitting carrier 10 can not only improve yield but also reduce costs.

[0053] The glass substrate 11 also has an anode via 112 spaced apart from the cathode via 111, through which the anode layer 131 is electrically connected to the silicon-based driving substrate 20. Both the cathode via 111 and the anode via 112 are fabricated using through-glass via (TGV) technology.

[0054] It should be understood that, compared with through-silicon via (TSV) technology, glass via technology has the advantages of superior high-frequency electrical characteristics, low cost, simple process flow, and strong mechanical stability.

[0055] Compared to the prior art where the sub-pixel 13 is fabricated on the silicon-based driving substrate 20 and electrically connected to the silicon-based driving substrate 20 through silicon vias, this application sets the sub-pixel 13 on the glass substrate 11 and bonds the sub-pixel 13 to the silicon-based driving substrate 20 through glass vias, which can reduce costs and improve high-frequency electrical characteristics.

[0056] The anode through-holes 112 are arranged one-to-one with the anode layer 131 and are located close to the cathode through-holes 111, so that the anode through-holes 112 are located as close as possible to the isolation structure 14 and away from the pixel opening 121, which is beneficial to the planarization of the anode layer 131.

[0057] The material of the pixel definition layer 12 is not limited here and can be selected according to actual needs. In the direction parallel to the pixel definition layer 12, the connecting via 122 is spaced apart from the anode layer 131. In the direction perpendicular to the pixel definition layer 12, the connecting via 122 penetrates the pixel definition layer 12.

[0058] The conductive material inside the connecting through-hole 122 can be the same as or different from the material of the conductive part 141. There is no restriction on the conductive material inside the connecting through-hole 122; it can be selected according to actual needs. It should be understood that the connecting through-hole 122 is a metallized hole used to connect the conductive part 141 to the corresponding cathode through-hole 111.

[0059] In this embodiment, the conductive material inside the connecting through hole 122 is different from the material of the conductive part 141.

[0060] The isolation structure 14 is used to isolate sub-pixels 13 of different colors to prevent optical crosstalk between sub-pixels 13 of different colors. Compared with the existing technology that uses FMM (Fine Metal Mask) process to prepare sub-pixels 13, this embodiment uses the isolation structure 14 to isolate sub-pixels 13, eliminating the need for a fine metal mask and reducing costs.

[0061] In this embodiment, the isolation structure 14 is located between sub-pixels 13 of different colors, and also between sub-pixels 13 of the same color.

[0062] It should be noted that the display panel 100 in this application includes a display area (not shown) and a border area (not shown), and the sub-pixel 13 and the isolation structure 14 are both located in the display area.

[0063] In a direction parallel to the glass substrate 11, the top structure 142 extends out a conductive portion 141. Specifically, the orthographic projection of the top structure 142 on the pixel definition layer 12 covers the orthographic projection of the conductive portion 141 on the pixel definition layer 12, and the area of ​​the orthographic projection of the top structure 142 on the pixel definition layer 12 is larger than the area of ​​the orthographic projection of the conductive portion 141 on the pixel definition layer 12.

[0064] The orthographic projection of the top structure 142 on the glass substrate 11 covers the orthographic projection of the cathode via 111 on the glass substrate 11, thus preventing the cathode via 111 from occupying the position of the anode layer 131.

[0065] The top structure 142 of the isolation structure 14 includes a support structure 142A and an eaves structure 142B. The support structure 142A is disposed on the upper surface of the conductive portion 141 and supports the eaves structure 142B. The edge of the eaves structure 142B extending beyond the conductive portion 141 is used to adjust the evaporation angle of the sub-pixel 13 so that the cathode layer 133 of the sub-pixel 13 covers the light-emitting layer 132 of the sub-pixel 13 and can achieve good overlap with the conductive portion 141.

[0066] In a direction parallel to the pixel definition layer 12, the eaves structure 142B extends out of the upper surface of the support structure 142A. The support structure 142A reduces the thickness of the portion of the conductive part 141 that protrudes from the pixel definition layer 12, preventing the opaque conductive part 141 from blocking the lateral light emitted by the sub-pixel 13 and reducing the light utilization rate of the sub-pixel 13; it also facilitates the upward movement of the cathode layer 133 to achieve a good connection with the conductive part 141.

[0067] It should be understood that the cathode layer 133 is disposed on the side of the conductive portion 141 away from the glass substrate 11. A portion of the cathode layer 133 overlaps with the upper surface of the conductive portion 141 to achieve electrical connection between the cathode layer 133 and the conductive portion 141.

[0068] The conductive portion 141 protrudes from the upper surface of the pixel definition layer 12. The conductive portion 141 of the isolation structure 14 overlaps with the cathode layer 133 to electrically connect the cathode layers 133 of the sub-pixels 13 to form a full-surface cathode.

[0069] The conductive part 141 covers the connecting through hole 122 to prevent the connecting through hole 122 from occupying too much space between the sub-pixels 13 and causing a short circuit with the anode layer 131.

[0070] At least a portion of the conductive portion 141 of the isolation structure 14 is electrically connected to the silicon-based driving substrate 20 via a connecting via 122 and a cathode via 111. This can be understood as follows: a connecting via 122 is provided directly below the conductive portion 141 of some isolation structures 14; a connecting via 122 is not provided directly below the conductive portion 141 of some isolation structures 14; or, connecting via 122 is provided directly below the conductive portion 141 of all isolation structures 14. The conductive portion 141 of the isolation structure 14 is in contact with the connecting via 122 directly below it to achieve electrical connection.

[0071] In some embodiments, a single isolation structure 14 is provided corresponding to at least one connection via 122. That is, in an isolation structure 14 electrically connected to the silicon-based driving substrate 20 through a connection via 122, the conductive portion 141 of one isolation structure 14 covers at least one connection via 122. It can be understood that an isolation structure 14 is electrically connected to the silicon-based driving substrate 20 through one or more connection vias 122. The more connection vias 122 there are, the smaller the connection resistance between the cathode layers 133 of the sub-pixels 13, and the better the effect of improving voltage drop.

[0072] In other embodiments, multiple isolation structures 14 share the same connecting via 122. That is, in the isolation structures 14 electrically connected to the silicon-based driving substrate 20 via the connecting via 122, the conductive portions 141 of multiple isolation structures 14 simultaneously cover a single connecting via 122. By having multiple isolation structures 14 share the same connecting via 122, the aperture of the connecting via 122 can be appropriately increased, simplifying the fabrication of the connecting via 122 and improving product yield. Specifically, the multiple isolation structures 14 are partially overlapped and have a common overlapping area. The connecting via 122 is located in the overlapping area.

[0073] It should be understood that multiple isolation structures 14 share the same connecting via 122. The adjustable range of the aperture of the connecting via 122 is related to the arrangement of the sub-pixels 13 and the spacing between the sub-pixels 13.

[0074] Please see Figures 1 to 4 , Figure 2This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the first embodiment provided in this application. Figure 3 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the second embodiment provided in this application. Figure 4 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the third embodiment of this application.

[0075] In this embodiment, a single isolation structure 14 is provided to correspond to a single connection through hole 122.

[0076] In the direction parallel to the glass substrate 11, the cross-section of the connecting through hole 122 can be rectangular, circular, triangular or polygonal, etc. There is no restriction here, and it can be selected according to actual needs.

[0077] In this embodiment, the cross-section of the connecting through hole 122 is circular in the direction parallel to the glass substrate 11, which facilitates the fabrication of the connecting through hole 122.

[0078] In some embodiments, the aperture of the connecting via 122 is 5 micrometers to 15 micrometers. It should be understood that in other embodiments, the aperture of the connecting via 122 can be adjusted according to the spacing between the sub-pixels 13 and the arrangement of the sub-pixels 13, and can be adjusted to other values.

[0079] The display panel 100 in this embodiment includes sub-pixels 13 of various colors. Each sub-pixel 13 corresponds to a pixel opening 121. The sub-pixels 13 are OLEDs. The colors of the sub-pixels 13 are not limited here and can be selected according to actual needs.

[0080] In some embodiments, the size of subpixel 13 is 6 micrometers to 15 micrometers. It should be understood that the size of subpixel 13 can also be other values.

[0081] In some embodiments, the sub-pixel 13 is rectangular in a direction parallel to the glass substrate 11. The connecting via 122 is located on the side of the rectangle; or, the connecting via 122 is located in the corner region of the rectangle; or, a portion of the connecting via 122 is located on the side of the rectangle, and another portion of the connecting via 122 is located in the corner region of another rectangle.

[0082] In this embodiment, the connecting hole 122 is located on the long side of the rectangle and between two adjacent sub-pixels 13.

[0083] In one specific embodiment, the aperture of the connecting through hole 122 is 10 micrometers.

[0084] In other embodiments, the connecting through-hole 122 may be located on the short side of the rectangle, or the connecting through-hole 122 may be located on each side of the rectangle. An isolation structure 14 may correspond to two connecting through-holes 122, and the two connecting through-holes 122 are disposed on one side of the rectangle, and arranged side-by-side along the long or short side of the rectangle (see...). Figure 3 and Figure 4 ).

[0085] It should be understood that when one connecting through hole 122 corresponds to multiple connecting through holes 122, and the multiple connecting through holes 122 are located on the same side of the rectangle, the aperture of the connecting through hole 122 can be appropriately reduced in order to avoid sacrificing the area of ​​the sub-pixel 13 as much as possible.

[0086] The light-emitting carrier 10 also includes an extension electrode 15, which is located on the side of the glass substrate 11 away from the isolation structure 14. The extension electrode 15 includes an anode extension electrode 152 and a cathode extension electrode 151.

[0087] The conductive part 141 is electrically connected to the cathode extension electrode 151 through the connecting through hole 122 and the cathode through hole 111 in sequence. The cathode extension electrode 151 is bonded to the cathode driving electrode 221 of the silicon-based driving substrate 20.

[0088] The anode layer 131 is electrically connected to the anode extension electrode 152 through the anode through-hole 112, and the anode extension electrode 152 is bonded to the anode driving electrode 222 of the silicon-based driving substrate 20.

[0089] The driving circuit layer 22 has a cathode driving electrode 221 and an anode driving electrode 222. That is, the cathode extension electrode 151 is bonded to the cathode driving electrode 221 of the driving circuit layer 22. The anode extension electrode 152 is bonded to the anode driving electrode 222 of the driving circuit layer 22.

[0090] In other words, the extended electrode 15 on the light-emitting carrier 10 is bonded to the driving electrode (i.e., the anode driving electrode 222 and the cathode driving electrode 221) on the silicon-based driving substrate 20 to achieve the bonding connection between the light-emitting carrier 10 and the silicon-based driving substrate 20.

[0091] The driving circuit layer 22 provides a common voltage to the common cathode layer 133 through the cathode driving electrode 221, and provides an operating voltage to the anode layer 131 of the sub-pixel 13 through the anode driving electrode 222, so as to drive the sub-pixel 13 to emit light.

[0092] The light-emitting carrier 10 also includes an encapsulation layer 16, which is disposed on the side of the sub-pixel 13 away from the glass substrate 11 to encapsulate the sub-pixel 13. The structure and material of the encapsulation layer 16 are not limited here and can be selected according to actual needs. The surface of the encapsulation layer 16 away from the glass substrate 11 is planarized.

[0093] In this embodiment, the encapsulation layer 16 includes a first encapsulation layer 161 and a second encapsulation layer 162. The first encapsulation layer 161 encapsulates the sub-pixel 13 and the isolation structure 14, and the second encapsulation layer 162 is located on the side of the first encapsulation layer 161 away from the glass substrate 11. Specifically, the first encapsulation layer 161 is an organic material, and the second encapsulation layer 162 is an inorganic material.

[0094] Please see Figures 1 to 5 , Figure 5 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the fourth embodiment of this application.

[0095] The fourth embodiment of sub-pixel 13 and connecting via 122 provided in this application is basically similar in structure to the first embodiment of sub-pixel 13 and connecting via 122 provided in this application. The difference is that the connecting via 122 is located in the corner area of ​​a rectangle.

[0096] In this embodiment, the sub-pixel 13 is rectangular in the direction parallel to the glass substrate 11.

[0097] Subpixels 13 are arranged in a matrix. Multiple isolation structures 14 partially overlap each other and share a common overlapping area. Connecting vias 122 are located in the overlapping area. Specifically, as shown... Figure 5 As shown, the connecting via 122 is located in the overlapping area of ​​the four adjacent isolation structures 14 in a direction parallel to the glass substrate 11. That is, the four isolation structures 14 share the same connecting via 122.

[0098] In one specific embodiment, the aperture of the connecting through hole 122 is 15 micrometers.

[0099] Compared to the first embodiment of sub-pixels 13 and connecting vias 122 provided in this application, the design of the connecting vias 122 in this embodiment can reduce the spacing between sub-pixels 13, ensuring that the conductive portion 141 of the isolation structure 14 can be electrically connected to the silicon-based driving substrate 20 through the connecting vias 122 without sacrificing the area of ​​the sub-pixels 13. Furthermore, the increased aperture of the connecting vias 122 simplifies the fabrication of the connecting vias 122, thereby improving process yield and ultimately enhancing product reliability.

[0100] Please see Figures 1 to 7 , Figure 6 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the fifth embodiment provided in this application. Figure 7 This is a schematic diagram of the arrangement structure of the sub-pixels and connecting vias in the sixth embodiment of this application.

[0101] The fifth embodiment of sub-pixel 13 and connecting via 122 provided in this application is basically similar in structure to the fourth embodiment of sub-pixel 13 and connecting via 122 provided in this application. The difference is that a part of the connecting via 122 is located on the side of a rectangle, and another part of the connecting via 122 is located in the corner area of ​​another rectangle.

[0102] In this embodiment, three sub-pixels 13 are combined to form a rectangular repeating unit. The repeating units are arranged in a matrix.

[0103] In each repeating unit, two sub-pixels 13 are arranged side by side along the row direction of the repeating unit and are located on the same side of another sub-pixel 13 along the column direction of the repeating unit. In each repeating unit, three adjacent isolation structures 14 share the same connecting via 122.

[0104] The connecting through hole 122 is located at the corner area of ​​the two rectangles formed by the two sub-pixels 13 arranged side by side, and is located on one side of the rectangle formed by the other sub-pixel 13.

[0105] In one specific embodiment, the aperture of the connecting through hole 122 is 15 micrometers.

[0106] In this embodiment, the design of the connecting via 122 can also reduce the spacing between sub-pixels 13, ensuring that the isolation structure 14 can be electrically connected to the silicon-based driving substrate 20 through the connecting via 122 without sacrificing the area of ​​the sub-pixels 13. Compared with the fourth embodiment of sub-pixels 13 and connecting via 122 provided in this application, the arrangement of sub-pixels 13 in this embodiment is different.

[0107] It should be understood that in other embodiments, within each repeating unit, a portion of the connecting through-holes 122 are located on the sides of the rectangle, and a portion of the connecting through-holes 122 are located in the corner areas of the rectangle (see...). Figure 7 The arrangement of sub-pixels 13 varies, and the setting of the connecting through-hole 122 is also diverse. There are no restrictions here, and the choice can be made according to actual needs.

[0108] Please see Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the display device provided in this application.

[0109] This application provides a display device 300. The display device 300 includes a motherboard 200 and the aforementioned display panel 100. The display device 300 in this embodiment is an AMOLED.

[0110] The motherboard 200 is electrically connected to the display panel 100. The motherboard 200 is used to transmit various required signals to the display panel 100 to control the display screen of the display panel 100. For example, clock signals (CK), low potential signals (Vss), power supply voltage signals (VDD), and data signals (Data) required by the driving circuit layer.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0112] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, characterized in that, include: Silicon-based driving substrate; The light-emitting carrier is bonded to the silicon-based driving substrate; The light-emitting carrier plate includes: Glass substrate with cathode via; A pixel definition layer is disposed on the side of the glass substrate away from the silicon-based driving substrate; the pixel definition layer has pixel openings and connection vias; A sub-pixel is disposed at the pixel opening; the sub-pixel includes an anode layer, a light-emitting layer, and a cathode layer stacked sequentially. An isolation structure protrudes from the pixel definition layer and is disposed on the side of the sub-pixel; the isolation structure includes a conductive portion and a top structure stacked sequentially; the cathode layer overlaps with the conductive portion to achieve mutual electrical connection between the cathode layers; Wherein, at least a portion of the conductive portion of the isolation structure is electrically connected to the silicon-based driving substrate by passing through the connection via and the cathode via in sequence; The glass substrate also has an anode via spaced apart from the cathode via, and the anode layer is electrically connected to the silicon-based driving substrate through the anode via; The anode through-holes are provided one-to-one with the anode layer and are located close to the cathode through-holes; The light-emitting carrier also includes an extended electrode, which is located on the side of the glass substrate away from the isolation structure; the extended electrode includes an anode extended electrode and a cathode extended electrode; The conductive portion is electrically connected to the cathode extension electrode through the connecting through hole and the cathode through hole in sequence, and the cathode extension electrode is bonded to the cathode driving electrode of the silicon-based driving substrate; The anode layer is electrically connected to the anode extension electrode through the anode via, and the anode extension electrode is bonded to the anode driving electrode of the silicon-based driving substrate.

2. The display panel according to claim 1, characterized in that, Each of the isolation structures corresponds to at least one of the connection vias.

3. The display panel according to claim 1, characterized in that, Multiple isolation structures share the same connection via.

4. The display panel according to claim 3, characterized in that, The multiple isolation structures are partially overlapped with each other and have a common overlapping area; the connecting through hole is disposed in the overlapping area.

5. The display panel according to claim 1, characterized in that, The sub-pixel is rectangular in a direction parallel to the glass substrate; The connecting through hole is located on the side of the rectangle; or, The connecting through hole is located in the corner area of ​​the rectangle; or, A portion of the connecting through hole is located on the side of the rectangle, and another portion of the connecting through hole is located in the corner area of ​​another rectangle.

6. The display panel according to claim 1, characterized in that, The silicon-based driving substrate includes a silicon substrate and a driving circuit layer; the driving circuit layer is disposed on the side of the silicon substrate close to the light-emitting carrier.

7. The display panel according to claim 1, characterized in that, In a direction parallel to the glass substrate, the top structure extends the conductive portion; the orthographic projection of the conductive portion on the glass substrate covers the orthographic projection of the connecting via on the glass substrate.

8. A display device, characterized in that, Includes the motherboard and the display panel according to any one of claims 1 to 7.

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