Memory operation method

Abstract

The application provides a memory operation method applied to a memory array including a plurality of split gate floating gate devices. The method comprises: applying a first voltage to a target bit line connected with a target memory part to be programmed; and applying a second voltage and a third voltage with different levels respectively to first and second bit lines connected with at least first and second inhibition memory parts on a target word line to be programmed and inhibited. The application can precisely inhibit according to the interference intensity by applying graded inhibition voltages to inhibition bit lines at different positions, effectively reduces the programming interference, improves the programming precision and data reliability, and helps to reduce the operation power consumption and device stress.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory operation method. Background Technology

[0002] Non-volatile memory, especially flash memory, is an indispensable data storage component in modern electronic systems. To improve the performance, density, and reliability of memory, the industry continues to develop new memory cell structures, among which split-gate floating gate devices are a structure that has attracted much attention.

[0003] Please refer to Figure 1 This illustrates a schematic diagram of a dual-separated-gate floating gate device. For example... Figure 1 As shown, the memory cell 101 is disposed on a semiconductor substrate 201. An active region 205(S) and a drain region 206(D) are formed in the substrate 201. Above the channel region between the source region 205 and the drain region 206, two separate first gate structures 102a and 102b are disposed, and a second gate structure 103 is located between them. Each first gate structure serves as an independent memory portion, including a floating gate 104 and a control gate 105, etc. The control gates 105 of the two first gate structures are respectively connected to independent control gate lines CG0 and CG1, while the word line gate 106 located between them is connected to a shared word line WL.

[0004] When programming this type of device, please refer to the appendix. Figure 2 The diagram shows a partial schematic of the memory array. A conventional programming method is as follows: For example, when programming a target memory segment 'a' on bit line bl0, a high programming voltage is applied to the control gate line CG0 and word line WL corresponding to that memory segment. Simultaneously, a programming enable voltage (e.g., ground) is applied to bit line bl0, which generates a programming current (Ibl0) of 1mA to 5mA to induce electrons to tunnel into the floating gate of the target memory segment.

[0005] To prevent other memory sections on the same word line WL from being incorrectly programmed, existing technology applies a uniform programming suppression voltage to the bit lines connected to these suppressed memory sections. For example, a suppression voltage of 4.5V is applied to bit line bl1 connected to memory section 'c' and bit line bl2 connected to adjacent cells (Vbl1 = 4.5V, Vbl2 = 4.5V).

[0006] However, this traditional method using a uniform suppression voltage has serious drawbacks. As device dimensions continue to shrink, the electric field coupling effect between cells becomes increasingly significant. The strong programming electric field applied to the target cell can still cause severe interference to adjacent memory sections. Specifically, even with a suppression voltage of 4.5V, this voltage is not optimal for suppression cells in different locations. For example, memory sections 'b' (located on the same bit line bl0 but belonging to adjacent word lines) and 'c' (located on adjacent bit lines bl1 and on the same word line WL), which are physically very close to the target cell 'a', will still be subject to significant programming interference, causing their threshold voltages to drift unexpectedly. This phenomenon is called programming interference, which severely affects data accuracy and memory reliability.

[0007] Therefore, there is an urgent need for a new programming bias scheme specifically designed for this type of split-gate floating-gate device structure to effectively suppress programming interference and improve the accuracy and consistency of programming operations. Summary of the Invention

[0008] The purpose of this application is to provide a memory operation method that aims to solve the problems of severe programming interference, low programming accuracy and reliability caused by the use of a uniform suppression voltage when programming discrete-gate floating-gate devices in the prior art.

[0009] To achieve the above and other related objectives, this application provides a memory operation method applied to a memory array including multiple discrete-gate floating-gate devices. The memory array includes multiple control gate lines, word lines, and bit lines. The method includes:

[0010] Step 1: Apply programming voltage to the target control gate line and target word line corresponding to the target memory section to be programmed;

[0011] Step 2: Apply various different voltages to multiple bit lines corresponding to multiple memory portions in the memory array. Specifically, apply a first voltage to the target bit line connected to the target memory portion; apply a second voltage and a third voltage to the first bit line and the second bit line connected to at least the first suppression memory portion and the second suppression memory portion to be programmed and suppressed on the target word line, respectively. The first voltage, the second voltage, and the third voltage are all different from each other.

[0012] Preferably, in step two, the first voltage is the ground voltage.

[0013] Preferably, in step two, the level of the second voltage is higher than the level of the third voltage.

[0014] Preferably, in step two, the second voltage is 3.0V to 4.0V and the third voltage is 1.0V to 2.0V.

[0015] Preferably, the second voltage is 3.5V and the third voltage is 1.5V.

[0016] Preferably, in step two, when the second voltage is applied to the first line, the current flowing through the first line is 10μA to 20μA.

[0017] Preferably, in step two, the method further includes: applying a floating state to the corresponding bit line connected to at least one other suppression storage portion other than the first suppression storage portion and the second suppression storage portion on the target word line that is to be programmed and suppressed.

[0018] Preferably, the split-gate floating-gate device includes: a substrate; a first source / drain region and a second source / drain region formed in the substrate; a channel region disposed between the first source / drain region and the second source / drain region; at least two first gate structures and one second gate structure, the first gate structures and the second gate structures being alternately disposed above the channel region; wherein each first gate structure constitutes a memory portion and includes a floating gate and a control gate located above the floating gate and connected to a control gate line; the second gate structure includes a word line gate connected to a word line; the first source / drain region and the second source / drain region are respectively connected to different bit lines.

[0019] Preferably, the split-gate floating gate device includes two first gate structures and a second gate structure located between the two first gate structures; the control gates of the two first gate structures are respectively connected to the first control gate line and the second control gate line.

[0020] As described above, the memory operation method of the present invention has the following beneficial effects:

[0021] This invention applies graded and differentiated suppression voltages to suppression memory sections at different distances, combined with floating processing of far-end bit lines. This enables precise suppression based on the spatial distribution of programming interference intensity, effectively reducing programming interference to adjacent memory sections and improving programming accuracy. Precise interference suppression avoids unexpected drift of the suppression cell threshold voltage, ensuring data accuracy and improving the programming uniformity and data reliability of the entire memory array. The graded voltage and floating strategy avoids applying unnecessarily high voltages to all suppression cells, reducing overall power consumption and current flowing through bit lines during operation. At the same time, lower electrical stress helps extend the device's erase / write life and durability. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a split-gate floating gate device provided in an embodiment of this application;

[0023] Figure 2 This is a partial schematic diagram of the memory array used in the memory operation method of this application embodiment;

[0024] Figure 3 This is a flowchart illustrating a memory operation method provided in an embodiment of this application. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] This application provides a memory operation method applied to a memory array including multiple discrete-gate floating-gate devices, the memory array including multiple control gate lines, word lines and bit lines.

[0027] Please see Figure 3 The methods include:

[0028] Step 1: Apply programming voltage to the target control gate line and target word line corresponding to the target memory section to be programmed.

[0029] This step aims to establish the necessary electric field conditions for programming the target memory section. The applied programming voltage, typically referred to as Vpgm, is high enough to generate a strong electric field on the tunneling dielectric layer of the target memory section in conjunction with subsequent steps, allowing electrons to be injected from the channel region into the floating gate.

[0030] Step 2: Apply various different voltages to multiple bit lines corresponding to multiple storage sections in the memory array.

[0031] Specifically, a first voltage is applied to the target bit line connected to the target storage section.

[0032] In some embodiments, in step two, the first voltage is a ground voltage. Grounding the target bit line (e.g., 0V) clamps the channel potential beneath the target memory portion to a minimum level, thereby maximizing the potential difference between the control gate and the channel. This helps to create the strongest tunneling electric field on the tunneling dielectric layer, enabling efficient electron injection and fast programming.

[0033] Specifically, a second voltage and a third voltage are applied to the first bit line and the second bit line connected to at least the first suppression storage portion and the second suppression storage portion to be programmed and suppressed on the target word line, respectively, wherein the first voltage, the second voltage and the third voltage are different from each other.

[0034] This step is one of the core aspects of this application. By applying different levels of suppression voltage to suppression cells at different locations, programming interference can be precisely countered. Since the interference effect of the programming electric field attenuates with increasing distance, applying one voltage to the first suppression memory section, which is closest to the target cell and most severely affected by interference, and applying a different voltage to the second suppression memory section, which is slightly farther away and less affected, achieves a graded and differentiated suppression effect. This refined biasing scheme can more effectively stabilize the channel potential beneath the suppression cells, preventing unintended drift in their threshold voltage, thereby significantly improving the accuracy of programming operations and the data reliability of the entire memory array.

[0035] In some embodiments, in step two, the level of the second voltage is higher than the level of the third voltage. Typically, the first suppression memory section is the cell physically closest to the target memory section, and therefore experiences the strongest coupling interference. Applying a relatively high second voltage to it can more forcefully raise the channel potential below it, thereby more effectively counteracting programming interference. For the second suppression memory section, which is slightly further away, the interference is weaker; therefore, applying a relatively low third voltage can satisfy the requirement of suppressing programming while reducing power consumption and electrical stress on the device, thus contributing to improved device durability and lifespan.

[0036] In some embodiments, in step two, the second voltage is 3.0V to 4.0V and the third voltage is 1.0V to 2.0V. In a preferred embodiment, in step two, the second voltage is 3.5V and the third voltage is 1.5V.

[0037] In some embodiments, in step two, when the second voltage is applied to the first bit line, the current flowing through the first bit line is 10μA to 20μA. Compared to the programming current, which may be as high as several milliamps in conventional programming methods, the suppression current in the method of this application is controlled at the microamp level. This helps to reduce the overall power consumption of the array, reduce the voltage drop on the bit line, and make the bias voltage applied to each cell more accurate, further improving the consistency and uniformity of programming.

[0038] In some embodiments, step two further includes applying a floating state to the corresponding bit lines connected to at least one other suppression memory portion (besides the first and second suppression memory portions) on the target word line that is to be programmed and suppressed. For suppression cells farther from the target cell, the programming interference they experience is already very weak. In this case, placing their corresponding bit lines in a floating state is an efficient suppression strategy. These floating bit lines will passively raise their potential to an intermediate potential sufficient to suppress programming through the capacitive coupling effect between them and the high-voltage word lines and control gate lines. This approach eliminates the need for an external drive circuit to provide a precise voltage, thereby simplifying peripheral circuit design and further reducing operating power consumption.

[0039] The following is combined Figure 2 To illustrate a specific programming scenario. Figure 2 A portion of a memory array is shown. Assume that a target memory segment 'a', intersecting the control gate line CG0 and the word line WL, needs to be programmed. According to the method of this application, a first voltage, in this embodiment ground voltage 0V (Vbl0 = 0V), is applied to the target bit line bl0 connected to the target memory segment 'a'. Memory segment 'c', being the first suppressed memory segment located on the same word line and physically closest to the target memory segment 'a', is most susceptible to programming interference. Therefore, a relatively high second voltage, such as 3.5V (Vbl1 = 3.5V), is applied to the first bit line bl1 connected to memory segment 'c', at which point the current flowing through bit line bl1 is approximately 15μA. The memory segment located on bit line bl2, being a slightly farther second suppressed memory segment, is less susceptible to interference. Therefore, a relatively low third voltage, such as 1.5V (Vbl2 = 1.5V), is applied to the second bit line bl2 connected to this memory segment. For other suppressed memory sections located further away on bit lines bl3 to bl5, the corresponding bit lines bl3 to bl5 are applied in a floating state. Through this refined, hierarchical voltage bias scheme, programming interference to the most critical adjacent memory sections 'b' (located on the same bit line) and 'c' (located on adjacent bit lines) can be specifically suppressed, thereby improving programming uniformity.

[0040] The split-gate floating-gate device used in the operation method of this application includes: a substrate; a first source / drain region and a second source / drain region formed in the substrate; a channel region disposed between the first source / drain region and the second source / drain region; at least two first gate structures and one second gate structure, wherein the first gate structure and the second gate structure are alternately disposed above the channel region. Each first gate structure constitutes a memory portion and includes a floating gate and a control gate located above the floating gate and connected to a control gate line; the second gate structure includes a word line gate connected to a word line; the first source / drain region and the second source / drain region are respectively connected to different bit lines.

[0041] In some embodiments, the substrate may be a P-type single-crystal silicon substrate. Alternatively, a silicon-on-insulator (SOI) substrate may be used to reduce latch-up effects and parasitic capacitance, or strained silicon technology such as silicon-germanium (SiGe) may be used to improve carrier mobility and device performance.

[0042] In some embodiments, the first source / drain region and the second source / drain region are N+ heavily doped regions. N-type dopants such as phosphorus (P) or arsenic (As) can be implanted into the P-type substrate through ion implantation. The dopants can then be activated and lattice damage repaired through subsequent rapid thermal annealing (RTA) and other processes.

[0043] In some embodiments, the floating gate in the first gate structure can be made of heavily doped N-type or P-type polysilicon. In other embodiments, the floating gate can be replaced by a charge trapping layer, such as a silicon nitride (SiN) layer, to trap charges, forming charge-trapped memories with structures such as SONOS or TANOS. The tunneling dielectric layer can be an ultrathin thermally grown silicon dioxide (SiO2) layer, the thickness of which needs to be precisely controlled within a few nanometers to balance programming speed and data retention time. To improve reliability, the tunneling dielectric layer can also be a multilayer structure, such as a silicon oxide / silicon nitride / silicon oxide (ONO) stack. The control gate can be made of doped polysilicon or a metal gate material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or combinations thereof. Using a metal gate helps to eliminate the polysilicon depletion effect and improve device performance. The control gate dielectric layer (also known as IPD) between the control gate and the floating gate can be an ONO stacked structure, or a high-k material such as alumina (Al2O3) or hafnium oxide (HfO2) can be used to obtain a higher gate coupling ratio, thereby reducing the operating voltage.

[0044] In some embodiments, the word line gate in the second gate structure can also be made of doped polysilicon or a metal gate material. The underlying gate dielectric layer is typically a relatively thick layer of silicon dioxide to ensure its stability and high reliability as a select transistor and to prevent accidental charge injection or leakage under various operating bias voltages.

[0045] In some embodiments, the split-gate floating-gate device includes two first gate structures and a second gate structure located between the two first gate structures; the control gates of the two first gate structures are respectively connected to a first control gate line and a second control gate line. This dual-memory structure allows a single device to store multiple bits of information, improving storage density.

[0046] To gain a more comprehensive understanding of the discrete-gate floating-gate device involved in this application, the method can employ a replacement gate process. The method can begin by providing a semiconductor substrate, such as a P-type single-crystal silicon substrate 201. An isolation region is formed on the substrate 201 using processes such as shallow trench isolation (STI) to define the effective area of ​​the device. Next, a material layer for forming the sacrificial gate, such as a polysilicon layer, is sequentially deposited on the substrate, and sacrificial gate structures are formed at locations where the first and second gate structures will be formed in the future, using photolithography and etching processes. Using these sacrificial gate structures as masks, N-type dopants are implanted into the exposed areas of the substrate using an ion implantation process to form self-aligned first source / drain regions 205 and second source / drain regions 206. Then, an interlayer dielectric (ILD) material, such as silicon dioxide, is deposited over the entire structure, and the interlayer dielectric is chemically mechanically polished (CMP) until the top of the sacrificial gate structure is exposed. Subsequently, a selective etching process is used to remove the sacrificial gate structure, thereby leaving a gate trench in the interlayer dielectric corresponding to the original sacrificial gate. For trenches used to form the second gate structure (select gate), a gate dielectric layer 204 is first formed at its bottom using methods such as thermal oxidation or atomic layer deposition (ALD). Then, word line gate material, such as tungsten (W), is filled in, and planarization is performed to form the word line gate 106. For trenches used to form the first gate structure (memory gate), the process is more complex: a tunneling dielectric layer 202 is first formed at the bottom of the trench. Next, material (such as polysilicon) is deposited and patterned to form the floating gate 104. Then, a control gate dielectric layer 203 is formed on top of it. Finally, material (such as a metal gate stack) is filled in for the control gate 105, and planarization is completed. Finally, using standard back-end online (BEOL) processes, metal layers are deposited, photolithography is performed, and etching is used to form electrodes and interconnects connecting the source / drain regions and each gate, completing the device fabrication.

[0047] In summary, the method provided in this application, by applying differentiated, multi-level suppression voltages to suppression bit lines at different locations during programming operations, and combining this with floating processing of far-end bit lines, can achieve precise and hierarchical suppression based on the spatial distribution of interference intensity. Compared with the prior art's use of a uniform suppression voltage, this application can more effectively suppress interference to adjacent memory sections caused by programming operations, especially for compact split-gate floating-gate devices, where the suppression effect is more significant. This not only improves data write accuracy and reliability but also reduces the electrical stress of the device by avoiding unnecessarily high voltages applied to all suppression cells, thus helping to extend the erase and write life of the memory. Simultaneously, the combination of hierarchical voltage and the floating strategy optimizes power consumption during operation, enabling the memory to maintain good energy efficiency while achieving high performance. Ultimately, the method of this application helps improve the overall performance, reliability, and durability of split-gate flash memory devices.

[0048] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A memory operation method applied to a memory array comprising multiple discrete-gate floating-gate devices, the memory array including multiple control gate lines, word lines, and bit lines, characterized in that, At least including: Step 1: Apply programming voltage to the target control gate line and target word line corresponding to the target memory section to be programmed; Step 2: Apply various different voltages to multiple bit lines corresponding to multiple storage portions in the memory array, wherein... A first voltage is applied to the target bit line connected to the target storage portion; A second voltage and a third voltage are applied to a bit line and a second bit line connected to at least a first suppression memory portion and a second suppression memory portion to be programmed and suppressed on the target word line, respectively, wherein the first voltage, the second voltage and the third voltage are different from each other; A floating state is applied to the corresponding bit line connected to at least one other suppression memory portion other than the first suppression memory portion and the second suppression memory portion that is to be programmed and suppressed on the target word line.

2. The memory operation method according to claim 1, characterized in that: In step two, the first voltage is the ground voltage.

3. The memory operation method according to claim 1 or 2, characterized in that: In step two, the level of the second voltage is higher than the level of the third voltage.

4. The memory operation method according to claim 1, characterized in that: In step two, the second voltage is 3.0V to 4.0V, and the third voltage is 1.0V to 2.0V.

5. The memory operation method according to claim 4, characterized in that: In step two, the second voltage is 3.5V and the third voltage is 1.5V.

6. The memory operation method according to claim 4 or 5, characterized in that: In step two, when the second voltage is applied to the first bit line, the current flowing through the first bit line is 10μA to 20μA.

7. The memory operation method according to claim 1, characterized in that: The split-gate floating-gate device includes: a substrate; a first source / drain region and a second source / drain region formed in the substrate; a channel region disposed between the first source / drain region and the second source / drain region; at least two first gate structures and one second gate structure, the first gate structures and the second gate structures being alternately disposed above the channel region; wherein each first gate structure constitutes a memory portion and includes a floating gate and a control gate located above the floating gate and connected to the control gate line; the second gate structure includes a word line gate connected to the word line; the first source / drain region and the second source / drain region are respectively connected to different bit lines.

8. The memory operation method according to claim 7, characterized in that: The split-gate floating gate device includes two first gate structures and a second gate structure located between the two first gate structures; the control gates of the two first gate structures are respectively connected to a first control gate line and a second control gate line.

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