A chip multilayer ceramic capacitor and a manufacturing method and application thereof

Abstract

The application belongs to the field of electronic component manufacturing, and specifically discloses a chip multilayer ceramic capacitor and a preparation method and application thereof; the chip multilayer ceramic capacitor is prepared by a preparation method comprising the following steps: pre-sintering a green body of a ceramic layer stack after degreasing by heating in a first reducing atmosphere, and cooling; then, formally sintering by heating in a second reducing atmosphere, and cooling; then, oxidizing by heating in an oxidizing atmosphere, and then processing to obtain the chip multilayer ceramic capacitor. The preparation method in the application pre-sinters the green body of the ceramic layer stack after degreasing in a strong reducing atmosphere, creates oxygen vacancies in the green body of the ceramic layer stack to improve sintering activity, makes the crystal grains grow uniformly, and further improves the electrode continuity, capacity and insulation resistance of the prepared chip multilayer ceramic capacitor, prevents electrode spheroidization, improves the comprehensive performance of the chip multilayer ceramic capacitor, and enables the chip multilayer ceramic capacitor to meet the use requirements of electronic equipment.

Description

Technical Field

[0001] This invention belongs to the field of electronic component manufacturing, specifically relating to a chip multilayer ceramic capacitor, its preparation method, and its application. Background Technology

[0002] Multilayer ceramic chip capacitors (MLCCs) are widely used in computers, mobile electronic devices, and new energy vehicle electronic devices due to their small size, high capacitance, and ease of installation. The typical manufacturing process for multilayer ceramic chip capacitors includes: fabricating a ceramic dielectric layer; printing an internal electrode layer on the ceramic dielectric layer; stacking and cutting the ceramic dielectric layers with internal electrode layers to form a laminated green body; sintering the laminated green body at high temperature to form a ceramic chip; and finally fabricating external electrodes at both ends of the ceramic chip to form the multilayer ceramic capacitor.

[0003] The sintering process of stacked green bodies has a significant impact on the performance of MLCCs. Existing sintering processes suffer from problems such as low sintering activity, difficulty in grain growth or uneven grain size distribution, and electrode spheroidization due to long sintering times, which in turn lead to poor electrical performance of MLCCs and affect their applications. Summary of the Invention

[0004] In order to overcome at least one of the technical problems existing in the prior art, one of the objectives of the present invention is to provide a method for preparing a chip multilayer ceramic capacitor.

[0005] The second objective of this invention is to provide a chip-type multilayer ceramic capacitor.

[0006] A third objective of this invention is to provide a method for preparing the above-mentioned multilayer ceramic chip capacitor or an application of the above-mentioned multilayer ceramic chip capacitor in the field of electronic devices.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The first aspect of the present invention provides a method for fabricating a chip multilayer ceramic capacitor, comprising the following steps: The ceramic laminated green body after debinding is pre-sintered under a first reducing atmosphere and then cooled; then it is sintered under a second reducing atmosphere and then cooled; then it is oxidized under an oxidizing atmosphere and then processed to obtain the chip multilayer ceramic capacitor. Both the first reducing atmosphere and the second reducing atmosphere contain hydrogen, and the volume percentage of hydrogen in the first reducing atmosphere is greater than the volume percentage of hydrogen in the second reducing atmosphere.

[0008] Existing technologies employ a one-step sintering process in the fabrication of multilayer ceramic chip capacitors (MLCCs). This invention adds a pre-sintering step. Compared to the formal sintering step, the hydrogen content in the first reducing atmosphere is higher than in the second reducing atmosphere. This allows the MLCC product to undergo pre-sintering under a strong reducing atmosphere. During this pre-sintering, some oxygen atoms in the dielectric lattice of the ceramic laminate react with hydrogen, forming oxygen vacancy defects. This increases the activity of the dielectric grains during sintering, enabling uniform grain growth and improving product capacity. Simultaneously, due to the increased sintering activity, the sintering step in this invention is shorter than in existing technologies, thus saving energy and improving production efficiency. The shorter sintering time also improves electrode continuity, reducing the likelihood of electrode spheroidization.

[0009] In some embodiments of the present invention, the heating rate of the pre-sintering step is greater than or equal to the heating rate of the formal sintering step.

[0010] In some embodiments of the present invention, the ceramic laminate green body includes an inner electrode layer and a ceramic dielectric layer stacked together.

[0011] In some embodiments of the present invention, the material of the ceramic dielectric layer includes barium titanate.

[0012] In some embodiments of the present invention, the material of the inner electrode layer includes at least one of nickel, silver, and copper.

[0013] In some embodiments of the present invention, the pre-sintering temperature is 960~1300℃; in some embodiments of the present invention, the pre-sintering temperature is any value or a range formed by any combination of 960℃, 980℃, 1000℃, 1020℃, 1040℃, 1050℃, 1060℃, 1080℃, 1100℃, 1120℃, 1140℃, 1150℃, 1160℃, 1180℃, 1200℃, 1220℃, 1240℃, 1250℃, 1260℃, 1280℃, and 1300℃. In some preferred embodiments of the present invention, the pre-sintering temperature is 1000~1250℃.

[0014] In some embodiments of the present invention, the heating rate of the pre-sintering is 100~2000℃ / min; in some embodiments of the present invention, the heating rate of the pre-sintering is any value or a range formed by any two of the following: 100℃ / min, 200℃ / min, 300℃ / min, 400℃ / min, 500℃ / min, 600℃ / min, 700℃ / min, 800℃ / min, 900℃ / min, 1000℃ / min, 1100℃ / min, 1200℃ / min, 1300℃ / min, 1400℃ / min, 1500℃ / min, 1600℃ / min, 1700℃ / min, 1800℃ / min, 1900℃ / min, and 2000℃ / min.

[0015] In some embodiments of the present invention, the pre-sintering holding time is 1 to 35 min; in some embodiments of the present invention, the pre-sintering holding time is any value or a range formed by any two of 1 min, 3 min, 5 min, 6 min, 8 min, 10 min, 12 min, 15 min, 18 min, 20 min, 22 min, 25 min, 28 min, and 30 min; in some preferred embodiments of the present invention, the pre-sintering holding time is 1 to 30 min.

[0016] In some embodiments of the present invention, the formal sintering temperature is 1120~1350℃; in some embodiments of the present invention, the formal sintering temperature is any value or a range formed by any two of 1120℃, 1140℃, 1150℃, 1160℃, 1180℃, 1200℃, 1220℃, 1240℃, 1250℃, 1260℃, 1280℃, 1300℃, 1320℃, 1340℃, and 1350℃.

[0017] In some embodiments of the present invention, the heating rate of the formal sintering is 50~2000℃ / min; in some embodiments of the present invention, the heating rate of the formal sintering is any value or a range formed by any two of the following: 50℃ / min, 100℃ / min, 200℃ / min, 300℃ / min, 400℃ / min, 500℃ / min, 600℃ / min, 700℃ / min, 800℃ / min, 900℃ / min, 1000℃ / min, 1100℃ / min, 1200℃ / min, 1300℃ / min, 1400℃ / min, 1500℃ / min, 1600℃ / min, 1700℃ / min, 1800℃ / min, 1900℃ / min, and 2000℃ / min.

[0018] In some embodiments of the present invention, the holding time for formal sintering is 0.5 to 30 min; in some embodiments of the present invention, the holding time for formal sintering is any value of 0.5 min, 1 min, 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, or a range formed by any two of these values.

[0019] In some embodiments of the present invention, the oxidation treatment temperature is 930~1100℃; in some embodiments of the present invention, the oxidation treatment temperature is any value of 930℃, 940℃, 950℃, 960℃, 970℃, 980℃, 990℃, 1000℃ or a range formed by any two of them.

[0020] In some embodiments of the present invention, the heating rate of the oxidation treatment is 3~50℃ / min; in some embodiments of the present invention, the heating rate of the oxidation treatment is any value or a range formed by any two of the following: 3℃ / min, 5℃ / min, 10℃ / min, 15℃ / min, 20℃ / min, 25℃ / min, 30℃ / min, 35℃ / min, 40℃ / min, 45℃ / min, 50℃ / min.

[0021] In some embodiments of the present invention, the holding time of the oxidation treatment is 2 to 6 hours; in some embodiments of the present invention, the holding time of the oxidation treatment is any value of 2 hours, 2.5 hours, 3 hours, 3.5 hours, 4 hours, 4.5 hours, 5 hours, 5.5 hours, 6 hours, or a range formed by any two of these values.

[0022] In some embodiments of the present invention, the oxygen concentration in the oxidation treatment step is 0~60 ppm; in some embodiments of the present invention, the oxygen concentration in the oxidation treatment step is any value or a range formed by any two of 0 ppm, 5 ppm, 10 ppm, 15 ppm, 20 ppm, 25 ppm, 30 ppm, 35 ppm, 40 ppm, 45 ppm, 50 ppm, 55 ppm, and 60 ppm. When the oxygen concentration in the oxidation treatment step is 0, the oxygen produced by the high-temperature decomposition of water vapor will fill the oxygen vacancies, thereby achieving the oxidation treatment.

[0023] In some embodiments of the present invention, the first reducing atmosphere contains 0.3% to 3% hydrogen by volume; in some embodiments of the present invention, the volume percentage of hydrogen in the first reducing atmosphere is any value or a range formed by any two of the following: 0.3%, 0.4%, 0.5%, 0.6%, 0.8%, 1%, 1.2%, 1.4%, 1.5%, 1.6%, 1.8%, 2%, 2.2%, 2.4%, 2.5%, 2.6%, 2.8%, and 3%; in some preferred embodiments of the present invention, the first reducing atmosphere contains 0.3% to 2.5% hydrogen by volume.

[0024] In some embodiments of the present invention, the second reducing atmosphere contains hydrogen gas at a volume percentage of 0.1 to 0.3%; in some embodiments of the present invention, the volume percentage of hydrogen gas in the second reducing atmosphere is any value of 0.1%, 0.15%, 0.2%, 0.25%, 0.3% or a range formed by any two of these values.

[0025] In this invention, the volume percentage of hydrogen in the first reducing atmosphere and the volume percentage of hydrogen in the second reducing atmosphere are not both 0.3%.

[0026] In some embodiments of the present invention, the first reducing atmosphere, the second reducing atmosphere, and the oxidizing atmosphere all contain water vapor and a protective gas.

[0027] In some embodiments of the present invention, the first reducing atmosphere, the second reducing atmosphere, and the oxidizing atmosphere each contain 3 to 11% water vapor by volume.

[0028] In some embodiments of the present invention, the first reducing atmosphere is composed of the following gas by volume percentage: 0.1-3% hydrogen, 3-11% water vapor, and the balance being a protective gas.

[0029] In some embodiments of the present invention, the second reducing atmosphere is composed of the following gas by volume percentage: 0.1-0.3% hydrogen, 3-11% water vapor, and the balance being a protective gas.

[0030] In some embodiments of the present invention, the oxidizing atmosphere is composed of the following gas by volume percentage: oxygen 0-60 ppm, water vapor 3-11%, and protective gas as the balance.

[0031] In some embodiments of the present invention, the volume percentage of water vapor in the first reducing atmosphere is selected from any value of 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, or a range formed by any two of these values.

[0032] In some embodiments of the present invention, the volume percentage of water vapor in the second reducing atmosphere is selected from any value of 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, or a range formed by any two of these values.

[0033] In some embodiments of the present invention, the volume percentage of water vapor in the oxidizing atmosphere is selected from any value of 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, or a range formed by any two of these values.

[0034] In some embodiments of the present invention, the protective gas is selected from at least one of nitrogen, argon, and helium.

[0035] In some embodiments of the present invention, the cooling is natural cooling; in some embodiments of the present invention, the cooling step is natural cooling to 20~40°C.

[0036] In some embodiments of the present invention, the ceramic laminated green body after debinding is prepared by a method including the following steps: The ceramic slurry is cast into a film to obtain a ceramic dielectric layer; An internal electrode paste is printed on the ceramic dielectric layer to obtain a ceramic dielectric layer containing an internal electrode layer. After stacking, pressing, and cutting the ceramic dielectric layer containing the inner electrode layer, a ceramic laminate green body is obtained. The binder is removed from the ceramic laminate green body to obtain the binder-removed ceramic laminate green body.

[0037] In some embodiments of the present invention, the ceramic slurry includes barium titanate, polyvinyl butyral (PVB), terpineol, and 2-ethylhexanoic acid.

[0038] In some embodiments of the present invention, the mass ratio of terpineol to barium titanate is (0.1~1):1; in some embodiments of the present invention, the mass ratio of terpineol to barium titanate is any value or a range formed by any two of the following: 0.1:1, 0.2:1, 0.3:1, 0.4:1, 0.5:1, 0.6:1, 0.7:1, 0.8:1, 0.9:1, 1:1.

[0039] In some embodiments of the present invention, the mass ratio of polyvinyl butyral (PVB) to barium titanate is (1.5~2.5):1; in some embodiments of the present invention, the mass ratio of polyvinyl butyral (PVB) to barium titanate is any value or a range formed by any two of the following: 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2.0:1, 2.1:1, 2.2:1, 2.3:1, 2.4:1, 2.5:1.

[0040] In some embodiments of the present invention, the mass ratio of 2-ethylhexanoic acid to barium titanate is (0.01~0.05):1; in some embodiments of the present invention, the mass ratio of 2-ethylhexanoic acid to barium titanate is any value of 0.01:1, 0.02:1, 0.03:1, 0.04:1, 0.05:1 or a range formed by any two of these values.

[0041] In some embodiments of the present invention, the internal electrode slurry comprises nickel powder, ethyl cellulose, terpineol, and 2-(11-methyldodecyloxy)ethanol phosphate.

[0042] In some embodiments of the present invention, the mass ratio of terpineol to nickel powder is (0.1~0.25):1; in some embodiments of the present invention, the mass ratio of terpineol to nickel powder is any value of 0.1:1, 0.15:1, 0.2:1, 0.25:1 or a range formed by any two of them.

[0043] In some embodiments of the present invention, the mass ratio of ethyl cellulose to nickel powder is (0.3~0.5):1; in some embodiments of the present invention, the mass ratio of ethyl cellulose to nickel powder is any value of 0.3:1, 0.35:1, 0.4:1, 0.45:1, 0.5:1 or a range formed by any two of these values.

[0044] In some embodiments of the present invention, the mass ratio of 2-(11-methyldodecyloxy)ethanol phosphate to nickel powder is (0.01~0.03):1; in some embodiments of the present invention, the mass ratio of 2-(11-methyldodecyloxy)ethanol phosphate to nickel powder is any value of 0.01:1, 0.02:1, 0.03:1 or a range formed by any two of these values.

[0045] In some embodiments of the present invention, after pre-sintering, the oxygen vacancy content of the ceramic dielectric layer is 8.25 × 10⁻⁶. 6 ~3.25×10 13 pcs / mm 3 In some preferred embodiments of the present invention, after pre-sintering, the oxygen vacancy content of the ceramic dielectric layer is 1.25 × 10⁻⁶. 10 ~9.75×10 12 pcs / mm 3 This invention introduces oxygen vacancies in the pre-sintering step, thereby improving the activity of the sintering process. Studies have found that when the oxygen vacancy content after pre-sintering is limited to 1.25 × 10⁻⁶, the effect is significant. 10 ~9.75×10 12 pcs / mm 3Within this range, good sintering results can be achieved. Below this range, the improvement in sintering activity is limited, while above this range, it is not conducive to controlling the grain size, resulting in larger grain sizes and posing certain difficulties for the oxidation process. Therefore, the oxygen vacancy content of the pre-sintered ceramic dielectric layer is preferably 1.25 × 10⁻⁶. 10 ~9.75×10 12 pcs / mm 3 .

[0046] In some embodiments of the present invention, after formal sintering, the oxygen vacancy content of the ceramic dielectric layer is 9.14 × 10⁻⁶. 6~ 3.59×10 13 pcs / mm 3 In some preferred embodiments of the present invention, after formal sintering, the oxygen vacancy content of the ceramic dielectric layer is 1.4 × 10⁻⁶. 10 ~1.1×10 13 pcs / mm 3 .

[0047] In some embodiments of the present invention, after oxidation treatment, the oxygen vacancy content of the ceramic dielectric layer is 3.02 × 10⁻⁶. 5 ~1.82×10 11 pcs / mm 3 In some preferred embodiments of the present invention, after oxidation treatment, the oxygen vacancy content of the ceramic dielectric layer is 6 × 10⁻⁶. 8 ~1×10 11 pcs / mm 3 .

[0048] The study found that the oxygen vacancy content in the ceramic dielectric layer after pre-sintering, formal sintering, and oxidation treatment was maintained within the above range. After pre-sintering and formal sintering, sufficient sintering activity and full and uniform grain growth were ensured. After oxidation treatment, oxygen vacancy was completely replenished, avoiding problems such as ceramic semiconductivity and decreased insulation.

[0049] A second aspect of the present invention provides a chip multilayer ceramic capacitor, which is prepared by the aforementioned method.

[0050] In some embodiments of the present invention, the electrode continuity of the internal electrode of the chip multilayer ceramic capacitor is 71-95%; in some preferred embodiments of the present invention, the electrode continuity of the internal electrode of the chip multilayer ceramic capacitor is 81-95%.

[0051] In some embodiments of the present invention, the capacitance of the chip multilayer ceramic capacitor is 0.82~1.64μF; in some preferred embodiments of the present invention, the capacitance of the chip multilayer ceramic capacitor is 0.96~1.64μF.

[0052] In some embodiments of the present invention, the insulation resistance of the chip multilayer ceramic capacitor is 0.76~1.2 GΩ; in some preferred embodiments of the present invention, the insulation resistance of the chip multilayer ceramic capacitor is 1.01~1.2 GΩ.

[0053] The third aspect of the present invention provides the application of the preparation method described in the first aspect of the present invention or the chip multilayer ceramic capacitor described in the second aspect of the present invention in the field of electronic devices.

[0054] The beneficial effects of the present invention are as follows: The preparation method of the present invention pre-sintersects the ceramic laminate green body after debinding in a first reducing atmosphere with a high hydrogen concentration, thereby creating oxygen vacancies in the ceramic laminate green body to improve sintering activity, making the grains grow uniformly, thereby improving the electrode continuity, capacitance and insulation resistance of the prepared chip multilayer ceramic capacitor, preventing electrode spheroidization, improving the overall performance of the chip multilayer ceramic capacitor, and enabling it to meet the needs of electronic devices. Detailed Implementation

[0055] The following examples provide a more detailed description of the specific implementation of the present invention, but the implementation and protection of the present invention are not limited thereto. It should be noted that any processes not specifically described below are methods that can be implemented or understood by those skilled in the art by referring to existing technology. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0056] Example 1 This example provides a method for fabricating a multilayer ceramic chip capacitor, including the following steps: (1) Barium titanate powder, polyvinyl butyral (PVB), terpineol and 2-ethylhexanoic acid are mixed and ball-milled in a mass ratio of barium titanate:PVB:terpineol:2-ethylhexanoic acid = 3.5:5.5:1:0.1 to obtain ceramic slurry. Then the ceramic slurry is cast into a film and dried to obtain ceramic dielectric layer (i.e. dielectric layer). (2) Nickel powder, ethyl cellulose, terpineol and 2-(11-methyldodecoxy)ethanol phosphate are mixed evenly in a mass ratio of nickel powder: ethyl cellulose: terpineol: 2-(11-methyldodecoxy)ethanol phosphate = 6.5: 2.5: 1: 0.1 to obtain an internal electrode paste. The internal electrode paste is printed on the ceramic dielectric layer obtained in step (1). After drying, an internal electrode layer is formed on the ceramic dielectric layer. (3) The ceramic dielectric layer with the inner electrode layer is stacked, pressed and cut to obtain a ceramic laminate green body; (4) The obtained ceramic laminate green body is placed in a debinding furnace for debinding treatment. The temperature is raised to 600℃ at a heating rate of 20℃ / min, held for 5 hours, and then naturally cooled to room temperature. (5) The ceramic laminate green body after debinding is sintered according to the following sintering method to obtain ceramic chip.

[0057] Step a: Pre-sintering. The ceramic laminated green body is pre-sintered under a first reducing atmosphere consisting of H2, N2, and H2O, with H2 comprising 2% by volume, H2O comprising 11% by volume, and the balance being N2. The temperature is increased to 1120℃ (the sintering temperature) at a heating rate of 600℃ / min, held for 6 minutes, and then allowed to cool naturally to room temperature.

[0058] Step b: Formal sintering. The ceramic laminated green body is sintered under a second reducing atmosphere, which consists of H2, N2 and H2O, with H2 accounting for 0.1% by volume, H2O accounting for 11% by volume, and the balance being N2. The temperature is raised to 1220℃ at a heating rate of 300℃ / min, held for 5 min, and then allowed to cool naturally to room temperature. Step c: Oxidation. The ceramic laminate green body is re-oxidized in an oxidizing atmosphere, wherein the O2 concentration is 30 ppm (1 ppm means 0.0001% by volume), the H2O by volume is 11%, and the balance is nitrogen. The temperature is raised to 930℃ (oxidation temperature) at a heating rate of 20℃ / min and held for 6 hours. Then the temperature is cooled to room temperature by natural cooling, as shown in Tables 1 and 2 below.

[0059] (6) The ceramic chip is chamfered, covered with external electrode paste and fired to obtain the chip multilayer ceramic capacitor in this example.

[0060] Examples 2-5 The only difference between the preparation methods of the chip multilayer ceramic capacitors in Examples 2-5 and Example 1 is that the volume percentage of hydrogen in the first reducing atmosphere is different in step a, as shown in Tables 1-2 below.

[0061] Examples 6-9 The only difference between the preparation methods of the chip multilayer ceramic capacitors in Examples 6-9 and Example 1 is that the sintering temperature in step a is different, as shown in Tables 1-2 below.

[0062] Examples 10-13 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 10-13 and Example 1 is that the heat preservation time in step a is different, as shown in Tables 1-2 below.

[0063] Examples 14-15 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 14-15 and Example 1 is that the concentration of oxygen in the oxidizing atmosphere is different in step c, as shown in Tables 1-2 below.

[0064] Examples 16-17 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 16-17 and Example 1 is that the oxidation temperature is different in step c, as shown in Tables 1-2 below.

[0065] Examples 18-19 The only difference between the preparation method of the chip multilayer ceramic capacitor in Examples 18-19 and Example 1 is that the heat preservation time is different in step c, as shown in Tables 1-2 below.

[0066] Examples 20-21 The preparation methods of the chip multilayer ceramic capacitors in Examples 20-21 differ from those in Example 1 only in the following aspects: the heating rate in step a is different; the heating rate, sintering temperature, holding time, and volume percentage of hydrogen in the second reducing atmosphere are different in step b; and the heating rate in step c is different, as shown in Tables 1-2 below.

[0067] Comparative Example 1 The only difference between the preparation method of the chip multilayer ceramic capacitor in this example and that in Example 1 is that this example is prepared according to the existing technology, without a pre-sintering stage. The formal sintering and oxidation steps are the same as in Example 1, as shown in Tables 1 and 2 below.

[0068] Comparative Example 2 The only difference between the preparation method of the chip multilayer ceramic capacitor in this example and that in Example 1 is that this example is prepared according to the existing preparation method, without a pre-sintering stage and the holding time in the formal sintering step is 60 min, as shown in Tables 1 and 2 below. Table 1 Parameters for pre-sintering and formal sintering steps

[0069] Table 2 Parameters of the oxidation step

[0070] Performance testing: The performance of the chip multilayer ceramic capacitors prepared in Examples 1-21 and Comparative Examples 1-2 were tested according to the following test methods, as follows: Oxygen vacancy quantity test: The oxygen vacancy content of the ceramic dielectric layer in the ceramic chip after the pre-sintering, formal sintering and oxidation steps was tested by electron paramagnetic resonance spectroscopy (EPR).

[0071] Grain size and standard deviation: Grain size was observed using a scanning electron microscope (SEM), and the grain size and standard deviation were statistically analyzed.

[0072] Electrode continuity test: The side of the MLCC is polished and the continuity and spheroidization of the electrodes are observed using a metallographic microscope, and the electrode continuity is calculated.

[0073] Capacitance testing: The capacitance of the fabricated multilayer ceramic chip capacitor was tested using an impedance analyzer under the conditions of 1.0±0.2Vrms and 1kHz±10%.

[0074] Insulation resistance: The insulation resistance of the manufactured multilayer ceramic chip capacitor is measured using an insulation resistance tester.

[0075] The number of oxygen vacancies in the ceramic dielectric layer of the ceramic chips prepared in Examples 1-21 and Comparative Examples 1-2, as measured by the above test method, is shown in Table 3 below. The performance data of the chip multilayer ceramic capacitors prepared in Examples 1-21 and Comparative Examples 1-2 are shown in Table 4 below.

[0076] Table 3. Number of oxygen vacancies in the ceramic dielectric layer of the ceramic chip.

[0077] As shown in Table 3, this invention controls the number of oxygen vacancies in the ceramic dielectric layer during the pre-sintering, formal sintering, and oxidation steps, and adjusts the grain size and standard deviation of the ceramic dielectric layer in the multilayer ceramic chip capacitor, thereby enabling the multilayer ceramic chip capacitor to possess high electrode continuity, high capacitance, and high insulation resistance. The number of oxygen vacancies in the multilayer ceramic chip capacitors in Examples 1-21 of this invention after pre-sintering is 8.25 × 10⁻⁶. 6 ~3.25×10 13 pcs / mm 3 After formal sintering, the number of oxygen vacancies is 9.14 × 10⁻⁶. 6~ 3.59×10 13 pcs / mm 3 The number of oxygen vacancies after oxidation is 3.02 × 10⁻⁶. 5 ~1.82×10 11 pcs / mm 3 .

[0078] Table 4. Performance characteristics of multilayer ceramic chip capacitors

[0079] As shown in Table 4, the average grain size of the ceramic dielectric layer in the chip multilayer ceramic capacitors of Examples 1 to 21 of the present invention is 264 to 685 nm, the standard deviation of the grain size is 86 to 196 nm, which has a large grain size and a relatively uniform grain size distribution. In addition, the electrode continuity of the chip multilayer ceramic capacitor is 71 to 95%, the capacitance is 0.82 to 1.64 μF, and the insulation resistance is 0.76 to 1.2 GΩ.

[0080] This invention improves the electrode continuity and capacitance of multilayer ceramic chip capacitors by introducing a pre-sintering step. In Comparative Examples 1-2, without pre-sintering, the capacitance of the resulting multilayer ceramic chip capacitors was significantly lower; even increasing the sintering time did not significantly improve the capacitance and resulted in poor electrode continuity. Compared to Examples 5, 8-9, and 13, Examples 1-4, 6-7, 10-12, and 14-21, by adjusting the parameters of the pre-sintering, formal sintering, and oxidation steps, further improve sintering activity, promote uniform grain growth, and ensure dielectric capacitance performance, without causing a deterioration in electrode continuity or a decrease in insulation resistance.

[0081] Comparing Examples 1 to 5, it can be seen that during pre-sintering, the volume percentage of hydrogen in the first reducing atmosphere affects the capacity and insulation resistance of the ceramic dielectric layer by influencing the number of oxygen vacancies. Therefore, the volume percentage of hydrogen during pre-sintering is preferably 0.3 to 2.5%.

[0082] Comparing Examples 6-10, it can be seen that during pre-sintering, the pre-sintering temperature and the pre-sintering holding time affect the capacity and insulation resistance of the ceramic dielectric layer by influencing the number of oxygen vacancies. Therefore, the pre-sintering temperature should preferably be 1000-1250℃, and the pre-sintering holding time should preferably be 1-30min.

[0083] The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A method for fabricating a multilayer ceramic chip capacitor, characterized in that: Includes the following steps: The ceramic laminated green body after debinding is heated under a first reducing atmosphere for pre-sintering and then cooled. Then, the temperature is raised under a second reducing atmosphere for formal sintering, followed by cooling. The capacitor is then subjected to oxidation treatment at a higher temperature under an oxidizing atmosphere, followed by further processing to obtain the multilayer ceramic chip capacitor. Both the first reducing atmosphere and the second reducing atmosphere contain hydrogen, and the volume percentage of hydrogen in the first reducing atmosphere is greater than the volume percentage of hydrogen in the second reducing atmosphere.

2. The method for preparing a multilayer ceramic chip capacitor according to claim 1, characterized in that: The pre-sintering step has at least one of the following characteristics: (a1) The pre-sintering temperature is 960~1300℃; (a2) The heating rate of the pre-sintering is 100~2000℃ / min; (a3) The holding time for the pre-sintering is 1~35 min.

3. The method for preparing a multilayer ceramic chip capacitor according to claim 1, characterized in that: The formal sintering step has at least one of the following characteristics: (b1) The formal sintering temperature is 1120~1350℃; (b2) The heating rate for the formal sintering is 50~2000℃ / min; (b3) The holding time for formal sintering is 0.5~30 min.

4. The method for preparing a multilayer ceramic chip capacitor according to claim 1, characterized in that: The oxidation treatment step has at least one of the following characteristics: (c1) The oxidation treatment temperature is 930~1100℃; (c2) The heating rate of the oxidation treatment is 3~50℃ / min; (c3) The holding time for the oxidation treatment is 2~6 hours; (c4) The oxygen concentration in the oxidation treatment step is 0~60ppm.

5. The method for preparing a multilayer ceramic chip capacitor according to claim 1, characterized in that: The first reducing atmosphere contains 0.3% to 3% hydrogen by volume; the second reducing atmosphere contains 0.1% to 0.3% hydrogen by volume.

6. The method for preparing a multilayer ceramic chip capacitor according to claim 1, characterized in that: The first reducing atmosphere, the second reducing atmosphere, and the oxidizing atmosphere all contain water vapor and protective gases; And / or, the first reducing atmosphere, the second reducing atmosphere, and the oxidizing atmosphere each contain 3 to 11% water vapor by volume.

7. The method for preparing a multilayer ceramic chip capacitor according to claim 1, characterized in that: The ceramic laminate green body after debinding is prepared by a method including the following steps: The ceramic slurry is cast into a film to obtain a ceramic dielectric layer; An internal electrode paste is printed on the ceramic dielectric layer to obtain a ceramic dielectric layer containing an internal electrode layer. After stacking, pressing, and cutting the ceramic dielectric layer containing the inner electrode layer, a ceramic laminate green body is obtained. The binder is removed from the ceramic laminate green body to obtain the binder-removed ceramic laminate green body.

8. The method for preparing a multilayer ceramic chip capacitor according to claim 7, characterized in that: After pre-sintering, the oxygen vacancy content of the ceramic dielectric layer is 8.25 × 10⁻⁶. 6 ~3.25×10 13 pcs / mm 3 ; And / or, after formal sintering, the oxygen vacancy content of the ceramic dielectric layer is 9.14 × 10⁻⁶. 6~ 3.59×10 13 pcs / mm 3 ; And / or, after oxidation treatment, the oxygen vacancy content of the ceramic dielectric layer is 3.02 × 10⁻⁶. 5 ~1.82×10 11 pcs / mm 3 .

9. A multilayer ceramic chip capacitor, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 8.

10. The application of the preparation method according to any one of claims 1 to 8 or the chip multilayer ceramic capacitor according to claim 9 in the field of electronic devices.

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