A source type, drain type switch quantity protection circuit and system

Abstract

A source type, drain type switch quantity protection circuit and system, comprising: a series connection of PMOS tube Q4, resistor R1, PMOS tube Q2; resistor R13 and resistor R12; a voltage drop control unit; the output end of comparator U10B is connected between resistor R2 and resistor R9 through resistor R3, the gate of PMOS tube Q4 is connected between resistor R2 and resistor R9; the gate of PMOS tube Q2 is connected with the collector of NPN type triode Q6, wherein the base of triode Q6 is connected with the output end of controllable logic gate U1A; and the input end of controllable logic gate U1A is used for receiving a first voltage signal, and the enable end is used for receiving an enable signal output by the output end of comparator U8B; wherein the positive electrode of comparator U8B is connected with reference voltage Vref1, and the other end is connected between resistor R13 and resistor R12, thereby improving the reliability of the switch quantity output channel.

Description

Technical Field

[0001] This article relates to electronic circuit technology, particularly a source-type and sink-type switching quantity protection circuit and system. Background Technology

[0002] In industrial automation control systems, switching signals are frequently used to control and drive equipment, making the protection of these signals crucial. The most important aspect of port protection for switching signals is preventing short circuits at output ports. Industrial production lines require extremely continuous operation; a short circuit at a single port can paralyze the entire control system, potentially causing significant economic losses and serious personal injury. Therefore, short-circuit protection for switching outputs is a key element in ensuring normal equipment operation and improving system reliability.

[0003] Currently, relevant port short-circuit protection solutions mainly rely on adding fuses. However, due to manufacturing limitations of fuses, this solution suffers from drawbacks such as large size, large trip current tolerance, and slow response time. The response time of conventional fuses is typically between milliseconds and seconds, which is insufficient to quickly cut off power to downstream load devices, potentially causing serious damage. Furthermore, this solution cannot provide a clear and effective alarm, making on-site troubleshooting difficult and hindering timely corrective action. Summary of the Invention

[0004] This application provides a source-type and sink-type switch quantity protection circuit and system.

[0005] A source-type switching quantity protection circuit, comprising: A PMOS transistor Q4, a resistor R1, and a PMOS transistor Q2 are connected in series, with PMOS transistor Q4 connected to the power supply V0 and the drain of PMOS transistor Q3 connected to the source load. One end of resistor R13 is connected between resistor R1 and the source of PMOS transistor Q2, and the other end is grounded through resistor R12; One end of resistor R2 is connected to power supply V0, and the other end is grounded through resistor R9; The voltage drop control unit has its positive terminal connected to the gate of PMOS transistor Q2 and its negative terminal connected to resistor R1 and the source of PMOS transistor Q2. The voltage drop control unit is used to provide a bias voltage to the gate of PMOS transistor Q2 when a source-type load is short-circuited, so that PMOS transistor Q2 operates in the linear region. The non-inverting input of comparator U10B is connected to the reference voltage Vref1, the negative input is connected between resistors R13 and R12, and the output is connected between resistors R2 and R9 via resistor R3. The gate of PMOS transistor Q4 is connected between resistors R2 and R9; The gate of PMOS transistor Q2 is connected to the collector of NPN transistor Q6. The base of transistor Q6 is connected to the output of controllable logic gate U1A through resistor R6, and the emitter is grounded. One end of resistor R10 is connected between the base of transistor Q6 and resistor R6, and the other end is grounded. The input terminal of the controllable logic gate U1A is used to receive the first voltage signal, and the enable terminal is used to receive the enable signal output by the output terminal of the comparator U8B. The positive terminal of the comparator U8B is connected to the reference voltage Vref1, and the other end is connected between resistor R13 and resistor R12.

[0006] A leakage-type switch quantity protection circuit, comprising: The NMOS transistor Q3, resistor R22, and NMOS transistor Q1 are connected in series, with the drain of NMOS transistor Q3 connected to the power supply V0 through a drain load, and the source of NMOS transistor Q1 grounded. One end of resistor R21 is connected between resistor R22 and the drain of NMOS transistor Q1, and the other end is grounded through resistor R20; Comparator U6A has its positive input connected to the reference voltage Vref2, its negative input connected between resistors R21 and R20, its output connected between resistors R2 and R9 via resistor R3, and its output connected to one end of resistors R28 and R19 in sequence. One end of resistor R27 is connected to the power supply VCC, and the other end is connected to the other end of resistor R19; The gate of NMOS transistor Q1 is connected between resistors R27 and R19; The gate of NMOS transistor Q3 is connected to the output of controllable logic gate U5A through resistor R30, wherein: The input terminal of the controllable logic gate U5A is used to receive the second voltage signal. The enable terminal is connected to the output terminal of the comparator U3A through the resistor R11. The positive input terminal of the comparator U3A is connected between the resistors R21 and R20, and the negative input terminal is connected to the reference voltage Vref2.

[0007] A digital input protection system includes the source-type digital input protection circuit and the sink-type digital input protection circuit described above.

[0008] This application provides a protection circuit with high reliability and fast response speed, which is suitable for switch output channels in the industrial control industry and can effectively improve the reliability of the circuit.

[0009] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0011] Figure 1 This is a schematic diagram of the source-type switch quantity protection circuit provided in the embodiments of this application; Figure 2 for Figure 1 Another schematic diagram of the circuit shown; Figure 3 This is a schematic diagram of the structure of the leakage-type switch quantity protection circuit provided in the embodiments of this application; Figure 4 for Figure 3 Another schematic diagram of the circuit shown; Figure 5 This is a schematic diagram of the structure of the switch quantity protection system provided in the embodiment of this application. Detailed Implementation

[0012] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0013] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0014] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0015] Figure 1 This is a schematic diagram of the source-type switch quantity protection circuit provided in an embodiment of this application. Figure 1 As shown, the circuit is used in industrial automation control systems to provide short-circuit protection for source output channels (such as PLC source output points).

[0016] The source-type switch protection circuit includes: A source-type output channel includes a PMOS transistor Q4, a sampling resistor R1 (preferably with a resistance of 1Ω), and a PMOS transistor Q2 connected in series. The source of the PMOS transistor Q4 is connected to the power supply V0, and its drain is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the source of the PMOS transistor Q2. The drain of the PMOS transistor Q2 serves as the output terminal of the circuit and is connected to the source-type load.

[0017] A voltage divider sampling network includes a resistor R13 (preferably 470kΩ) and a resistor R12 (preferably 75kΩ) connected in series. One end of resistor R13 is connected to the node between the sampling resistor R1 and the source of the PMOS transistor Q2, and the other end is connected to resistor R12. The other end of resistor R12 is grounded. This voltage divider sampling network is used to sample the voltage drop across R1 caused by the load current.

[0018] A bias network includes a series resistor R2 (preferably 24kΩ) and a resistor R9 (preferably 330kΩ). One end of resistor R2 is connected to the power supply V0, and the other end is connected to resistor R9; the other end of resistor R9 is grounded.

[0019] A voltage drop control unit is provided, with its positive terminal connected to the gate of PMOS transistor Q2 and its negative terminal connected to the source of PMOS transistor Q2 (i.e., the node between resistor R1 and PMOS transistor Q2). The voltage drop control unit is used to provide a bias voltage to the gate of PMOS transistor Q2 when a source-type load is short-circuited, so that PMOS transistor Q2 operates in the linear region.

[0020] A comparator U10B (e.g., an open-drain output LM393) has its positive input connected to a reference voltage Vref1 (e.g., 0.83V); its negative input connected to the node between resistors R13 and R12 in the voltage divider sampling network; and its output connected to the node between resistors R2 and R9 in the bias network via a resistor R3 (preferably 24kΩ).

[0021] The gate of PMOS transistor Q4 is directly connected to the node between resistors R2 and R9 in the bias network.

[0022] The gate of PMOS transistor Q2 is connected to the collector of NPN transistor Q6; the base of transistor Q6 is connected to the output of a controllable logic gate U1A (as a control signal drive unit) through a resistor R6 (preferably with a resistance of 2kΩ); the emitter of transistor Q6 is grounded; a pull-down resistor R10 (preferably with a resistance of 10kΩ) is connected between the base of transistor Q6 and ground to ensure that the base is reliably turned off when there is no input.

[0023] The input terminal of the controllable logic gate U1A is used to receive the first external voltage signal; its enable terminal is used to receive the enable signal output by the output terminal of another comparator U8B; the positive input terminal of the comparator U8B is connected to the reference voltage Vref1, and its negative input terminal is also connected to the node between resistor R13 and resistor R12 in the voltage divider sampling network.

[0024] Figure 1 The working mechanism of the circuit shown can be explained in three stages: normal operation, abnormal protection, and fault recovery. I. Normal working status Initial conduction phase: The first voltage signal outputs a high level through the controllable logic gate U1A, turning on the NPN transistor Q6, which in turn pulls the gate of the PMOS transistor Q2 low to near ground potential. At this time, the V of the PMOS transistor Q2... GS The gate-source voltage is much smaller than its threshold voltage V. TH (Negative value) PMOS transistor Q2 is in a fully conducting state with extremely low impedance.

[0025] Meanwhile, since the load has not yet fully established voltage, the voltage at the negative input terminal of comparator U10B is low, and comparator U10B outputs a high level (open-drain output, equivalent to being off). At this time, the voltage is divided by resistors R2 and R9, resulting in a high gate voltage (close to V0) for PMOS transistor Q4. GS With a relatively small absolute value, PMOS transistor Q4 operates in the linear region (not fully turned on), thus providing initial current limiting.

[0026] Stable employment phase: As PMOS transistor Q2 turns on, the load voltage rises, and current flows through resistors R1, R13, and R12 to form a voltage divider.

[0027] When the voltage at the connection point of resistors R13 and R12 exceeds the reference voltage Vref1, comparator U10B outputs a low level (equivalent to the lower end of resistor R3 being grounded).

[0028] At this point, resistors R2, R3, and R9 form a new voltage divider network, causing the gate voltage of PMOS transistor Q4 to drop, and the Vo of PMOS transistor Q4 to decrease. GS As the absolute value increases, PMOS transistor Q4 enters a fully conducting state with extremely low impedance, allowing the load to obtain a voltage close to the power supply V0.

[0029] by Figure 1 The preferred resistance value of the resistor in the structure shown is used as an example for explanation: The external control system issues a turn-on command, with the first voltage signal being high, making the output of the controllable logic gate U1A valid (high level). This signal drives the NPN transistor Q6 to saturate and conduct through resistor R6, thereby pulling the gate voltage of the PMOS transistor Q2 down to near ground potential. At this time, the gate-source voltage V of the PMOS transistor Q2... GS The value is a large negative value, much smaller than its threshold voltage (e.g., -3V), so the PMOS transistor Q2 is in a low-resistance on state.

[0030] Upon initial power-up, since the load current has not yet been established, the voltage at the sampling point (between R13 and R12) is low, lower than the reference voltage Vref1, causing comparator U10B to output a high level (effectively disconnected due to its open-drain output). At this time, the power supply V0 is divided by resistors R2 and R9. Because R9 (330kΩ) >> R2 (24kΩ), the gate voltage of PMOS transistor Q4 is high (e.g., approximately 22.4V). The source voltage of PMOS transistor Q4 is approximately V0 (24V), and its gate-source voltage V0... GS (Q4) is approximately -1.6V. For a typical PMOS transistor (such as FDN360P, Vth ≈ -1V ~ -3V), this V... GS The absolute value of the current is insufficient to enable it to conduct fully. PMOS transistor Q4 operates in the linear region and exhibits a certain resistance, which, together with resistor R1, serves as an initial current limiter.

[0031] As PMOS transistor Q2 turns on, a current is established in the load circuit, creating a voltage drop across sampling resistor R1, causing the voltage at the sampling point (between R13 and R12) to rise. When this voltage exceeds the reference voltage Vref1, the comparator U10B output flips to a low level (equivalent to grounding its output through the internal MOS transistor). At this time, resistors R3 and R9 form a parallel connection, which, together with resistor R2, divides the voltage, significantly reducing the gate voltage of PMOS transistor Q4 (e.g., dropping it to approximately 12V). This causes the Vref1 of PMOS transistor Q4 to... GS When the absolute value increases (for example, to approximately -12V), which is much smaller than its threshold voltage, the PMOS transistor Q4 enters a low-resistance saturation conduction state. At this time, the power supply V0 can be applied to the load with almost no loss, and the circuit enters a normal low-power operating state.

[0032] Under normal conditions, the sampling point voltage is always higher than the reference voltage Vref1. Therefore, the enable signal output by comparator U8B is low, which does not shield the controllable logic gate U1A, and the control signal is unimpeded. The voltage drop control unit is reverse-biased and does not function because the gate of PMOS transistor Q2 is low.

[0033] II. Abnormal Protection Status If a source-type load experiences a short circuit to ground, the load-side voltage drops sharply to zero. A huge short-circuit current flows through the sampling resistor R1, but the voltage drop across it is also pulled to an extremely low level due to the short circuit. This causes the voltage at the sampling point between resistors R13 and R12 to drop rapidly to a level far below the reference voltage Vref1.

[0034] This change triggers a dual protection mechanism: First layer of protection (PMOS transistor Q4 current limiting): The voltage drop at the sampling point causes the voltage at the negative input terminal of comparator U10B to be lower than that at the positive input terminal, and the output of comparator U10B immediately flips to a high level (equivalent to being disconnected). At this time, the bias network reverts to the voltage divider between resistors R2 and R9, and the gate voltage of PMOS transistor Q4 is pulled high again, causing its V... GS As the absolute value decreases, it exits the saturation region and re-enters the high-resistance linear operating region, thereby greatly limiting the magnitude of the short-circuit current.

[0035] Second layer of protection (Q2 current limiting and signal shielding): The drop in sampling point voltage also causes the enable signal output by comparator U8B to flip to a high level. This high-level signal is sent to the enable terminal of controllable logic gate U1A, disabling or shielding it, causing its output to be invalid, and transistor Q6 to turn off. The gate of PMOS transistor Q2 is no longer pulled low, but is pulled high through the voltage drop control unit. At this time, the V of PMOS transistor Q2... GS When the current approaches zero and is much greater than its threshold voltage (negative value), the PMOS transistor Q2 also enters the linear region (high resistance state), further limiting the current.

[0036] III. Fault Recovery Status Once the short-circuit fault is cleared, the load circuit is restored. The sampling point voltage then rises back above the reference voltage Vref1, and the output states of comparators U10B and U8B automatically flip back to their normal operating states. The enable signal output by comparator U8B is low, releasing the shielding of the controllable logic gate U1A; the output of comparator U10B is low, fully turning on PMOS transistor Q4 again. The circuit automatically resumes normal operation without any software intervention or external reset.

[0037] The circuit provided in this application embodiment improves circuit reliability by limiting current through PMOS transistors Q4 and Q2 respectively; and the circuit automatically resumes normal operation after the short circuit is removed, without the need for software intervention.

[0038] The following explains the resistance constraints for resistors R2, R9, and R13: The core purpose of this constraint is to ensure that the gate-source voltage V of PMOS transistor Q4 is maintained under both normal operation and short-circuit protection conditions. GS It can undergo a decisive change, thus reliably switching between the two states of "fully on" and "high-resistance current limiting".

[0039] 1. The resistance constraints between resistors R2 and R9: The constraint stems from the control of the operating state of PMOS transistor Q4, whose conduction condition is V. GS < V TH (where V) TH (Negative value).

[0040] Normal operating state (comparator U10B outputs low level): The comparator U10B output is equivalent to ground. Resistors R3 and R9 are connected in parallel, and the total parallel resistance R_parallel is much smaller than R9.

[0041] The gate voltage V of PMOS transistor Q4 G (Q4) The voltage is determined by the voltage division between resistor R2 and the total parallel resistance R_parallel. This voltage must be ensured during the design process. G (Q4) Low enough that V GS (Q4) = V G (Q4) - V S (Q4) ≈ V G (Q4) - V0 becomes a very large negative value (e.g., -12V), much smaller than the threshold voltage V of the PMOS transistor Q4. TH(e.g., -2.5V), thus ensuring that the PMOS transistor Q4 is fully turned on, and the on-resistance R_DS(ON) is extremely small.

[0042] Constraint: The resistance values ​​of resistors R2 and R9 (considering the parallel effect of R3) must satisfy |V GS (Q4)_normal| >> |V TH |

[0043] Short circuit protection status (comparator U10B outputs high level): At this time, comparator U10B outputs high impedance (disconnected), and the total parallel resistance R_parallel is invalid. The gate voltage V of PMOS transistor Q4... G (Q4) is determined by the voltage divider formed by resistors R2 and R9. In this state, V... GS The absolute value of (Q4) decreases and becomes greater than V. TH The absolute value (i.e., V) GS If the low-resistance conduction condition is not met, the PMOS transistor Q4 is forced to exit the saturation region and enter the linear region to limit the current.

[0044] Calculation example: Let V0 = 24V, V TH (Q4) = -2.5V. For reliable shutdown, V is required. GS (Q4) > V TH .

[0045] For example, designing V GS (Q4)_protect ≈ -1.6V, then V G (Q4)_protect = V S (Q4) + V GS (Q4)_protect ≈ 24V + (-1.6V) = 22.4V.

[0046] According to the principle of voltage division: V G (Q4)_protect = V0 * [R9 / (R2 + R9)] = 24V * [R9 / (R2+ R9)] = 22.4V.

[0047] Solving for R, we get: R2 / R9 ≈ (24 - 22.4) / 22.4 ≈ 1.6 / 22.4 ≈ 1 / 14.

[0048] Therefore, the resistance of resistor R2 should be much smaller than that of resistor R9 (e.g., 24kΩ vs. 330kΩ in the embodiment, a ratio of approximately 1:13.75) to satisfy the voltage division relationship described above. This is crucial to ensuring the effectiveness of the first layer of protection.

[0049] 2. The resistance values ​​of resistors R13 and R12 are subject to constraint. The constraints are derived from the setting of the sampling voltage and need to be used in conjunction with the reference voltage Vref1 to set the overcurrent point I_trip.

[0050] Function: Resistors R13 and R12 divide the voltage drop V_R1 across resistor R1 to obtain the voltage V_sense sent to the negative input terminal of comparator U10B / U8B.

[0051] Relationship: V_sense = V_R1 * [R12 / (R13 + R12)] = (I_load * R1) * [R12 / (R13 + R12)] Overcurrent point setting: When I_load reaches the set overcurrent point I_trip, set V_sense = Vref1.

[0052] Therefore, Vref1 = (I_trip * R1) * [R12 / (R13 + R12)] Constraints: The resistance ratio of resistors R13 and R12, R12 / (R13 + R12), must match Vref1, resistor R1, and the required I_trip.

[0053] Calculation example: Let I_trip = 0.1A, R1 = 1Ω, Vref1 = 0.83V.

[0054] 0.83V = (0.1A * 1Ω) * K, which gives a voltage divider coefficient K = 8.3. This is clearly unreasonable (K should be less than 1), indicating that the assumed values ​​for I_trip or R1 may not be applicable to this circuit. A more reasonable I_trip value would likely be in the several ampere range.

[0055] Let I_trip = 4A, R1 = 1Ω, Vref1 = 0.83V.

[0056] 0.83V = (4A * 1Ω) * K, so K = 0.83 / 4 ≈ 0.2075.

[0057] That is, R12 / (R13 + R12) ≈ 0.2075. Choosing R12 = 75kΩ, then 0.2075 = 75kΩ / (R13 + 75kΩ), solving for R13 gives ≈ 286kΩ. In this embodiment, 470kΩ is preferred, which means that the actual I_trip or Vref1 needs to be adjusted accordingly. This indicates that the values ​​of resistors R13, R12, R1, and the reference voltage Vref1 are a complex system engineering decision requiring comprehensive consideration, but the mathematical constraints between them are clear and must be followed.

[0058] As can be seen from the above analysis, the ratio of resistors R2 and R9 determines the switching state of PMOS transistor Q4; the ratio of resistors R13 and R12, together with resistor R1 and reference voltage Vref1, determines the overcurrent protection trigger point of the circuit.

[0059] In this circuit, resistor R6 is connected in series between the output of the controllable logic gate U1A and the base of the NPN transistor Q6. Its main functions are current limiting and buffering. Detailed explanation follows: Limiting Base Current: The base-emitter junction of transistor Q6 is a PN junction with a forward voltage of approximately 0.7V. Without resistor R6, a very large transient base current would be generated when the controllable logic gate U1A outputs a high level (e.g., 5V or 3.3V). This current could exceed the maximum output current capability of the controllable logic gate U1A and even damage the base of transistor Q6. The presence of resistor R6 effectively limits the maximum current flowing into the base of transistor Q6: I_B ≈ (V_U1A_out - V_BE) / R6.

[0060] Suppressing Oscillations and Slowing Down Switching Speed: The base of a transistor has a parasitic capacitance. Resistor R6 and this parasitic capacitance form an RC circuit, which helps slow down the turn-on and turn-off speeds of transistor Q6. Although this slightly increases switching losses, it effectively suppresses high-frequency oscillations or ringing that may be caused by fast switching and line inductance, improving the circuit's electromagnetic compatibility (EMC) and stability.

[0061] Provides isolation: It isolates the output stage of the controllable logic gate U1A from the capacitive load that may exist at the base of the transistor Q6 to a certain extent, thus protecting the controllable logic gate.

[0062] Resistor R10 is connected between the base of NPN transistor Q6 and ground, and its main function is to act as a pull-down resistor to ensure deterministic turn-off. Detailed explanation follows: Ensuring reliable shutdown: When the controllable logic gate U1A outputs a low level (0V) or is in a high-impedance state, the base of transistor Q6 is forcibly pulled low to ground potential (0V) through resistor R10. This provides a clear discharge path for the base charge, ensuring that transistor Q6 can be quickly and completely turned off.

[0063] Improving anti-interference capability: Without resistor R10, the base of transistor Q6 is in a floating or high-impedance state, making it highly susceptible to external noise, electromagnetic interference, or PCB leakage current, which may cause transistor Q6 to mis-turn on. Resistor R10 reduces the impedance at this point, greatly enhancing the circuit's anti-interference capability and ensuring that transistor Q6 is always in a definite off state when there is no effective voltage signal.

[0064] Define the default state: Together with resistor R6, it determines the base voltage of the controllable logic gate U1A when the output impedance is high, thus clarifying that the default state of the circuit is off.

[0065] Figure 2 for Figure 1 Another schematic diagram of the circuit shown. (See diagram below.) Figure 2 As shown, it demonstrates the... Figure 1 The improvements or optimizations to the circuit shown are noteworthy.

[0066] In one exemplary embodiment, a specific implementation of the voltage drop control unit is defined.

[0067] The voltage drop control unit consists of a resistor R14 (preferably with a resistance of 24kΩ) and a Zener diode D1 (preferably with a Zener voltage of 1V) connected in series. The resistor R14 is connected to the gate of the PMOS transistor Q2, and the cathode of the Zener diode D1 is connected to the gate of the PMOS transistor Q2, while the anode is connected to the source of the PMOS transistor Q2.

[0068] I. Normal working status When the output of the controllable logic gate U1A is valid, it drives the transistor Q6 to conduct.

[0069] The collector of NPN transistor Q6 (i.e. the gate of PMOS transistor Q2) is pulled down to near ground potential (0V).

[0070] At this time, since the source voltage of PMOS transistor Q2 is positive (because current flows through resistor R1), the gate-source voltage V of PMOS transistor Q2 is... GS It is a large negative value (e.g., above -10V), much smaller than its threshold voltage V. TH (e.g., -2V), so PMOS transistor Q2 is fully turned on.

[0071] In this state, the Zener diode D1 and resistor R14 branch are almost ineffective. Because the gate voltage (0V) of PMOS transistor Q2 is much lower than the cathode voltage of Zener diode D1 (the source voltage of PMOS transistor Q2 minus the Zener voltage of Zener diode D1), Zener diode D1 is in reverse cutoff, and this branch is equivalent to being open.

[0072] II. Abnormal Protection Status After a short circuit occurs in the source load, the enable signal output by comparator U8B is high, which shields the controllable logic gate U1A, causing the NPN transistor Q6 to be cut off.

[0073] After the NPN transistor Q6 is turned off, its collector presents a high impedance state and no longer pulls the gate of the PMOS transistor Q2 low. At this time, the source voltage VS of the PMOS transistor Q2 will flow through resistor R14 to the gate (V) of the PMOS transistor Q2. G )Charge.

[0074] When the V of PMOS transistor Q2 G The voltage rises to a level lower than the source voltage VS of PMOS transistor Q2 by the regulated voltage V of D1. Z At a voltage of 1V (for example), the Zener diode D1 breaks down and enters the Zener operating region, thereby reducing the voltage of the PMOS transistor Q2. GS The clamp is within a preset range (approximately -1V), this V GS The absolute value of (-1V) is less than the V required for Q2 to be fully turned on. GS The absolute value, but greater than its threshold voltage V TH The absolute value of (-2V), i.e., |V TH | > | V GS |. In this V GS Under certain conditions, PMOS transistor Q2 will exit the saturation region and enter the linear region (resistive region), and its on-resistance R_DS(on) will become very large, thereby effectively limiting the short-circuit current and playing a second protection role.

[0075] III. Fault Recovery Status Once the short-circuit fault is cleared and the load circuit is restored, the sampling point voltage rises back to above the reference voltage Vref1, and the output states of comparators U10B and U8B automatically flip back to their normal operating states.

[0076] In the exemplary embodiment described above, the voltage drop control unit is a fault-activated clamping circuit. It sleeps during normal operation and activates when the control signal fails. It uses a Zener diode to precisely control the gate-source voltage of the PMOS transistor Q2 to a value that allows it to operate in the high-impedance linear region, thereby achieving reliable current-limiting protection.

[0077] The following is a detailed supplementary explanation of the reasons for deploying the Zener diode D1 and the resistance constraint conditions of resistor R14: Under short-circuit fault conditions, the controllable logic gate U1A is shielded, and transistor Q6 is turned off. At this time, the gate of PMOS transistor Q2 is in a floating (high impedance) state. If no measures are taken, the gate potential of PMOS transistor Q2 will become uncertain due to various factors (such as leakage current and noise), which may lead to it being fully turned on or completely turned off. Neither of these states can achieve the purpose of current limiting protection.

[0078] The core reason for deploying the Zener diode D1 is precisely to solve this problem, and its specific function is as follows: 1. Provide a defined bias voltage (core function): In the protection state, the source voltage (V) of PMOS transistor Q2 S It will charge the gate through resistor R14.

[0079] When the gate voltage (V G The voltage rises to a level lower than the source voltage by the stable breakdown voltage V of the Zener diode D1. Z Time (i.e., V) GS ≈ -V Z The Zener diode D1 is reverse-biased and enters the Zener operating region.

[0080] The breakdown characteristic of Zener diode D1 will reduce the gate-source voltage V of Q2. GS Precisely clamped to a stable, known, and controllable value, approximately -V. Z For example, choose V. Z A Zener diode with a voltage of 1V can regulate the voltage of Q2. GS The clamp is at approximately -1V.

[0081] 2. Force PMOS transistor Q2 to operate in the linear region (to achieve the objective): Choose the Zener diode D1's Zener voltage value V Z This makes the V after clamping GS Satisfy: |V TH (Q2)| > |V GS | > 0 (where V) TH (Negative value).

[0082] Example: Let the threshold voltage V of PMOS transistor Q2 be... TH = -2V, V of D1 Z = 1V, then V GS = -1V.

[0083] Due to |V GS | (1V) < |VTH | (2V), PMOS transistor Q2 cannot enter saturation conduction state (saturation conduction requires |V) GS | > |V TH |).

[0084] At the same time, due to V GS If the voltage is not zero and its absolute value is greater than zero (-1V), the PMOS transistor Q2 will not be completely turned off.

[0085] Under these conditions, PMOS transistor Q2 is forced to operate in the linear region of its output characteristics (or the transistor region, variable resistance region). Within this region, PMOS transistor Q2 behaves as a transistor whose resistance varies with V. GS The variable resistor is controlled. At this time, V GS The absolute value of the resistance is relatively small, so the on-resistance R_DS(ON) of PMOS transistor Q2 is very large (it may be in the ohm or even kiloohm range), which effectively limits the short-circuit current and achieves a second layer of smooth hardware current limiting protection.

[0086] 3. Difference from a simple pull-down resistor: If only one large resistor is used to pull the gate of PMOS transistor Q2 to ground, V GS Approximately equal to -V S During a short circuit, V S It may vary within a wide range, leading to unstable rate limiting effects.

[0087] The clamping effect of the Zener diode D1 makes V GS In the protected state, it is a fixed value, which is related to the source voltage V. S Irrelevant (as long as V) S > V Z This ensures the consistency and predictability of the flow restriction behavior, greatly improving the reliability of the protection.

[0088] The reason for deploying D1 is to provide a stable and precise bias voltage to the gate of PMOS transistor Q2 after the control signal fails, rather than an uncertain floating or coarse voltage, thereby forcing and reliably making it work in a linear high-impedance state, and achieving a stable and designable current limiting function.

[0089] Resistor R14 is not a simple current-limiting resistor in this unit; its resistance value needs to be carefully calculated and must simultaneously meet the following constraints: 1. Provide sufficient gate drive current (lower limit constraint – resistance value cannot be too large): Function: Resistor R14 forms the gate charging path. At the moment a fault occurs and transistor Q6 is turned off, the gate capacitance of Q2 needs to be charged through R14 to establish a protective VC. GS Voltage.

[0090] Constraint: The value of resistor R14 must be small enough to ensure that the gate voltage settling time (Time ≈ R14 * C_iss(Q2), where C_iss is the input capacitance of PMOS transistor Q2) is much shorter than the time it would take for a short circuit to cause damage (typically in the microsecond range). If R14 is too large, the response will be too slow, and the protection may fail.

[0091] Therefore, based on the above calculation expression, we know that R14 << T_max / C_iss(Q2) (T_max is the maximum allowable response time). 2. Limit the current of the Zener diode D1 (core constraint – resistance value cannot be too small): Function: The core function of resistor R14 is to limit the current I_D1 flowing through Zener diode D1.

[0092] Constraint: I_D1 must be limited to the minimum stable operating current I of the Zener diode D1. ZK and maximum rated power consumption P ZMAX between.

[0093] To ensure voltage regulation: I_D1 must be greater than I. ZK Otherwise, D1 cannot enter a good voltage regulation range, and the clamping voltage will be inaccurate.

[0094] To prevent burnout: I_D1 must satisfy I_D1 < P ZMAX / V Z .

[0095] Calculation expression: I_D1 ≈ (V S - V Z ) / R14.

[0096] Therefore, the value of R14 must satisfy: (V S - V Z ) / I ZK > R14 > (V S - V Z ) * V Z / P ZMAX .

[0097] For example: Assume V is short-circuited. S ≈ 5V, D1 parameter is V Z =1V, IZK =0.5mA, P ZMAX =500mW.

[0098] R14 < (5V - 1V) / 0.0005A = 8 kΩ (upper limit resistance value to ensure voltage regulation); R14 > (5V - 1V) * 1V / 0.5W = 8Ω (lower limit of resistance value to prevent burnout).

[0099] As can be seen, the lower limit for preventing burnout is very low; typically, ensuring the minimum current required for voltage regulation (i.e., the upper limit of resistance) is a more stringent constraint. The 24kΩ chosen in the example may be too large; it is necessary to ensure that at the lowest possible voltage... S It can also satisfy I_D1 > I ZK This could mean that the I selected for D1 in the design. ZK Very small (e.g., uA level), or V at this point S Relatively high.

[0100] 3. Does not affect normal working efficiency (secondary constraint): Function: During normal operation, transistor Q6 is turned on, and the gate of PMOS transistor Q2 is pulled low to near ground potential. At this time, the anode voltage of D1 (source voltage of Q2) is high, and D1 is reverse-biased and cut off.

[0101] Constraint: The resistance of resistor R14 needs to be large enough to ensure that, during normal operation, the leakage current I_R14 through resistor R14 and Zener diode D1 is very small (I_R14 ≈ V). S / R14), so small that it will not significantly affect the current sinking capability of transistor Q6, nor will it generate unnecessary power consumption.

[0102] Overall design trade-offs: The final selection of the R14 resistance value was a compromise between response speed, D1 operating current requirements, and leakage current under normal conditions.

[0103] The primary constraint is to satisfy the voltage regulation condition of D1 (I_D1 > I). ZK Then check whether its response speed meets the protection requirements, and finally confirm whether the normal leakage current is acceptable.

[0104] The 24kΩ given in the example is a reasonable preferred value. It means that the designer prioritized lower static leakage current and power dissipation, and selected an IL... ZK A very small Zener diode (or V at this time) S (Higher), to ensure that even in the protection state, there is still a small current to allow D1 to enter the regulated state.

[0105] In an exemplary embodiment, the circuit further includes: a resistor R7 (10kΩ), one end of which is connected to the power supply VCC and the other end of which is connected to the output terminal of the comparator U8B, wherein the connection point between the resistor R7 and the output terminal of the comparator U8B serves as the sampling point of the source-type diagnostic signal, wherein the source-type diagnostic signal is used to indicate whether a short circuit has occurred in the source-type load.

[0106] In the above exemplary embodiment, a hardware diagnostic circuit is added to report the short-circuit fault status to the upper-level control system (such as MCU).

[0107] I. Normal working status Under normal conditions, the voltage at the sampling point (between resistors R13 and R12) is high, higher than the reference voltage Vref1. This causes the enable signal output by comparator U8B to be low (because the reference voltage Vref1 at its positive input is lower than the voltage at its negative input).

[0108] Because the enable signal output by comparator U8B is low, it forcibly pulls the diagnostic signal sampling point down to near 0V. Therefore, the source-type diagnostic signal read by the control system is low (0V), indicating "channel normal, no short circuit".

[0109] II. Abnormal Protection Status When the load is short-circuited to ground, the voltage at the sampling point (between resistors R13 and R12) drops sharply to near 0V, below the reference voltage Vref1. Comparator U8B flips, and its output becomes high-impedance (because comparator U8B is an open-drain output, such as LM393, a high output is equivalent to being off). At this time, the power supply VCC (e.g., 3.3V or 5V) is applied to the diagnostic signal sampling point through pull-up resistor R7 (10kΩ). Therefore, the voltage at the sampling point is pulled high (VCC) by resistor R7.

[0110] The source-type diagnostic signal read by the control system is high level (VCC), which is a clear "source-type load short circuit" alarm signal.

[0111] III. Fault Recovery Status Once the short-circuit fault is cleared, the load circuit is restored. The sampling point voltage then rises back to above the reference voltage Vref1, and the output states of comparators U10B and U8B automatically flip back to their normal operating states.

[0112] In the above exemplary embodiment, the logic state of the open-drain output comparator U8B is converted into a level signal (0V or VCC) that can be recognized by the MCU through a simple pull-up resistor (resistor R7), realizing the hardware-level real-time fault diagnosis and reporting function without the need for software to participate in the judgment, with fast response speed and high reliability.

[0113] In one exemplary embodiment, a simple yet important reference voltage generation circuit is designed to provide a stable decision reference (reference voltage Vref1) for comparators U10B and U8B.

[0114] Circuit structure: Resistors R4 and R5 form a classic voltage divider circuit. The power supply VCC (usually a stable system power supply, such as 5V or 3.3V) serves as the input.

[0115] Voltage Calculation: According to the voltage divider principle, the value of the reference voltage Vref1 is determined by the following expression: Vref1 = VCC * [R5 / (R4 + R5)]; For example, with R4=10kΩ and R5=2kΩ, Vref1 ≈ VCC * (2k / (10k + 2k)) = VCC * (1 / 6); If VCC = 5V, then Vref1 ≈ 0.83V.

[0116] This fixed Vref1 voltage value is the benchmark threshold for judging whether the voltage drop across resistor R1 is too large.

[0117] Comparators U10B and U8B compare the sampled load current signal (converted to a voltage signal) with Vref1, where: When the sampled voltage is higher than the reference voltage Vref1, the current is considered normal.

[0118] When the sampled voltage is lower than the reference voltage Vref1 (due to a short circuit causing the voltage at the sampling point to be pulled down), a short circuit is considered to have occurred, triggering the protection action.

[0119] The design advantages of the above scheme include: Stability: The power supply VCC is usually regulated, so the resulting Vref1 is also very stable and is not affected by fluctuations in the field power supply V0 (24V).

[0120] Adjustability: By changing the ratio of the resistance values ​​of resistors R4 and R5, the overcurrent trigger point of the protection circuit can be easily adjusted to adapt to the overcurrent protection requirements of different loads, demonstrating the flexibility of the circuit.

[0121] In the exemplary embodiments described above, what is provided is not a "working" circuit, but a reference source circuit. It provides a stable and settable voltage reference for the entire protection system, serving as a "ruler" for determining whether the circuit should enter the protection state, and is the basis for the accurate implementation of the protection function.

[0122] Figure 3This is a schematic diagram of the structure of a leakage-type switch quantity protection circuit provided in an embodiment of this application. Figure 3 As shown, the circuit is used in industrial automation control systems to provide short-circuit protection for sinking output channels (such as sinking output points of PLCs). This circuit is a complementary and symmetrical implementation of the source-type switching quantity protection circuit in this embodiment.

[0123] Figure 3 The leakage-type switch protection circuit shown includes: A drain-type output channel includes an NMOS transistor Q3, a sampling resistor R22 (preferably 1Ω), and an NMOS transistor Q1 connected in series between the drain-type load and ground. One end of the drain-type load is connected to an external power supply V0 (typically a 24V industrial field power supply), and the other end is connected to the drain of the NMOS transistor Q3. The source of Q3 is connected to one end of the sampling resistor R22; the other end of the resistor R22 is connected to the drain of the NMOS transistor Q1; the source of the NMOS transistor Q1 is directly grounded.

[0124] A voltage divider sampling network includes a series resistor R21 (preferably 470kΩ) and a resistor R20 (preferably 75kΩ); one end of resistor R21 is connected to the node between the sampling resistor R22 and the drain of the NMOS transistor Q1, and the other end is connected to resistor R20; the other end of resistor R20 is grounded; this voltage divider sampling network is used to sample the voltage drop formed by the load current across R22.

[0125] A comparator U6A (e.g., an open-drain output LM393) has its positive input connected to a reference voltage Vref2 (e.g., 0.83V); its negative input connected to the node between resistors R21 and R20 in the voltage divider sampling network; and its output connected to one end of a resistor R19 (preferably 4.7kΩ).

[0126] A pull-up bias circuit includes a resistor R27 (preferably 10kΩ), one end of which is connected to the internal control power supply VCC (e.g., 5V or 3.3V), and the other end is connected to the other end of a resistor R19.

[0127] The gate of NMOS transistor Q1 is directly connected to the node between resistors R27 and R19.

[0128] The gate of NMOS transistor Q3 is connected to the output of a controllable logic gate U5A (as a control signal drive unit) through a resistor R30.

[0129] The input of the controllable logic gate U5A is used to receive an external second voltage signal; its enable terminal is connected to the output of another comparator U3A. The non-inverting input of comparator U3A is connected to the node between resistors R21 and R20 in the voltage divider sampling network; its negative input is connected to the reference voltage Vref2.

[0130] In the above exemplary embodiment, the sinking switching protection circuit can be divided into three operating stages: normal operation, abnormal protection, and fault recovery. Its core principle is to monitor the load current by measuring the voltage drop across the resistor and use a comparator to determine if an overcurrent has occurred. Once a short circuit occurs, the protection circuit immediately causes the output stage MOSFETs (Q1 and Q3) to exit the saturation region and enter the linear region (high impedance state), thereby limiting the short-circuit current and achieving protection.

[0131] I. Normal working status Control signal on: A second voltage signal is applied to the controllable logic gate U5A, causing it to output a high level. This high level drives the gate of NMOS transistor Q3 through resistor R30, causing NMOS transistor Q3 to meet the conduction condition (V). GS > V TH When the NMOS transistor Q3 is fully turned on, its impedance is extremely low.

[0132] Output stage setup: With NMOS transistor Q3 turned on, the voltage of power supply V0 is mainly applied to the load, and the load operates normally.

[0133] At this time, the current flows through resistor R22 (1Ω), generating a small voltage drop across resistor R22 (V_R22 = I_load × R22).

[0134] Current monitoring and on-state maintenance: Resistors R21 and R20 form a voltage divider network to sample the voltage across resistor R22. Under normal current conditions, the voltage at this sampling point (i.e., the negative input terminal of U6A) is lower than the reference voltage Vref2; therefore, comparator U6A outputs a high level.

[0135] The high-level output of comparator U6A, through resistors R28 and R19, interacts with the VCC power supply from resistor R27 to pull the gate of NMOS transistor Q1 high. GS > V TH The NMOS transistor Q1 is also fully turned on, and the impedance of the entire path is extremely small.

[0136] II. Abnormal Protection Status When a sinking load is short-circuited to the power supply V0 (i.e., the two ends of the load are short-circuited), the power supply V0 voltage is applied almost directly to the NMOS transistor Q1 and resistor R22, causing the current to increase sharply.

[0137] This change will trigger the following mechanism: First layer of protection (current limiting of NMOS transistor Q1): The large short-circuit current generates a significant voltage drop across resistor R22, causing the voltage at the point where resistors R21 and R20 divide the circuit (i.e., the negative input of comparator U6A) to rise sharply, exceeding the reference voltage Vref2. At this point, comparator U6A flips, outputting a low level (close to 0V).

[0138] After comparator U6A outputs a low level, the power supply VCC forms a new voltage divider circuit through resistors R27, R19, and R28, as well as the low output of comparator U6A. This voltage divider significantly pulls down the gate voltage of NMOS transistor Q1. At this time, the VC of NMOS transistor Q1... GS The voltage becomes very small, possibly even less than its threshold voltage V. TH (V) GS < V TH When the NMOS transistor Q1 exits the saturation region and enters the linear region (high impedance state), the short-circuit current is greatly limited, which is the fastest first-line hardware protection.

[0139] Second layer of protection (NMOS transistor Q3 turn-off + signal shielding): The increase in voltage at the same sampling point is also transmitted to the positive input of comparator U3A, making its voltage higher than Vref2 at the negative input. Therefore, comparator U3A outputs a high level.

[0140] This high level is transmitted to the enable terminal of the controllable logic gate U5A through resistor R11, which shields or disables the controllable logic gate U5A, making its output invalid (becoming low level).

[0141] After the controllable logic gate U5A outputs a low level, the NMOS transistor Q3 is turned off because its gate voltage is pulled low (V). GS ≈ 0 <V TH This cuts off the main power path, providing a second layer of protection.

[0142] III. Fault Recovery Status Once the short-circuit fault is cleared, the huge short-circuit current disappears, the voltage drop across resistor R22 returns to normal, and the sampling point voltage subsequently falls back below the reference voltage Vref2. The output states of comparators U6A and U3A automatically flip back to their normal operating states. Comparator U3A outputs a low level, unshielding the controllable logic gate U5A; comparator U6A outputs a high level, resuming normal drive of the gate of NMOS transistor Q1. The circuit automatically resumes normal operation without any software intervention or external reset.

[0143] The circuit provided in this application embodiment, when a short circuit occurs in the sink output channel, combines the fast current limiting of NMOS transistor Q1 with the complete turn-off of NMOS transistor Q3 to form a dual protection with fast response speed and high reliability, thereby improving the reliability of the circuit; after the short circuit fault is cleared, the sampling point voltage returns to normal, all comparator states automatically flip, the circuit is deprotected and returns to normal operation without software intervention.

[0144] In one exemplary embodiment, the circuit further includes: Resistor R28 (preferably 100Ω) is connected in series between the output of comparator U6A and resistor R19; its main function is as a damping resistor / oscillation damping resistor. Detailed explanation follows: The NMOS transistor Q1 has a large parasitic capacitance (C_iss) between its gate and source. The output of comparator U6A typically has a certain output impedance, and long traces may also introduce inductance. These factors, along with the gate capacitance of the NMOS transistor Q1, easily form an LC resonant circuit. When the output state of comparator U6A changes rapidly (high-low level switching), it induces severe high-frequency oscillations on the gate of the NMOS transistor Q1. This gate oscillation causes the NMOS transistor Q1 to rapidly and violently switch between on and off states, resulting in the following problems: MOSFET overheating and damage: Frequent switching means huge switching losses.

[0145] Electromagnetic interference (EMI): Generates strong electromagnetic noise, affecting the normal operation of other circuits in the system.

[0146] Protection function failure: The circuit cannot stabilize in the current limiting protection state.

[0147] Connecting a small resistor R28 (e.g., 100Ω) in series can significantly increase the damping of the resonant circuit, effectively dissipating oscillation energy and thus smoothing the gate voltage waveform, making the switching process of the NMOS transistor Q1 smooth and reliable. This is a very common and critical design in high-speed switching circuits.

[0148] The resistance constraints for resistors R27, R19, and R28 are explained below: The core purpose of this constraint is to ensure that, in the event of a short circuit and the comparator U6A outputting a low level, the voltage divider network consisting of resistors R27, R19, and R28 can reduce the gate voltage V of the NMOS transistor Q1. G (Q1) Pull down to its threshold voltage V TH Nearby, it exits the saturation region and enters a linear high-resistance state, thereby achieving precise current limiting.

[0149] Under normal operating conditions, comparator U6A outputs high impedance, and the gate voltage V of NMOS transistor Q1 is... G (Q1) is pulled high to near VCC by pull-up resistor R27, V GS (Q1) > V TH PMOS transistor Q1 is fully turned on.

[0150] In the short-circuit protection state, comparator U6A outputs a low level (~0V). At this time, the gate circuit of NMOS transistor Q1 is equivalent to the power supply VCC passing through resistor R27, then through resistors R19 and R28, and finally to ground (the output of U6A). This is a typical voltage divider circuit. In this state, V... G (Q1) must be pulled down to make V GS (Q1) = V G (Q1) - V S (Q1) ≈ V G (Q1) - 0V = V G (Q1) < V TH (Q1), thus forcing the NMOS transistor Q1 into the linear region.

[0151] Let V TH (Q1) = 2.0V, for reliable current limiting, V needs to be designed. G (Q1)_protect ≈ 1.5V.

[0152] Assume VCC = 5V, U6A_output = 0V.

[0153] V G (Q1)_protect represents the voltage drop across VCC and ground caused by resistors R27, R19, and R28. In simplified terms, R19 and R28 are connected in series, and then the voltage is divided by R27.

[0154] V G (Q1)_protect = VCC * [(R19 + R28) / (R27 + R19 + R28)] 1.5V = 5V * [(R19 + R28) / (R27 + R19 + R28)] Solving for R19, we get: (R19 + R28) / (R27 + R19 + R28) = 0.3 This means that the total resistance of (R19 + R28) should be much smaller than the resistance of R27. In the example, R27 = 10kΩ, R19 = 4.7kΩ, and R28 = 100Ω. Substituting these values ​​into the calculation: (4.7k + 0.1k) / (10k + 4.7k + 0.1k) = 4.8k / 14.8k ≈ 0.324, therefore V is calculated. G (Q1) ≈ 5V * 0.324 = 1.62V, which meets the condition of being less than the typical NMOS threshold voltage (2V~4V), and can achieve reliable current limiting protection.

[0155] The function of resistor R28: Resistor R28 is a small-value resistor whose main function is to limit current and suppress oscillation, preventing ringing or overshoot when the output of comparator U6A directly charges and discharges the gate capacitance of NMOS transistor Q1, thus improving circuit stability. Its resistance is much smaller than that of resistor R19, and it has a smaller impact on the voltage division ratio, but it is indispensable.

[0156] Based on the above analysis, the resistance values ​​of resistors R27, R19, and R28 must satisfy the requirement that, under protection conditions, their voltage division across VCC results in a gate voltage V of the NMOS transistor. G (Q1) is lower than the threshold voltage V of NMOS transistor Q1. TH (Q1). This is the core constraint that ensures the successful implementation of the first-level current limiting function of the leakage protection circuit.

[0157] In one exemplary embodiment, the circuit further includes: Resistor R11 (preferably 100Ω) is connected in series between the output of comparator U3A and the enable terminal of controllable logic gate U5A. Its main functions are current limiting and isolation. Detailed explanation follows: Limiting fault current: The enable pin of the controllable logic gate U5A typically has an internal ESD (electrostatic discharge) protection diode. If the output voltage of the comparator U3A is higher than the VCC power supply voltage of the controllable logic gate U5A or lower than the ground voltage due to some anomaly (such as power-on transient or voltage spike), resistor R11 can limit the maximum current flowing into the control pin of the controllable logic gate U5A, preventing the internal ESD diode from burning out due to overcurrent, thereby protecting the controllable logic gate U5A.

[0158] Isolating capacitive loads: The enable terminal of the controllable logic gate U5A also has parasitic capacitance. Resistor R11 can isolate the output of comparator U3A from this capacitive load, preventing U3A from generating instantaneous large current or oscillation when driving a large capacitive load during state switching, thus improving the stability of U3A's operation.

[0159] Reduce mutual interference: It isolates the comparator U3A and the controllable logic gate U5A to a certain extent, reducing mutual interference between them.

[0160] Based on the above analysis, it can be seen that resistors R28 and R11 are both used to improve circuit stability and reliability. Resistor R28 is mainly used to suppress high-frequency oscillations and protect the NMOS transistor; resistor R11 is mainly used to limit current and protect sensitive chip control pins. Both are effective means of addressing common problems in high-speed switching circuits and chip interconnects.

[0161] Figure 4 for Figure 3 Another schematic diagram of the circuit shown. (See diagram below.) Figure 4 As shown, it demonstrates the... Figure 3 The improvements or optimizations to the circuit shown are noteworthy.

[0162] In an exemplary embodiment, the circuit further includes: a resistor R26 (preferably with a resistance of 10kΩ), one end of which is connected to the power supply VCC and the other end of which is connected to the output of comparator U3A, wherein the connection point between resistor R26 and the output of comparator U3A serves as the sampling point for a leak diagnostic signal, wherein the leak diagnostic signal is used to indicate whether a short circuit has occurred in the leak load.

[0163] In the above exemplary embodiment, the sinking protection circuit adds a hardware diagnostic circuit to report the short-circuit fault status of the sinking channel to the control system (such as MCU or PLC).

[0164] I. Normal working status The load current generates a small voltage drop across resistor R22, causing the voltage at the point where resistors R21 and R20 divide the voltage (i.e., the non-inverting input of U3A) to be lower than the reference voltage Vref2. Therefore, comparator U3A outputs a low level (because the voltage at its non-inverting input is lower than the voltage at its negative input Vref2).

[0165] Since comparator U3A typically has an open-drain output (such as LM393), its internal MOSFET turns on when the output is low, forcefully pulling the output to ground. At this time, even with a pull-up resistor R26 connected to VCC, the diagnostic signal sampling point will be forcibly clamped to a low level (close to 0V) by the internal output transistor of comparator U3A. Therefore, the sink-type diagnostic signal read by the control system is low, indicating that "the sink-type channel is normal and there is no short-circuit fault."

[0166] II. Abnormal Protection Status When a sinking load short-circuits to the power supply V0, the current increases dramatically, and the voltage drop across resistor R22 increases. This causes the voltage at the voltage divider point of R21 and R20 to rise sharply, exceeding the reference voltage Vref2.

[0167] Comparator U3A flips, and its output becomes high impedance (the internal MOSFET is off, and the open-drain output is equivalent to an open circuit). At this time, the power supply VCC is applied to the diagnostic signal sampling point through resistor R26. Therefore, the voltage at the sampling point is pulled up to a high level (VCC) by resistor R26.

[0168] The control system reads a high-level leak diagnostic signal, which is a clear "leak load short circuit" alarm signal.

[0169] In the exemplary embodiment described above, hardware-level real-time fault diagnosis of the sink channel is achieved through the cooperation of a pull-up resistor (resistor R26) and an open-drain output comparator U3A. It directly converts the current sampling comparison result into a level signal readable by the MCU, enabling rapid and reliable fault reporting, which is a key part of the system's intelligent monitoring and maintenance.

[0170] In an exemplary embodiment, the circuit further includes: resistor R24 ​​(preferably 10kΩ) and resistor R25 (preferably 2kΩ); wherein: one end of resistor R24 ​​is connected to power supply VCC, and the other end is connected to one end of resistor R25, wherein the other end of resistor R25 is grounded, and wherein the connection point between resistor R24 ​​and resistor R25 serves as a sampling point for reference voltage Vref2.

[0171] The exemplary embodiment described above designs an independent reference voltage generation circuit to provide a stable decision benchmark (reference voltage Vref2) for comparators U6A and U3A. Its principle is exactly the same as the generation principle of reference voltage Vref1 described above, but it serves the purpose of protecting the leakage-type switching circuit.

[0172] The circuit structure includes a simple voltage divider formed by resistors R24 and R25. A stable power supply VCC serves as the input.

[0173] The value of the reference voltage Vref2 is determined by the following expression: Vref2 = VCC * [R25 / (R24 + R25)].

[0174] Taking R24=10kΩ and R25=2kΩ as an example: Vref2 ≈ VCC * (2k / (10k + 2k)) = VCC * (1 / 6); If VCC = 5V, then Vref2 ≈ 0.83V.

[0175] The aforementioned reference voltage Vref2 is the benchmark threshold for judging whether the voltage drop across resistor R22 is too large.

[0176] Comparator U6A (with its negative input connected to Vref2) and comparator U3A (with its negative input connected to Vref2) compare the sampled voltage signal with Vref2.

[0177] For comparator U6A: When the sampled voltage > the reference voltage Vref2, the output is low, triggering the NMOS transistor Q1 to limit the current (first level of protection).

[0178] For comparator U3A: When the sampled voltage > the reference voltage Vref2, the output is high, triggering the NMOS transistor Q3 to turn off (secondary protection) and generating a diagnostic signal.

[0179] The technical advantages of the above solution include: Independence and stability: Provides an independent reference source for the sink circuit, ensuring its performance is unaffected by the source circuit or other components. Based on a stable power supply VCC, the reference voltage Vref2 is also highly stable.

[0180] Flexibility: By adjusting the resistance values ​​of resistors R24 and R25 separately, the overcurrent protection trigger point of the sink channel can be finely adjusted independently, so that it can have different protection thresholds than the source channel, adapting to a wider range of application scenarios.

[0181] In the exemplary embodiments described above, a precise current protection threshold is set, which is the cornerstone for the accurate and reliable operation of the entire leakage protection function. Its existence ensures that the protection behavior is no longer based on fuzzy analog changes, but on a precise comparison with a stable reference.

[0182] Figure 5 This is a schematic diagram of the structure of a switch quantity protection system provided in an embodiment of this application. Figure 5 As shown, the system includes the source-type switch protection circuit and the sink-type switch protection circuit described above.

[0183] In summary, the embodiments of this application provide a protection circuit with high reliability and fast response speed, which is suitable for the switch output channels in the industrial control industry. It can effectively improve the reliability of the system, and has the function of reporting short circuit phenomena, and can efficiently monitor port anomalies.

[0184] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, resistive RAM, resistive ROM, EEP resistive ROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A source-type switching quantity protection circuit, characterized in that, include: A PMOS transistor Q4, a resistor R1, and a PMOS transistor Q2 are connected in series, with PMOS transistor Q4 connected to the power supply V0 and the drain of PMOS transistor Q2 connected to the source load. One end of resistor R13 is connected between resistor R1 and the source of PMOS transistor Q2, and the other end is grounded through resistor R12; One end of resistor R2 is connected to power supply V0, and the other end is grounded through resistor R9; The voltage drop control unit has its positive terminal connected to the gate of PMOS transistor Q2 and its negative terminal connected to resistor R1 and the source of PMOS transistor Q2. The voltage drop control unit is used to provide a bias voltage to the gate of PMOS transistor Q2 when a source-type load is short-circuited, so that PMOS transistor Q2 operates in the linear region. The non-inverting input of comparator U10B is connected to the reference voltage Vref1, the negative input is connected between resistors R13 and R12, and the output is connected between resistors R2 and R9 via resistor R3. The gate of PMOS transistor Q4 is connected between resistors R2 and R9; The gate of PMOS transistor Q2 is connected to the collector of NPN transistor Q6, and the base of transistor Q6 is connected to the output of controllable logic gate U1A, with its emitter grounded. The input terminal of the controllable logic gate U1A is used to receive the first voltage signal, and the enable terminal is used to receive the enable signal output by the output terminal of the comparator U8B. The positive terminal of the comparator U8B is connected to the reference voltage Vref1, and the other end is connected between resistor R13 and resistor R12.

2. The circuit according to claim 1, characterized in that, The voltage drop control unit includes a Zener diode D1 and a resistor R14.

3. The circuit according to claim 1, characterized in that, The circuit also includes: Resistor R7 is connected at one end to the power supply VCC and at the other end to the output of comparator U8B. The connection point between resistor R7 and the output of comparator U8B serves as the sampling point for the source-type diagnostic signal, which is used to indicate whether a short circuit has occurred in the source-type load.

4. The circuit according to claim 1, characterized in that, The circuit also includes: Resistors R4 and R5; where: One end of resistor R4 is connected to the power supply VCC, and the other end is connected to one end of resistor R5, with the other end of resistor R5 grounded. The connection point between resistors R4 and R5 serves as the sampling point for the reference voltage Vref1.

5. The circuit according to any one of claims 1 to 4, characterized in that, The circuit also includes: Resistor R6 is connected in series between the output of controllable logic gate U1A and the base of NPN transistor Q6.

6. The circuit according to any one of claims 1 to 4, characterized in that, The circuit also includes: Resistor R10 is connected at one end between the base of NPN transistor Q6 and the output of controllable logic gate U1A, and at the other end to ground.

7. A leakage-type switch quantity protection circuit, characterized in that, include: The NMOS transistor Q3, resistor R22, and NMOS transistor Q1 are connected in series, with the drain of NMOS transistor Q3 connected to the power supply V0 through a drain load, and the source of NMOS transistor Q1 grounded. One end of resistor R21 is connected between resistor R22 and the drain of NMOS transistor Q1, and the other end is grounded through resistor R20; Comparator U6A has its positive input connected to the reference voltage Vref2, its negative input connected between resistors R21 and R20, and its output connected between resistor R27 and the gate of NMOS transistor Q1 via resistor R19. The gate of NMOS transistor Q3 is connected to the output of controllable logic gate U5A through resistor R30, wherein: The input terminal of the controllable logic gate U5A is used to receive the second voltage signal, and the enable terminal is connected to the output terminal of the comparator U3A. The positive input terminal of the comparator U3A is connected between resistors R21 and R20, and the negative input terminal is connected to the reference voltage Vref2.

8. The circuit according to claim 7, characterized in that, The circuit also includes: Resistor R26 is connected at one end to the power supply VCC and at the other end to the output of comparator U3A. The connection point between resistor R26 and the output of comparator U3A serves as the sampling point for the sinking diagnostic signal, which is used to indicate whether a short circuit has occurred in the sinking load.

9. The circuit according to claim 7, characterized in that, The circuit also includes: Resistors R24 and R25; where: One end of resistor R24 ​​is connected to the power supply VCC, and the other end is connected to one end of resistor R25. The other end of resistor R25 is grounded. The connection point between resistors R24 and R25 serves as the sampling point for the reference voltage Vref2.

10. The circuit according to claim 7, characterized in that, The circuit also includes: Resistor R28 is connected in series between the output of comparator U6A and resistor R19.

11. The circuit according to claim 7, characterized in that, The circuit also includes: Resistor R11 is connected in series between the output of comparator U3A and the enable terminal of controllable logic gate U5A.

12. A switch quantity protection system, characterized in that, Includes the circuit as described in any one of claims 1 to 6 and the circuit as described in any one of claims 7 to 11.

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