A deterministic ethernet pass-through clock efficient automatic measurement system and method

Abstract

The application provides a deterministic Ethernet clock transmission efficient automatic measurement system and method, and belongs to the technical field of deterministic networks.The method can be applied to development of a deterministic Ethernet related device, compared with traditional manual calibration for each link, avoids human operation error risks under a large amount of work, greatly reduces test complexity, and realizes automatic measurement of all physical link clocks in the network with the lowest cost without affecting existing time synchronization protocols and implementation bases.The application has the characteristics of universality, ease of use and high efficiency, can be transplanted to other products, and has a wide application prospect.

Description

Technical Field

[0001] This invention belongs to the field of deterministic network technology and relates to a deterministic Ethernet transparent clock high-efficiency automatic measurement system and method. Background Technology

[0002] In the development of deterministic Ethernet, the realization of time deterministic services is the core function of deterministic Ethernet. The foundation for realizing highly deterministic services is to achieve high-precision time synchronization. In the time synchronization process, the time delay of data frames on the data link is required, which is called the pass-through clock. The accuracy of the pass-through clock greatly affects the synchronization accuracy of the deterministic system.

[0003] When constructing deterministic Ethernet with high-precision time synchronization, the following technical challenges are encountered: Deterministic Ethernet has a large number of nodes, requiring manual calibration of the transparent clock for each data link, resulting in a large workload and posing a significant challenge to building complex deterministic network systems. Deterministic Ethernet is generally used in high-deterministic control systems such as aerospace, aviation, and vehicles. In spaceborne, airborne, and vehicle-mounted electronic systems, the network topology of their control system equipment may vary considerably. When the deterministic Ethernet network topology changes, the transparent clock value will change, requiring recalibration of the transparent clock. Manual calibration presents problems of high operational complexity and poor feasibility. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art. This invention provides a deterministic Ethernet transparent transmission clock high-efficiency automatic measurement system and method.

[0005] The solution of this invention is: a deterministic Ethernet transparent clock high-efficiency automatic measurement system, comprising: a synchronizer and a compression host;

[0006] The synchronizer, on the one hand, sends CS frames to the compression host and records the CS frame transmission time; on the other hand, it receives CS frames forwarded back by the compression host and records the CS frame reception time. Then, it calculates the measurement value of a single transparent transmission clock by subtracting the CS frame reception time from the CS frame transmission time. The final transparent transmission clock is obtained by averaging several measurements, thus realizing automatic measurement of the transparent transmission clock. Subsequently, the synchronizer updates the transparent transmission clock parameters and sends another CS frame before jumping to the normal working state.

[0007] The compression host receives the CS frame sent by the synchronizer, timestamps it, and then forwards it back to the synchronizer.

[0008] The aforementioned synchronization machine can be a synchronization master or a synchronization slave.

[0009] Furthermore, the synchronous master or synchronous slave both include a time synchronization state machine module, a PCF transmission scheduling module, a physical layer data frame transmission listening module, a send_pit_reg register, a physical layer data frame reception listening module, a recv_pit_reg register, a transparent clock calculation module, and a physical layer chip I.

[0010] The time synchronization state machine module has the function of controlling the time synchronization protocol of the synchronization master or the synchronization slave, and realizes the synchronization master or synchronization slave state machine that meets the requirements of the deterministic Ethernet time synchronization protocol.

[0011] The PCF transmission scheduling module sends time synchronization frames (CS frames) that conform to the deterministic Ethernet protocol according to the enable signal provided by the time synchronization state machine module.

[0012] The physical layer data frame transmission listening module listens for the valid transmission signal ETH_TX_EN and latches the value of the local time Local_Clk register into the send_pit_reg register.

[0013] The send_pit_reg register holds a value that serves as the transmission time point for use by the transparent clock calculation module.

[0014] The physical layer data frame receiving and listening module listens for the valid signal ETH_RX_DV and latches the value of the local time Local_Clk register into the recv_pit_reg register.

[0015] The recv_pit_reg register latches a value that serves as the receiving time point for use by the transparent clock calculation module.

[0016] The transparent clock calculation module is used to calculate and obtain the measured value of the transparent clock.

[0017] Physical layer chip I is an Ethernet physical layer chip on the synchronous master or synchronous slave hardware platform, responsible for the conversion between the Ethernet link layer MII signal and the physical layer MDI signal of the synchronous master or synchronous slave.

[0018] Furthermore, the time synchronization state machine module supports both transparent clock automatic measurement mode and normal operation mode.

[0019] In the automatic measurement mode of transparent clock, the state machine of the time synchronization state machine module is always in an asynchronous state. This module provides the CS frame transmission enable signal CS_EN to the PCF transmission scheduling module so as to realize the automatic measurement of transparent clock by means of the transmission process of CS frame.

[0020] In normal operating mode, the state machines of the time synchronization state machine module all perform state transitions in accordance with the requirements of the deterministic Ethernet protocol. That is, after the synchronization master receives the CS frame sent back by the compression master, it jumps from the asynchronous state to the flooding state, while the synchronization slave waits to receive the PCF to enter the synchronization state.

[0021] Furthermore, the compression host includes a physical layer chip II and a compression host synchronization module;

[0022] Physical layer chip II is an Ethernet physical layer chip on the compression host hardware platform, responsible for the conversion between the Ethernet link layer MII signal and the physical layer MDI signal of the compression host;

[0023] The compressed host synchronization module is used to implement compressed host time synchronization protocol control that meets the requirements of the deterministic Ethernet time synchronization protocol. It can receive CS frames sent by the synchronization host or synchronization slave, fix their time, and forward them back to the synchronization host or synchronization slave.

[0024] Furthermore, the compression host synchronization module has an independent transparent clock parameter register for each port, which is configured with a unified initial value. In the working state, each port monitors the transparent clock field of the received PCF and updates the value of the field to the transparent clock parameter register of the corresponding port, which serves as the transparent clock value for the compression host to send the PCF.

[0025] A method for efficient automatic measurement of deterministic Ethernet transparent clocks includes:

[0026] (1) The synchronous master or synchronous slave enters the automatic measurement state of transparent clock;

[0027] (2) The time synchronization state machine module sends an enable signal according to the time parameters at a configured period;

[0028] (3) The PCF frame transmission scheduling module starts CS frame transmission after receiving the enable signal;

[0029] (4) Physical layer data frame transmission listening module, which records the transmission time of CS frames used to measure the transparent clock;

[0030] (5) The CS frame is transmitted to the compression host synchronization module through physical layer chip I and physical layer chip II. The compression host synchronization module forwards the solidified CS back to the synchronization host or synchronization slave.

[0031] (6) Physical layer data frame receiving and listening module, which records the receiving time of CS frames used to measure the transparent clock;

[0032] (7) Transparent clock calculation module, calculates and obtains the measured value of transparent clock; determines whether the measurement number n is satisfied. If satisfied, proceed to step (8); otherwise, return to step (2).

[0033] (8) The synchronous host or synchronous slave updates the transparent clock to the measured value, and after sending the CS frame again, it jumps to the normal working state. The compression host updates the transparent clock value according to the CS frame content.

[0034] Furthermore, the physical layer chip I and physical layer chip II are of the same type, meaning that the physical layer chip delays of the transmitting and receiving links are the same.

[0035] Furthermore, the method for obtaining the transmission time point is as follows: the physical layer data frame transmission listening module listens for the valid transmission signal ETH_TX_EN, latches the local time Local_Clk into the send_pit_reg register, and obtains the transmission time point.

[0036] Furthermore, the method for obtaining the receiving time point is as follows: the physical layer data frame receiving and listening module listens for the valid receiving signal ETH_RX_DV, latches the local time Local_Clk into the send_pit_reg register, and obtains the receiving time point.

[0037] Furthermore, the step of calculating and obtaining the measured value of the transparent clock is as follows:

[0038] First, the measured value of a single transparent clock transmission is obtained:

[0039]

[0040] recv_pit_reg is the receiving time point, and send_pit_reg is the sending time point;

[0041] Then, the average value of the TP_CLOCK measured n times is taken to obtain the final transparent clock value:

[0042]

[0043] TP_CLOCK i Let represent the i-th transparent clock measurement value, 1≤i≤n.

[0044] The beneficial effects of this invention compared to the prior art are:

[0045] Compared to traditional manual calibration for each link, this invention uses real-time dynamic automatic measurement of the system-level transparent clock, avoiding the risk of human error under heavy workload and greatly reducing testing complexity; the system-level transparent clock is acquired locally, simplifying the construction of complex deterministic networks with high-precision time synchronization; this invention achieves automatic measurement of the transparent clock of all physical links in the network with minimal overhead without affecting existing time synchronization. Attached Figure Description

[0046] Figure 1 A schematic diagram of a deterministic Ethernet transparent clock automatic measurement architecture;

[0047] Figure 2 Flowchart for automatic measurement of clocks via deterministic Ethernet pass-through. Detailed Implementation

[0048] The present invention will now be described in detail with reference to the accompanying drawings.

[0049] Deterministic Ethernet is generally used in highly deterministic control systems such as aerospace, aviation, and vehicles. In spaceborne, airborne, and vehicle-mounted electronic systems, the network topology of their control system equipment may vary greatly. Deterministic Ethernet has a large number of nodes, and when the network topology changes, the transparent clock value will change, requiring recalibration of the transparent clock. Manual calibration is labor-intensive, inaccurate, and impractical. The proposed method for efficient automatic measurement of the transparent clock in deterministic Ethernet enables automatic measurement of the transparent clock in complex and variable topology environments. In complex network topologies, the transparent clock of each physical link can be obtained without manual calibration, greatly reducing the complexity of building complex high-precision time synchronization networks.

[0050] This invention designs a transparent clock automatic measurement architecture, which adds a transparent clock automatic measurement state without changing the traditional time synchronization function, and is used to accurately measure logical delay and physical delay to automatically obtain the transparent clock value on all links.

[0051] like Figure 1 As shown, a deterministic Ethernet transparent clock high-efficiency automatic measurement system includes a synchronization master or synchronization slave and a compression master.

[0052] (1) Synchronous master or synchronous slave, including time synchronization state machine module, PCF (Protocol Control Frame) transmission scheduling module, physical layer data frame transmission listening module, send_pit_reg register, physical layer data frame reception listening module, recv_pit_reg register, transparent clock calculation module, physical layer chip I;

[0053] The time synchronization state machine module is a module with Synchronization Master (SM) / Synchronization Client (SC) time synchronization protocol control functions, implementing an SM / SC state machine that conforms to the requirements of the deterministic Ethernet time synchronization protocol. The time synchronization state machine module is designed with two operating modes: transparent clock automatic measurement mode and normal operation mode. In the transparent clock automatic measurement mode, the state machine of the time synchronization state machine module is always in the asynchronous (UNSYNC) state. In this state, the module provides a cold start frame transmission enable signal CS_EN to the PCF transmission scheduling module to realize transparent clock automatic measurement through the transmission process of the cold start frame. In the normal operation mode, the state machine of the time synchronization state machine module performs state transitions according to the requirements of the deterministic Ethernet protocol. That is, after the SM receives the cold start frame sent back by the compressed host, it normally jumps from the asynchronous state to the flood state, while the SC waits to receive the PCF to enter the synchronization state.

[0054] The PCF transmission scheduling module is a module in the synchronous master or slave that has the function of scheduling and sending time synchronization protocol control frames (PCF) according to a plan. It can send various time synchronization frames that conform to the deterministic Ethernet protocol, including CS (Coldstart) frames, CA (Coldstart Acknowledge) frames, and IN (Integration) frames, according to the enable signal provided by the time synchronization state machine module. In this method, in the transparent clock automatic measurement mode, this module continuously sends CS frames according to the CS_EN signal provided by the time synchronization state machine module.

[0055] The physical layer data frame transmission listening module is one of the core modules of this invention. It is responsible for recording the transmission time of the CS frame used to measure the transparent clock in the synchronous master or synchronous slave, that is, listening for the valid transmission signal ETH_TX_EN, and latching the value of the local time Local_Clk register into the send_pit_reg register as the transmission time and sending it to the transparent clock calculation module.

[0056] The send_pit_reg register is used to automatically calculate the pass-through clock by the CS frame transmission time point obtained by the physical layer data frame transmission listening module in the synchronous master or synchronous slave.

[0057] The physical layer data frame receiving and listening module is one of the core modules of this invention. In the synchronous master or synchronous slave, it is responsible for recording the receiving time point of the CS frame used to measure the transparent clock, that is, listening for the valid receiving signal ETH_RX_DV, and latching the value of the local time Local_Clk register into the recv_pit_reg register as the receiving time point and sending it to the transparent clock calculation module.

[0058] The recv_pit_reg register is used to automatically calculate the pass-through clock by the CS frame reception time point obtained by the physical layer data frame reception and listening module in the synchronous master or synchronous slave.

[0059] The transparent clock calculation module is one of the core modules of this invention. It is responsible for calculating the transparent clock value based on the values ​​of send_pit_reg and recv_pit_reg in the synchronous master or synchronous slave, thereby obtaining the transparent clock parameters through the automatic measurement of the system.

[0060] Physical layer chip I is an Ethernet physical layer chip on a synchronous host or synchronous slave hardware platform, responsible for the conversion between Ethernet link layer MII (Media Independent Interface) signals and physical layer MDI (Media Dependent Interface) signals;

[0061] (2) Compression host, including physical layer chip II and compression host synchronization module;

[0062] Physical layer chip II is an Ethernet physical layer chip on the compression host hardware platform, responsible for the conversion between Ethernet link layer MII signals and physical layer MDI signals; this invention requires that physical layer chip II on the compression host be the same model chip as physical layer chip I on the synchronous host or synchronous slave.

[0063] The compression master synchronization module is a module that implements the time synchronization protocol control function of the compression master (CM) in accordance with the requirements of the deterministic Ethernet time synchronization protocol. Its main functions include time fixing, PCF frame merging, compression, optimal frame selection, CM state machine control, PCF framing, etc. This method uses CS frames for transparent automatic clock measurement. After receiving the CS frame from the synchronization master or synchronization slave, the compression master sends it to the compression master synchronization module, and after time fixing, it forwards it back to the synchronization master or synchronization slave.

[0064] like Figure 2 As shown, a deterministic Ethernet transparent clock efficient automatic measurement method is proposed, and the specific steps are as follows:

[0065] (1) In the compression host synchronization module, an independent transparent clock parameter register is set for each port and configured with a uniform initial value. In the working state, each port monitors the transparent clock field of the received PCF and updates the value of the field to the transparent clock parameter register of the corresponding port as the transparent clock value of the compression host to send the PCF. The synchronization host or synchronization slave enters the transparent clock automatic measurement state. In this state, the synchronization state machine of the synchronization host or synchronization slave time synchronization state machine module is always in the asynchronous (UNSYNC) state and does not respond to the CS frame replied by the compression host.

[0066] (2) The time synchronization state machine module of the synchronous master or synchronous slave gives the CS_EN enable signal according to the time parameter and the configured period;

[0067] (3) The PCF frame transmission scheduling module of the synchronous master or synchronous slave receives the CS_EN transmission enable signal and starts CS frame transmission;

[0068] (4) The physical layer data frame transmission listening module of the synchronous master or synchronous slave listens for the valid transmission signal ETH_TX_EN. When the CS frame transmission is started, the local time Local_Clk is latched into the send_pit_reg register to obtain the transmission time point;

[0069] (5) When the compression host synchronization module receives the CS frame, it forwards the solidified CS back to the synchronization host or synchronization slave.

[0070] (6) The physical layer data frame receiving and listening module of the synchronous master or synchronous slave listens for the valid reception signal ETH_RX_DV. When CS reception is started, the local time Local_Clk is latched into the recv_pit_reg register to obtain the reception time point.

[0071] (7) The synchronous master or synchronous slave transparent clock calculation module calculates the difference between the values ​​of recv_pit_reg and send_pit_reg obtained in steps (6) and (4):

[0072] Δ=recv_pit_reg-send_pit_reg (1)

[0073] (8) The formula for calculating the transparent clock value is as follows:

[0074] TP_CLOCK=phy_send_delay+link_send_delay+phy_recv_delay (2) phy_send_delay is the physical layer chip delay of the sending link; link_send_delay is the physical layer chip delay of the receiving link; phy_recv_delay is the data link delay between the physical layer chip of the synchronization master or synchronization slave and the physical layer chip of the compression master.

[0075] Since the physical layer chip models of the synchronous master or synchronous slave and the compression master are the same, that is, the physical layer chip delays of the transmitting and receiving links are the same, and the data link delays are the same, then combining equations (1) and (2) yields:

[0076]

[0077] (9) Obtain the transparent clock value TP_CLOCK by averaging the values ​​of n measurements of TP_CLOCK. avg As shown below:

[0078]

[0079] TP_CLOCK i Let represent the i-th transparent clock measurement value, 1≤i≤n.

[0080] (10) Set TP_CLOCK avg The value is filled into the transparent clock register of the link on the synchronous host or synchronous slave as a configuration parameter. After the synchronous host or synchronous slave sends another CS frame (the transparent clock value in its payload has been updated to the parameter value obtained by automatic measurement), it enters the normal working state. After the compression host receives the CS frame, it updates the automatic measurement result in the transparent clock field to the transparent clock parameter register of the corresponding port.

[0081] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A deterministic Ethernet transparent clock high-efficiency automatic measurement system, characterized in that, include: Synchronizer, compressor host; The sync unit sends CS frames to the compression host and records the time of CS frame transmission. On the other hand, it receives CS frames forwarded back by the compressed host and records the CS frame reception time. Then, the difference between the CS frame reception time and the CS frame transmission time is calculated to determine the measurement value of the single transparent transmission clock. The final transparent clock is obtained by averaging several measurements, thus realizing automatic measurement of the transparent clock. Subsequently, the synchronizer updates the transparent clock parameters and sends another CS frame before jumping to the normal working state. The compression host receives the CS frame sent by the synchronizer, timestamps it, and then forwards it back to the synchronizer. The aforementioned synchronizer can be a master synchronizer or a slave synchronizer. The CS frame is a cold start frame.

2. The deterministic Ethernet transparent clock high-efficiency automatic measurement system according to claim 1, characterized in that, The aforementioned synchronization master or synchronization slave both include a time synchronization state machine module, a PCF transmission scheduling module, and a physical layer data frame transmission listening module. Registers, physical layer data frame receiving and listening module, Registers, transparent clock calculation module, physical layer chip I; The time synchronization state machine module has the function of controlling the time synchronization protocol of the synchronization master or the synchronization slave, and realizes the synchronization master or synchronization slave state machine that meets the requirements of the deterministic Ethernet time synchronization protocol. The PCF transmission scheduling module sends CS frames conforming to the deterministic Ethernet protocol according to the enable signal provided by the time synchronization state machine module. The physical layer data frame transmission listening module listens for valid transmission signals. , local time The register value is latched to register; The register, whose latched value serves as the transmission time point, is used by the transparent clock calculation module. The physical layer data frame receiving and listening module listens for valid signals. , local time The register value is latched to register; The register, whose latched value serves as the receiving time point, is used by the transparent clock calculation module. The transparent clock calculation module is used to calculate and obtain the measured value of the transparent clock. Physical layer chip I is an Ethernet physical layer chip on the synchronous master or synchronous slave hardware platform, responsible for the conversion between the Ethernet link layer MII signal and the physical layer MDI signal of the synchronous master or synchronous slave.

3. The deterministic Ethernet transparent clock high-efficiency automatic measurement system according to claim 2, characterized in that, The time synchronization state machine module supports both transparent clock automatic measurement mode and normal working mode. In the transparent clock automatic measurement mode, the state machine of the time synchronization state machine module is always in an asynchronous state. This module provides the CS frame transmission enable signal to the PCF transmission scheduling module. This allows for automatic measurement of the transparent clock by leveraging the transmission process of CS frames. In normal operating mode, the state machines of the time synchronization state machine module all perform state transitions in accordance with the requirements of the deterministic Ethernet protocol. That is, after the synchronization master receives the CS frame sent back by the compression master, it jumps from the asynchronous state to the flooding state, while the synchronization slave waits to receive the PCF to enter the synchronization state.

4. The deterministic Ethernet transparent clock high-efficiency automatic measurement system according to claim 1, characterized in that, The compression host includes a physical layer chip II and a compression host synchronization module; Physical layer chip II is an Ethernet physical layer chip on the compression host hardware platform, responsible for the conversion between the Ethernet link layer MII signal and the physical layer MDI signal of the compression host; The compressed host synchronization module is used to implement compressed host time synchronization protocol control that meets the requirements of the deterministic Ethernet time synchronization protocol. It can receive CS frames sent by the synchronization host or synchronization slave, fix their time, and forward them back to the synchronization host or synchronization slave.

5. The deterministic Ethernet transparent clock high-efficiency automatic measurement system according to claim 4, characterized in that, The compression host synchronization module has an independent transparent clock parameter register for each port, which is configured with a unified initial value. In the working state, each port monitors the transparent clock field of the received PCF and updates the value of the field to the transparent clock parameter register of the corresponding port, which serves as the transparent clock value for the compression host to send the PCF.

6. A method for efficient automatic measurement of deterministic Ethernet transparent clock, characterized in that, include: (1) The synchronous master or synchronous slave enters the automatic measurement state of transparent clock; (2) The time synchronization state machine module sends an enable signal at a configured period according to the time parameters; (3) The PCF frame transmission scheduling module starts CS frame transmission after receiving the enable signal; (4) Physical layer data frame transmission listening module, which records the transmission time of CS frames used to measure the transparent clock; (5) The CS frame is transmitted to the compression host synchronization module via physical layer chip I and physical layer chip II. The compression host synchronization module forwards the solidified CS back to the synchronization host or synchronization slave. (6) Physical layer data frame receiving and listening module, which records the receiving time of CS frames used to measure the transparent clock; (7) Transparent clock calculation module, which calculates and obtains the measured value of the transparent clock; Determine whether the number of measurements n is satisfied. If it is satisfied, proceed to step (8); otherwise, return to step (2). (8) The synchronous host or synchronous slave updates the transparent clock to the measured value, and after sending the CS frame again, it jumps to the normal working state. The compression host updates the transparent clock value according to the content of the CS frame. The CS frame is a cold start frame.

7. The method for efficient automatic measurement of deterministic Ethernet transparent clock according to claim 6, characterized in that, The physical layer chip I and physical layer chip II are of the same model, meaning that the physical layer chip delays of the transmitting and receiving links are the same.

8. The method for efficient automatic measurement of deterministic Ethernet transparent clock according to claim 6, characterized in that, The method for obtaining the transmission time point is as follows: the physical layer data frame transmission listening module listens for valid transmission signals. , local time Latch to The transmission time point is obtained from the register.

9. The method for efficient automatic measurement of deterministic Ethernet transparent clock according to claim 6, characterized in that, The method for obtaining the receiving time point is as follows: the physical layer data frame receiving and listening module listens for valid received signals. , local time Latch to The receiving time point is obtained from the register.

10. The method for efficient automatic measurement of deterministic Ethernet transparent clock according to claim 6, characterized in that, The steps for calculating and obtaining the measured value of the transparent clock are as follows: First, the measured value of a single transparent clock transmission is obtained: For the time point of reception, The time point of transmission; Then for n measurements The values ​​are averaged to obtain the final transparent clock value: Indicates the first i The next transparent clock measurement value, 1≤ i ≤n.

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