FPGA-based backplane bus communication method

Abstract

The application discloses a backplane bus communication method based on FPGA and relates to the technical field of communication.The method comprises the following steps: each module realizes the automatic identification of the master station and the slave station by detecting the address; the master station adopts the reverse traversal mode to send a topology query message to the slave station, and the network topology table is quickly established; after the topology is established, the master station generates and transmits a token, and each slave station encapsulates an Ethernet frame into a BLVDS message for transmission when holding the token, so that the high-speed data communication between the modules is realized.The system dynamically adjusts the sending opportunity when the token is held according to the historical sending frequency and the buffer state of the module, avoids the long-term failure to send of the low-frequency module, limits the excessive occupation of the high-frequency module, and improves the overall throughput.The master station continuously monitors the bus state, preferentially executes the local area topology repair when detecting the loss of the token, and then performs the whole network reconstruction after continuous failure, so that the recovery cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a backplane bus communication method based on FPGA. Background Technology

[0002] Currently, common inter-module communication methods in industrial control, communication equipment, and multi-module systems include SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), CAN (Controller Area Network), and BLVDS (Bus LowVoltage Differential Signaling).

[0003] Among them, SPI, I2C, and CAN buses, due to their bus characteristics, can generally only achieve low-speed data transmission, making it difficult to meet the needs of high-speed and large-volume communication. In contrast, the BLVDS bus, as a low-voltage differential transmission method, has a higher data transmission rate and stronger anti-interference capability, making it suitable for high-speed communication with large data volumes. Therefore, existing technologies often employ a combination of CAN bus arbitration and BLVDS data communication, that is, arbitration is completed through the CAN bus, and then data transmission is performed through the BLVDS bus. While this scheme improves communication speed to some extent, the arbitration process still relies on the CAN bus. Although the CAN bus arbitration mechanism can ensure timely transmission by high-priority nodes, low-priority nodes often have to wait for a long time, which can lead to "starvation" and insufficient overall system real-time performance. Using the CAN bus requires additional controllers and hardware circuits, which increases system complexity and cost, especially in large-scale modular systems. The priority of the CAN bus is usually fixed in the system design phase and lacks the ability to be dynamically adjusted according to the real-time communication load. Therefore, it is difficult to respond to communication needs in a timely manner under high load, reducing system flexibility. As the system scales up, the time overhead of CAN arbitration increases significantly, leading to a decline in system performance and making it difficult to meet the communication needs of large-scale networks.

[0004] Besides the CAN+BLVDS combination, other communication protocols are also used in multi-module communication, such as RS485 and Ethernet. RS485 is commonly used in industrial automation and building control, offering multi-point communication and interference resistance. However, due to its half-duplex nature, it cannot guarantee good real-time performance in concurrent communication scenarios. Furthermore, RS485 lacks a built-in arbitration mechanism and often relies on master-slave architectures or software arbitration, which can introduce communication latency and reduce real-time performance.

[0005] Ethernet communication offers high-speed transmission and good scalability, making it suitable for scenarios involving large data volumes. However, its collision detection and avoidance mechanisms (such as CSMA / CD) struggle to guarantee real-time performance under high load conditions. Furthermore, Ethernet typically requires complex protocol stacks and incurs high hardware costs, making it unsuitable for simple modular communication applications.

[0006] In summary, existing communication methods suffer from various problems to varying degrees, such as insufficient real-time performance, high hardware costs, high system complexity, or limited scalability, and cannot fully meet the requirements of multi-modal systems in terms of high real-time performance, high reliability, and high scalability. Summary of the Invention

[0007] To address the challenge of achieving high-speed, low-cost, and scalable backplane communication in large-scale modular systems while maintaining real-time performance, reliability, and flexibility, this invention proposes an FPGA-based backplane bus communication method. Based on the FPGA architecture, this method eliminates the traditional CAN bus arbitration mechanism, thereby avoiding the need for a CAN controller. This not only simplifies the system's hardware implementation and reduces hardware costs but also avoids the latency issues associated with CAN bus arbitration.

[0008] The present invention achieves the above objectives through the following technical solutions: A backplane bus communication method based on FPGA is applied to a communication system consisting of multiple modules interconnected via a backplane BLVDS bus. The method includes: Each module detects its own address signal. The module with address 0 is automatically identified as the master station and is responsible for initiating the establishment of the network topology. The other modules are all sub-stations. The master station sends topology query messages to each substation in reverse order from the highest physical slot address to the lowest physical slot address via unicast, and determines the online status of each substation based on whether an acknowledgment message is received, thus forming a network topology table. After the topology is established, the master station holds the initial token and passes it according to the topology order. After receiving the token, each substation, if it has an Ethernet frame to be sent, encapsulates the Ethernet frame into a BLVDS message and sends it, and releases the token after completion. Based on the historical Ethernet frame transmission frequency and current buffer status of each module on the backplane BLVDS bus, the Ethernet frame transmission opportunity of the module when holding a token is dynamically adjusted. Specifically, if the historical transmission frequency of any module is lower than a preset proportion of the total bandwidth and there are Ethernet frames to be transmitted, the priority of that module is increased to avoid being unable to transmit for a long time. If the historical transmission frequency of any module is higher than a preset proportion, the maximum number of frames that module can transmit when holding a token at one time is limited to improve the overall communication efficiency. The master station continuously monitors the status of the backplane BLVDS bus. If no BLVDS message is transmitted or no token is received within a preset time, it determines that the token is lost and re-initiates the topology establishment process. The master station prioritizes performing topology repair on local areas to reduce the overhead of rebuilding the entire network. If the topology repair of local areas fails for a preset number of consecutive times, the entire network topology is rebuilt.

[0009] As a preferred embodiment of the present invention, each module in the communication system includes: The FPGA chip, as the core control unit, is used to implement communication logic control and data processing; The BLVDS chip, as a physical transceiver, is electrically connected to the BLVDS bus on the backplane to complete the transmission and reception of differential signals. The FPGA chip includes: The Ethernet MAC controller, as a standard Ethernet protocol receiving module, is used to encapsulate and decapsulate Ethernet frames, and interacts with external CPUs or upper-layer processing units through the MII interface. The MAC2BLVDS module is used to implement format adaptation and protocol conversion between Ethernet frames and BLVDS messages. The FPGA chip also includes a token passing module, which is used to implement token-based bus access control logic to ensure that each module has exclusive access to the bus to send data when it holds a token; it also supports token generation, passing and loss detection.

[0010] As a preferred embodiment of the present invention, the MAC2BLVDS module specifically includes: The MAC control unit, as an interface logic, interacts with the Ethernet MAC controller to write received Ethernet frames into the SEND BRAM and retrieve data from the RECEIVE BRAM and send it back to the Ethernet MAC controller. The BRAM buffer unit includes SEND BRAM and RECEIVE BRAM, which are used to store Ethernet frames to be sent and Ethernet frames after decapsulation of received BLVDS messages, respectively. The BLVDS control unit is electrically connected to the BLVDS chip at the top and interacts with the BLVDS bus on the backplane via differential signals; it interacts with the SEND BRAM or RECEIVE BRAM at the bottom to complete data encapsulation and decapsulation.

[0011] As a preferred embodiment of the present invention, the topology query message includes a message header, message length, topology frame bytes, destination address, next-hop address, and CRC checksum, and adopts an asynchronous serial transmission method.

[0012] As a preferred embodiment of the present invention, the online status of the substation is recorded in the register during the topology establishment process. If the substation does not return an acknowledgment message within a preset time, the master station will retry the substation a preset number of times. If no acknowledgment message is received, the substation will be skipped and the topology traversal will continue.

[0013] As a preferred embodiment of the present invention, the token transmission interval increases progressively in the bus idle state until a preset maximum value is reached, and is adjusted to real-time transmission when there is a demand for BLVDS message transmission.

[0014] As a preferred embodiment of the present invention, the step of dynamically adjusting the Ethernet frame transmission opportunity of a module when holding a token based on the historical Ethernet frame transmission frequency and current buffer status of each module on the backplane BLVDS bus specifically includes: When the historical transmission frequency of any module is less than 30% of the total bandwidth and there are Ethernet frames to be transmitted, the priority of that module is automatically increased, and the number of Ethernet frames that the module is allowed to transmit the next time it holds a token is determined by (1 - historical transmission frequency) × (number of frames to be transmitted); When the historical transmission frequency of any module is higher than 60% of the total bandwidth, the priority of that module is reduced, so that the module can send a maximum of 1 Ethernet frame each time it holds a token. In other cases, each module transmits data at a maximum of two Ethernet frames at a time when holding a token.

[0015] As a preferred embodiment of the present invention, the master station continuously monitors the status of the backplane BLVDS bus. When the master station does not detect a BLVDS message within 5ms or does not receive a returned token within 100ms, it determines that the token is lost. Meanwhile, the substation monitors its own token acquisition status in real time. If it detects that it has not acquired a token within 100ms, it is determined that it has left the network topology. At this time, the substation sends an interference signal to the backplane BLVDS bus according to its own position in the network topology when the token is passed from its previous hop to the next hop, so as to prompt the master station to re-establish the link.

[0016] As a preferred embodiment of the present invention, the topology repair of the local area includes: the main station determines the module A that last holds the token and the module B that is the previous hop of the module through real-time monitoring, and adopts a reverse traversal mechanism to rebuild the topology only for the modules in the interval [B,A]. If topology repair in a local area fails three times in a row, the main station will perform a full network topology reconstruction.

[0017] As a preferred embodiment of the present invention, the master station is equipped with a 32-bit bus status counter and a substation status counter. The bus status counter is incremented each time the link is re-established, and the substation status counter is incremented accordingly by comparing the changes in the online registers of the substation before and after the link is established, so as to quickly locate abnormal modules or bus faults.

[0018] The beneficial effects of this invention are as follows: Each module automatically distinguishes between the master station and sub-stations by detecting its own address. The master station initiates a reverse-order topology query, which can efficiently determine the online status of each sub-station and quickly form a network topology table, improving the efficiency and accuracy of topology establishment. After the topology is established, the master station holds and transmits a token. Each sub-station, while holding a token, encapsulates Ethernet frames into BLVDS messages for transmission. This utilizes the high speed and strong anti-interference capability of the BLVDS bus while ensuring conflict-free communication under token control, thereby achieving efficient and stable data transmission between modules. The system dynamically adjusts the transmission opportunities of modules when holding a token based on their historical transmission frequency and buffer status. Low-frequency modules are given higher priority when they have data to send, avoiding prolonged periods without transmission; high-frequency modules are limited in the number of frames they can send under high load conditions, thus achieving fair bandwidth allocation and improving overall throughput. By continuously monitoring the bus status, the master station can quickly determine that the token is lost if no message is detected or no token is received within a preset time, and then re-initiate the topology establishment process. The system prioritizes performing topology repair on local areas and only performs full network topology reconstruction when local repairs fail consecutively. This significantly reduces the time overhead of network recovery and improves the availability and reliability of the system under abnormal conditions. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a diagram illustrating the overall architecture of the communication system according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the MAC2BLVDS module structure in an embodiment of the present invention; Figure 3 This is a flowchart of a method according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the reverse traversal topology in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0021] The backplane bus communication method provided in this invention is applied to a communication system consisting of multiple modules (plugged into the backplane, including at least one master station module and multiple slave station modules) interconnected via a backplane BLVDS bus. The architecture of this communication system is as follows: Figure 1 As shown, each module includes: The FPGA chip, as the core control unit, is used to implement communication logic control and data processing; The BLVDS chip, as a physical transceiver, is electrically connected to the backplane BLVDS bus to complete the transmission and reception of differential signals. It sends the BLVDS messages generated by the FPGA chip to the backplane BLVDS bus in the form of differential signals, or receives the differential signals on the backplane BLVDS bus and outputs them as corresponding BLVDS messages.

[0022] The FPGA chip contains: The Ethernet MAC controller, as a standard Ethernet protocol receiving module, implements Ethernet frame encapsulation and decapsulation; it interacts with external CPUs or upper-layer processing units through the MII interface. The MAC2BLVDS module is used to implement format adaptation and protocol conversion between Ethernet frames and BLVDS messages. The FPGA chip also includes a token passing module, which implements token-based bus access control logic to ensure that each module has exclusive access to the bus to send data when it holds a token; it also supports token generation, passing and loss detection.

[0023] Furthermore, such as Figure 2 As shown, the MAC2BLVDS module is internally divided into the following sub-modules: The MAC control unit, as an interface logic, interacts with the Ethernet MAC controller to write received Ethernet frames into the SEND BRAM and retrieve data from the RECEIVE BRAM and send it back to the Ethernet MAC controller. The BRAM buffer unit includes SEND BRAM (i.e., transmit buffer) and RECEIVE BRAM (i.e., receive buffer). SEND BRAM is used to store Ethernet frames to be sent; RECEIVE BRAM is used to store Ethernet frames after the received BLVDS messages have been decapsulated. The BLVDS control unit is electrically connected to the BLVDS chip at the top and interacts with the BLVDS bus on the backplane via differential signals; it also interacts with the SEND BRAM / RECEIVE BRAM at the bottom to complete data encapsulation and decapsulation.

[0024] The BLVDS control unit encapsulates the Ethernet frames to be sent in the SEND BRAM into BLVDS messages (including message header 0x0564, message length, topology frame bytes, destination address, next-hop address, Ethernet frame data, CRC16, etc.) and sends them to the backplane BLVDS bus through the BLVDS chip; or performs CRC check on the BLVDS messages received from the bus. If the CRC16 is correct, it continues to check whether the received destination address is consistent with its own address, or is 0xff. If they are consistent, it removes 0x0564, message length, topology frame bytes, destination address, next-hop address and the CRC16 at the end, and stores the remaining Ethernet frame data into the RECEIVE BRAM.

[0025] The back bus consists of a pair of differential signal lines, with 100Ω terminating resistors connected in parallel across both ends. The differential signal lines of the BLVDS control unit are connected to the bus via a 50Ω resistor in series.

[0026] In this embodiment, the data flow and connection logic is as follows: Transmission path: CPU → Ethernet MAC controller → MAC control unit → SEND BRAM → BLVDS control unit (frame encapsulation) → BLVDS chip → backplane BLVDS bus; Receive path: Backplane BLVDS bus → BLVDS chip → BLVDS control unit (CRC check, address comparison and decapsulation) → RECEIVE BRAM → MAC control unit → Ethernet MAC controller → CPU; Control path: The token passing module works in conjunction with the BLVDS control unit to ensure that after the module holding the token completes the sending, the token can be sequentially passed to the next module, realizing conflict-free scheduling of bus communication.

[0027] like Figure 3 , Figure 4 As shown, the FPGA-based backplane bus communication method in this embodiment includes the following: S1: System Initialization and Topology Establishment Master station identification: The backplane slot is uniquely identified by a 5-bit address signal, ranging from 0 to 31, where address 0 is the master station address. After power-on, each module detects its own address signal. The module with address 0 is automatically identified as the master station, and the remaining modules are slave stations. A module must be present at the master station position to initiate network topology establishment and re-establish the topology after a system connection failure.

[0028] Reverse topology traversal: The master station sends topology query messages (format: 0x0564 + message length + topology frame bytes + destination address + next hop address + CRC16) to each substation in reverse order from the highest physical slot address (e.g., module 31) to the lowest physical slot address via unicast. The messages are transmitted asynchronously in serial mode at a baud rate of 12.5 Mbps to ensure efficient data communication. After receiving a topology query message, each substation checks if it is its own address. If so, it records the "next address" sent by the master station and returns an acknowledgment message to the master station. After receiving the acknowledgment message, the master station continues to send topology query messages to the next address (module 30), traversing the network in the order of address 31→30→…→1, and finally returns to itself (address 0). By traversing in reverse order, the master station can grasp the entire link topology status and store the topology status in a 32-bit substation online register, with each node occupying 1 bit. The corresponding bit is set when the substation is online and cleared to 0 when it is offline.

[0029] Fault tolerance mechanism: If the master station does not receive an acknowledgment message from the substation within a specified time (e.g., 5ms), the master station will retry a preset number of times (default is 3 times). If no response is received, the master station will skip the substation and continue sending topology query messages to the next substation module. Quickly skipping unresponsive substation modules during reverse traversal avoids delaying the entire topology establishment process, ultimately forming a complete network topology table.

[0030] S2: Token Passing and Data Communication Token mechanism: After the topology is established, the master station first holds the token and passes the token to the substations in the topology order. After each substation obtains the token, it checks whether there are any Ethernet frames to be sent in its SEND BRAM. If there are, it sends them in the specified BLVDS message format and releases the token. The message format for token passing is: 0x0564 + message length + token passing bytes + destination address + next-hop address + CRC16 checksum.

[0031] Token passing interval is dynamically adjusted: If there is no need for BLVDS message transmission, the token passing interval is 5ms (preset maximum value). If there is a need for BLVDS message transmission, the token is passed in real time (interval 0ms) until there is no message transmission on the bus. The token passing interval increases step by step from 0ms, 1ms, 2ms, 3ms, 4ms, to 5ms until the preset maximum value is reached.

[0032] Priority dynamic scheduling: Since each module is connected to the backplane BLVDS bus, each module can monitor the Ethernet frame transmission status of other modules on the bus in real time, count the number of BLVDS messages transmitted on the bus, and calculate the proportion of its own transmitted Ethernet frames in the total transmitted messages.

[0033] If the historical transmission frequency of the current module is less than 30% of the total bandwidth and there are Ethernet frames to be transmitted in its SEND BRAM, the priority of the module will be automatically increased, allowing it to get a transmission opportunity faster in the next token transfer; at this time, the number of Ethernet frames it transmits is determined according to (1 - historical transmission frequency) × (number of frames to be transmitted in SEND BRAM).

[0034] If the current module's historical transmission frequency exceeds 60% of the total bandwidth, the system lowers its priority, requiring it to send a maximum of one Ethernet frame after acquiring a token. This allows the token to be passed to other modules with large amounts of data more quickly. This mechanism ensures that data requiring priority transmission is delivered promptly under high system load, reducing unnecessary waiting time and improving overall communication throughput. In other cases, each module transmits a maximum of two Ethernet frames at a time while holding a token.

[0035] The data transmission message format is: 0x0564 + message length + data bytes sent + destination address + next hop address + CRC16 checksum.

[0036] S3: Token Loss Detection and Topology Reconstruction In this embodiment, the master station continuously monitors the communication status of the backplane BLVDS bus to determine whether the token is in a normal transmission process. If no BLVDS message is detected on the bus within 5ms, or no token is received for the master station within 100ms, the master station determines that the current token has been lost and re-initiates the topology establishment process.

[0037] Furthermore, this embodiment also includes an auxiliary triggering mechanism for substations: if any substation detects that it has not acquired a token within 100ms, it considers itself to have left the network topology. In this case, based on its position in the network, the substation sends an interference signal to the BLVDS bus when the token is passed from the previous hop to the next hop, thereby changing the bus state and prompting the master station to re-initiate the link establishment process. Through the dual monitoring and triggering mechanism of the master station and substations, link problems can be detected more quickly in the event of token anomalies, shortening the system recovery time.

[0038] When the master station determines that a token is lost, it does not immediately perform a full network topology reconstruction. Instead, it first adopts a local repair strategy. Through real-time monitoring, the master station identifies the module A that last held the token and its predecessor module B. Using a reverse traversal mechanism, it only performs topology reconstruction on the local interval between module A and module B, thereby avoiding the overhead of a full network reconstruction.

[0039] If the partial repair is successful, the system will resume normal operation; if the partial repair fails three times in a row, the main station will perform a full network topology reconstruction to ensure the integrity and stability of the overall network topology.

[0040] During each topology reconstruction, the 32-bit bus status counter in the master station automatically increments to record the number of global link establishments. Simultaneously, the master station compares the online registers of the substations before and after link establishment; if a change in the state of a substation is detected, the corresponding substation status counter increments. Through comprehensive analysis of the bus status counter and the substation status counter, abnormal substations can be quickly located or the presence of bus faults can be determined, further improving the system's maintainability and fault tolerance.

[0041] In summary, this invention improves the real-time performance and reliability of inter-module communication by implementing a reverse topology establishment, token passing, dynamic priority scheduling, and local priority topology repair mechanism based on the BLVDS bus under an FPGA architecture. It also reduces hardware complexity and system recovery costs, making it suitable for high-speed and stable communication scenarios in large-scale modular systems.

[0042] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A backplane bus communication method based on FPGA, applied to a communication system consisting of multiple modules interconnected via a backplane BLVDS bus, characterized in that, The method includes: Each module detects its own address signal. The module with address 0 is automatically identified as the master station and is responsible for initiating the establishment of the network topology. The other modules are all sub-stations. The master station sends topology query messages to each substation in reverse order from the highest physical slot address to the lowest physical slot address via unicast, and determines the online status of each substation based on whether an acknowledgment message is received, thus forming a network topology table. After the topology is established, the master station holds the initial token and passes it according to the topology order. After receiving the token, each substation, if it has an Ethernet frame to be sent, encapsulates the Ethernet frame into a BLVDS message and sends it, and releases the token after completion. Based on the historical Ethernet frame transmission frequency and current buffer status of each module on the backplane BLVDS bus, the Ethernet frame transmission opportunity of the module when holding a token is dynamically adjusted. Specifically, if the historical transmission frequency of any module is lower than a preset proportion of the total bandwidth and there are Ethernet frames to be transmitted, the priority of that module is increased to avoid being unable to transmit for a long time. If the historical transmission frequency of any module is higher than a preset proportion, the maximum number of frames that module can transmit when holding a token at one time is limited to improve the overall communication efficiency. The master station continuously monitors the status of the backplane BLVDS bus. If no BLVDS message is transmitted or no token is received within a preset time, it determines that the token is lost and re-initiates the topology establishment process. The master station prioritizes performing topology repair on local areas to reduce the overhead of rebuilding the entire network. If the topology repair of local areas fails for a preset number of consecutive times, the entire network topology is rebuilt.

2. The FPGA-based backplane bus communication method according to claim 1, characterized in that, Each module within the communication system includes: The FPGA chip, as the core control unit, is used to implement communication logic control and data processing; The BLVDS chip, as a physical transceiver, is electrically connected to the BLVDS bus on the backplane to complete the transmission and reception of differential signals. The FPGA chip includes: The Ethernet MAC controller, as a standard Ethernet protocol receiving module, is used to encapsulate and decapsulate Ethernet frames, and interacts with external CPUs or upper-layer processing units through the MII interface. The MAC2BLVDS module is used to implement format adaptation and protocol conversion between Ethernet frames and BLVDS messages. The FPGA chip also includes a token passing module, which is used to implement token-based bus access control logic to ensure that each module has exclusive access to the bus to send data when it holds a token; it also supports token generation, passing and loss detection.

3. The FPGA-based backplane bus communication method according to claim 2, characterized in that, The MAC2BLVDS module specifically includes: The MAC control unit, as an interface logic, interacts with the Ethernet MAC controller to write received Ethernet frames into the SEND BRAM and retrieve data from the RECEIVE BRAM and send it back to the Ethernet MAC controller. The BRAM buffer unit includes SEND BRAM and RECEIVE BRAM, which are used to store Ethernet frames to be sent and Ethernet frames after decapsulation of received BLVDS messages, respectively. The BLVDS control unit is electrically connected to the BLVDS chip at the top and interacts with the BLVDS bus on the backplane via differential signals; it interacts with the SEND BRAM or RECEIVE BRAM at the bottom to complete data encapsulation and decapsulation.

4. The FPGA-based backplane bus communication method according to claim 3, characterized in that, The topology query message includes a message header, message length, topology frame bytes, destination address, next-hop address, and CRC checksum, and is transmitted asynchronously in serial mode.

5. The FPGA-based backplane bus communication method according to claim 1, characterized in that, During topology establishment, the online status of substations is recorded in the register. If a substation fails to return an acknowledgment message within a preset time, the master station will retry the substation a preset number of times. If no acknowledgment message is received, the master station will skip the substation and continue topology traversal.

6. The FPGA-based backplane bus communication method according to claim 1, characterized in that, The token transmission interval increases progressively in the bus idle state until a preset maximum value is reached, and is adjusted to real-time transmission when there is a need for BLVDS message transmission.

7. The FPGA-based backplane bus communication method according to claim 1, characterized in that, The master station continuously monitors the status of the backplane BLVDS bus. If the master station does not detect a BLVDS message within 5ms or does not receive a returned token within 100ms, it determines that the token is lost. Meanwhile, the substation monitors its own token acquisition status in real time. If it detects that it has not acquired a token within 100ms, it is determined that it has left the network topology. At this time, the substation sends an interference signal to the backplane BLVDS bus according to its own position in the network topology when the token is passed from its previous hop to the next hop, so as to prompt the master station to re-establish the link.

8. The FPGA-based backplane bus communication method according to claim 7, characterized in that, The topology repair of the local area includes: the main station determines the module A that last held the token and the module B that was the previous hop of the module through real-time monitoring, and adopts a reverse traversal mechanism to rebuild the topology only for the modules in the interval [B,A]. If topology repair in a local area fails three times in a row, the main station will perform a full network topology reconstruction.

9. The FPGA-based backplane bus communication method according to claim 8, characterized in that, The master station is equipped with a 32-bit bus status counter and a substation status counter. The bus status counter is incremented each time the link is re-established, and the substation status counter is incremented accordingly by comparing the changes in the online registers of the substation before and after the link is established, so as to quickly locate abnormal modules or bus faults.

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