Method for manufacturing thin film transistor, thin film transistor and display panel

Abstract

This invention provides a method for fabricating a thin-film transistor, a thin-film transistor, and a display panel. The fabrication method includes fabricating an active layer, a gate insulating layer, and a gate on a substrate. The active layer includes a channel region and source and drain regions located on opposite sides of the channel region. Low-dose ion implantation is performed on the source and drain regions. The preferred dose range for the low-dose ion implantation is 6E11 / cm². 3 ~5E14 / cm 3 The gate insulating layer is etched with vias to expose at least a portion of the source and drain regions. A metal trace layer is fabricated on the exposed source and drain regions. The metal trace layer is then subjected to plasma treatment using a reducing gas. By using low-injection-dose conductor formation, combined with plasma treatment of the metal trace layer to form ohmic contacts with the source and drain regions, the carrier concentration gradient between the source / drain regions and the channel region is reduced, minimizing carrier diffusion into the channel region and thus ensuring the effective length of the channel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a method for fabricating a thin-film transistor, the thin-film transistor, and a display panel. Background Technology

[0002] In metal-oxide devices, the actual channel length of the active layer is less than the design value due to the source-drain conductor formation process and subsequent high-temperature processes, which affects the device's electrical properties. The diffusion of high carrier concentration from the source and drain into the channel region can lead to a reduction in the effective channel length of the device. Especially in short-channel devices, the change in the effective channel length may directly cause the device to lose its switching characteristics. Summary of the Invention

[0003] In view of this, the present invention aims to provide a method for fabricating a thin-film transistor, a thin-film transistor, and a display panel, which can effectively reduce the reduction in the effective channel length.

[0004] According to one aspect of the inventive concept of the present invention, a method for fabricating a thin-film transistor is provided, comprising: An active layer, a gate insulating layer, and a gate are fabricated on a substrate. The active layer includes a channel region and a source region and a drain region located on both sides of the channel region, respectively. Low-dose ion implantation is performed on the source region and the drain region; The dose range of the low-dose ion implantation is 6E11 / cm. 3 ~5E14 / cm 3 ; The gate insulating layer is etched with vias to expose at least a portion of the source region and at least a portion of the drain region; Metal wiring layers are fabricated on the exposed source and drain regions; The metal trace layer is subjected to plasma treatment using a reducing gas.

[0005] In one embodiment, after the low-dose ion implantation of the source region and the drain region and before the via etching of the gate insulating layer, the method further includes: An interlayer insulating layer is prepared on the gate insulating layer and the gate, and via etching is performed on the interlayer insulating layer.

[0006] In one embodiment, fabricating a metal trace layer on the exposed source and drain regions includes: Multiple metal layers are sequentially fabricated on the exposed source and drain regions; The multiple metal layers are patterned to obtain the metal trace layer.

[0007] In one embodiment, the metal trace layer includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially; Preferably, the first metal layer is Ti; Preferably, the second metal layer is Al; Preferably, the third metal layer is Ti.

[0008] In one embodiment, the plasma treatment of the metal trace layer using a reducing gas includes: After the first metal layer is prepared and before the second metal layer is prepared, the first metal layer is subjected to plasma treatment using a reducing gas.

[0009] In one embodiment, the plasma treatment of the metal trace layer using a reducing gas includes: After the third metal layer is prepared, the multilayer metal layer is subjected to plasma treatment using a reducing gas.

[0010] In one embodiment, the reducing gas includes at least one of hydrogen plasma and argon-hydrogen mixed plasma; Preferably, the temperature of the plasma treatment is greater than or equal to 150°C.

[0011] In one embodiment, the fabrication of the active layer, the gate insulating layer, and the gate on the substrate includes: A crystalline oxide semiconductor material layer is deposited on a substrate, and the active layer is obtained by etching and patterning. A gate insulating layer is prepared on the active layer; Gate metal is deposited on the gate insulating layer, etched and patterned, and a gate structure is formed. Preferably, the process further includes, prior to depositing the crystalline oxide semiconductor material layer on the substrate: A buffer layer is deposited on the substrate, wherein the active layer is deposited on the buffer layer.

[0012] In one embodiment, depositing a buffer layer on the substrate includes: A buffer material is deposited on the substrate using chemical vapor deposition or physical vapor deposition; Preferably, the buffer material includes at least one of silicon nitride, silicon dioxide, aluminum oxide, and gallium nitride.

[0013] According to another aspect of the inventive concept of the present invention, a thin-film transistor is also provided, which is prepared by the thin-film transistor preparation method described in the foregoing embodiments.

[0014] According to another aspect of the inventive concept of the present invention, a display panel is also provided, including thin-film transistors as described in the foregoing embodiments.

[0015] According to the embodiment of the present invention, the thin-film transistor fabrication method, the thin-film transistor, and the display panel reduce the carrier concentration gradient between the source / drain region and the channel region by using low-injection-dose conductor formation, thereby reducing carrier diffusion into the channel region and ensuring the effective length of the channel. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a thin-film transistor in the prior art, as well as a schematic diagram of the carrier concentration after the source region, drain region, and channel region are conductive.

[0017] Figure 2 This is a flowchart of a method for fabricating a thin-film transistor according to an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the structure of a thin-film transistor according to an embodiment of the present invention, as well as a schematic diagram of the carrier concentration after the source region, drain region, and channel region are conductive.

[0019] Figure 4 This is a sub-flowchart of operation S240 in the fabrication method of a thin-film transistor according to another embodiment of the present invention.

[0020] Figure 5 This is a sub-flowchart of operation S240 in the fabrication method of a thin-film transistor according to another embodiment of the present invention.

[0021] Figure 6 This is a sub-flowchart of sub-operation S211 in the fabrication method of a thin-film transistor according to an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of the structure of a display device according to an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures: 10-Display Panel 100-Buffer layer; 200 - Active layer; 210-Source region; 220-Ditch area; 230 - Drain region; 300 - Gate insulating layer; 400-gate; 500 - Interlayer insulation layer; 600 - Metallic trace layer; 610 - First metal layer; l1 - Actual trench length; l2 - Design trench length; L1 - Carrier concentration after conductor formation in the source, drain, and channel regions in existing technologies; L2 - Carrier concentration after the source, drain, and channel regions are conductive in the embodiments of this application. Detailed Implementation

[0024] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. In the accompanying drawings and the following description, at least some well-known structures and techniques have not been shown in order to avoid unnecessarily obscuring the invention; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0025] In the description of this invention, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of the present invention. It should also be noted in the description of the present invention that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0027] In related technologies, the actual channel length of the active layer in metal-oxide devices is less than the design value due to the source-drain conductor formation process and subsequent high-temperature processes, affecting the device's electrical performance. This is especially true for short-channel devices, where changes in the effective channel length can directly cause the device to lose its switching characteristics. For example... Figure 1As shown, the metal oxide device includes, from bottom to top, a substrate (not shown), a buffer layer 100, an active layer 200, a gate insulating layer 300, a gate 400, an interlayer insulating layer 500, and a metal wiring layer 600. The active layer 200 includes a channel region 220 located in the middle and a source region 210 and a drain region 230 located on both sides of the channel region 220, respectively.

[0028] In the fabrication of metal-oxide devices, the source region 210 and drain region 230 need to be conductive to ensure good conductivity. Specifically, dopants need to be injected into the source region 210 and drain region 230 to increase the concentration of charge carriers (electrons or holes). After the conductive process of the source region 210 and drain region 230, the charge carrier concentration of the source region 210 and drain region 230 is significantly higher than that of the channel region 220. This concentration difference generates a diffusion driving force, prompting the high-concentration charge carriers in the source region 210 and drain region 230 to diffuse into the channel region 220. When the high-concentration charge carriers in the source region 210 and drain region 230 diffuse into the channel region 220, they will form an additional conductive region at the channel edge. This additional conductive region will shorten the effective channel length of the device (the length of the channel portion that can actually participate in conduction between the source and drain, i.e., l1), thereby causing changes in the device performance, such as increased switching speed and increased power consumption.

[0029] In addition, during the manufacturing process of metal oxide devices, a series of high-temperature processing steps are usually required, such as annealing and sintering. These high-temperature processing steps may further aggravate the influence of the source region 210 and drain region 230 conductor process on the active layer 200, resulting in a deviation (i.e., ΔL) between the actual value of the channel length (i.e., the actual channel length l1) and the design value (i.e., the design channel length l2).

[0030] As can be seen from the above, in the manufacturing process of metal oxide devices, the actual length of the channel region is often smaller than the designed length. Controlling the difference ΔL between the two is very important and is an important parameter affecting the performance and stability of the device.

[0031] Figure 2 This is a flowchart of a method for fabricating a thin-film transistor according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a thin-film transistor according to an embodiment of the present invention, as well as a schematic diagram of the carrier concentration after the source region, drain region, and channel region are conductive.

[0032] To address the aforementioned technical problems, according to one aspect of the inventive concept of the present invention, a method for fabricating a thin-film transistor is provided, such as... Figure 2 and Figure 3As shown, it includes: operations S210 to S220.

[0033] Operation S210 includes: fabricating an active layer 200, a gate insulating layer 300, and a gate 400 on a substrate (not shown in the figure). The active layer 200 includes a channel region 220 and a source region 210 and a drain region 230 located on both sides of the channel region.

[0034] Operation S220 includes: performing low-dose ion implantation on the source region 210 and the drain region 230 to achieve conductor formation; wherein the dose range of the low-dose ion implantation includes 6E11 / cm. 3 ~5E14 / cm 3 This is to reduce the carrier concentration between the source region 210, the drain region 230, and the channel region 220.

[0035] Operation S230 includes: performing via etching on the gate insulating layer 300 to expose the source region 210 and the drain region 230.

[0036] Operation S240 includes: fabricating a metal trace layer on the source region 210 and the drain region 230.

[0037] Operation S250 includes: using a reducing gas to perform plasma treatment on the metal trace layer to achieve ohmic contact between the source region 210 and the metal trace layer, and between the drain region 230 and the metal trace layer, wherein the metal trace layer is capable of storing H element to reduce H element diffusion to the source region 210 and the drain region 230.

[0038] In one embodiment, after the gate structure is fabricated, the source region 210 and drain region 230 need to be conductor-enhanced to form a high concentration of conductive charge carriers (electrons or holes) in the source region 210 and drain region 230, thus becoming good conductors. The concentration and distribution of these charge carriers will directly affect the device performance, such as on-resistance, switching speed, and leakage current. After forming a high concentration of charge carriers in the source region 210 and drain region 230, these regions will form good ohmic contacts with the subsequently deposited metal layer. This allows current to flow smoothly through the metal-semiconductor interface without generating significant additional resistance.

[0039] In this embodiment, by using a low-dose injection method to conduct the source and drain electrodes, the carrier concentration gradient between the source / drain region and the channel region 220 can be reduced, preventing carriers from the source / drain electrodes from diffusing into the channel region and thus affecting the effective channel length of the device. However, the reduction of the carrier concentration gradient will affect the barrier height between the metal and the semiconductor, thereby affecting the formation of ohmic contacts, that is, affecting the ohmic contact effect between the source region, the drain region and the metal trace layer. By using a reducing gas to perform plasma treatment on the metal trace layer, ohmic contacts between the source region, the drain region and the metal trace layer can be achieved.

[0040] In one embodiment, after operation S230 and before operation S240, the operation further includes: preparing an interlayer insulating layer on the gate insulating layer and the gate, and performing via etching on the interlayer insulating layer.

[0041] In this embodiment, an interlayer insulating layer 500 is disposed on the gate 400 and the gate insulating layer 300. The interlayer insulating layer 500 is made of a material with low dielectric constant and high mechanical strength, such as porous silicon dioxide or organic polymer, to reduce interlayer capacitance and signal delay. The interlayer insulating layer and the gate insulating layer are etched to form channels (vias) for providing wiring.

[0042] Compared to the high injection dose methods (e.g., typically 1E15 / cm³) commonly used in related technologies for source-drain conductor formation, the solution of this invention optimizes the injection dose (e.g., 1E15 / cm³). Figure 1 L1 and Figure 3 The L2 in the middle can be used to discover related technologies ( Figure 1 The concentration difference between the source region 210, drain region 230, and channel region 220 in the ) is relatively large. Therefore, ions implanted in the source region 210 and drain region 230 tend to diffuse more easily into the channel region 220. And... Figure 3 In the diagram, the concentration difference between source region 210, drain region 230, and channel region 220 in L2 is relatively small, and the diffusion degree of ions implanted in source region 210 and drain region 230 into channel region 220 is much smaller than that in channel region 220. Figure 1 As shown, the difference ΔL between the actual value and the design value of the channel region 220 in this embodiment of the invention is much smaller than that in the prior art, thereby ensuring the stability and yield of the device.

[0043] In this embodiment, low-dose ion implantation is indirectly implanted into the source region 210 and the drain region 230 through the gate insulating layer 300. The gate insulating layer 300 serves as an insulating layer between the gate 400 and the source and drain, ensuring that the gate voltage can control the carrier concentration of the channel region 220 without directly affecting the source and drain.

[0044] During ion implantation, it is crucial to ensure that the gate insulating layer 300 remains undamaged. This can be achieved by adjusting the parameters of the ion implanter, such as ion energy and angle. Simultaneously, during photoresist coating and photolithography, it is also essential to ensure that the photoresist does not coat the gate insulating layer, preventing damage to the gate insulating layer 300 during photoresist removal. Furthermore, during subsequent cleaning and annealing processes, it is necessary to ensure that the integrity of the gate insulating layer 300 is not compromised. This can be achieved by selecting appropriate cleaning solutions and annealing conditions.

[0045] In this embodiment, ohmic contact between the metal trace layer and the source region 210 and the drain region 230 is achieved by plasma treatment of the metal trace layer. The H storage function of the metal trace layer is used to prevent excessive H from diffusing to the source and drain of the active layer 200 and affecting the effective channel length of the device.

[0046] In one embodiment, the reducing gas includes at least one of hydrogen plasma and argon-hydrogen mixed plasma.

[0047] In one embodiment, hydrogen has a high diffusion coefficient in titanium at ≥150°C. In this embodiment, the metal trace layer is subjected to H2 plasma treatment at a temperature greater than or equal to 150°C to accelerate the decomposition rate of H2 molecules in the plasma, increase the number of active H atoms and H⁺ ions, thereby ensuring that they can react more effectively with the Ti metal layer on the surface of the first metal layer 610. Simultaneously, this also helps to improve the microstructure and chemical composition of the Ti metal layer at the source / drain contact interface, further reducing contact resistance and improving the quality of the ohmic contact.

[0048] In one embodiment, a gate metal, such as molybdenum (Mo), titanium (Ti), or nickel (Ni), is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques, and high-precision patterning is achieved through photolithography and etching techniques.

[0049] In one embodiment, the fabrication of the active layer 200, the gate insulating layer 300, and the gate 400 on the substrate in operation S210 includes sub-operations S211 to S213.

[0050] Sub-operation S211 includes: depositing a crystalline oxide semiconductor material layer on a substrate and etching a pattern to obtain an active layer 200.

[0051] Sub-operation S212 includes: preparing a gate insulating layer 300 on the active layer 200.

[0052] Sub-operation S213 includes: depositing gate metal on the gate insulating layer 300, etching patterning, and forming gate 400.

[0053] In this embodiment, the crystalline oxide semiconductor material layer is the key material for forming the channel region 220, and the gate insulating layer 300 is used to isolate the gate 400 and the channel region 220 to prevent current leakage from the gate 400.

[0054] In one embodiment, in sub-operation S213, the gate is patterned through steps such as coating, exposure and etching to define the shape and position of the gate 400.

[0055] In one embodiment, after the active layer, the gate insulating layer, and the gate are sequentially fabricated on the substrate, an interlayer insulating layer is deposited, and then via etching is performed on the deposited interlayer insulating layer and the gate insulating layer to prepare for subsequent metal wiring.

[0056] In one embodiment, prior to depositing a crystalline oxide semiconductor material layer on the substrate, a buffer layer 100 is deposited on the substrate to provide a good interface with subsequent layers and to provide isolation, wherein the active layer 200 is deposited on the buffer layer 100.

[0057] In one embodiment, depositing a buffer layer 100 on a substrate includes: depositing a buffer material on the substrate using chemical vapor deposition or physical vapor deposition.

[0058] In this embodiment, the buffer layer 100 can improve the lattice mismatch between the substrate and the active layer 200, thereby improving the performance and stability of the device. Furthermore, the buffer layer 100 also serves to relieve stress, isolate the device, and optimize electrochemical performance. For example, by adjusting the composition and thickness of the buffer layer 100, the electrical performance of the device can be optimized, such as increasing carrier mobility and reducing resistance.

[0059] Preferably, the cushioning material includes at least one of silicon nitride, silicon dioxide, aluminum oxide, or gallium nitride.

[0060] In one embodiment, fabricating a metal trace layer on the exposed source region 210 and drain region 230 includes: sequentially fabricating a plurality of metal layers on the exposed source region 210 and drain region 230, and patterning the plurality of metal layers to obtain a metal trace layer.

[0061] In one embodiment, the metal trace layer includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially. Preferably, the first metal layer is Ti; preferably, the second metal layer is Al; preferably, the third metal layer is Ti.

[0062] In this embodiment, the first metal layer 610 is a thin titanium (Ti) layer. On the one hand, it can serve as a barrier layer to prevent the subsequent aluminum (Al) layer from reacting adversely with the underlying oxide semiconductor layer or gate insulating layer 300; on the other hand, it serves as an adhesion layer to improve the adhesion between the aluminum layer and the underlying layer.

[0063] The second metal layer has low resistivity and good ductility, serving as a trace material and the main conductive channel, providing a low-resistance current path.

[0064] The third metal layer is a thin titanium layer, which mainly serves as a protective layer to prevent the aluminum layer from being oxidized or corroded during subsequent processing, and also helps to improve the overall mechanical strength.

[0065] In this embodiment, the patterning process of the three metal layers includes processes such as coating, exposure, development and etching, and resist removal, which will not be described in detail here.

[0066] Figure 4 This is a sub-flowchart of operation S240 in the fabrication method of a thin-film transistor according to another embodiment of the present invention.

[0067] In one embodiment, plasma treatment of the metal trace layer in operation S240 includes: sub-operations S410 to S430.

[0068] Sub-operation S410 includes: fabricating a first metal layer 610 on the source region 210 and the drain region 230.

[0069] Sub-operation S420 includes: plasma treatment of the first metal layer 610 using a reducing gas.

[0070] Sub-operation S430 includes: sequentially preparing a second metal layer and a third metal layer on the first metal layer 610.

[0071] That is, after the first metal layer 610 is prepared and before the second metal layer is prepared, the first metal layer 610 is subjected to plasma treatment with a reducing gas. Preferably, the first metal layer 610 is subjected to H2 plasma treatment.

[0072] In this embodiment, compared with the prior art, the conductor formation of the source region 210 and drain region 230 of the active layer 200 is achieved by low-dose implantation, which makes it more difficult to form stable chemical bonds at the source-drain-metal contact interface, resulting in increased contact resistance, which will affect the current transmission capability of the device and reduce the performance of the device.

[0073] After the deposition of the first metal layer 610 is completed, the device is placed in a plasma reaction chamber under a vacuum or inert gas environment. High-purity H2 gas is introduced into the reaction chamber, and the H2 concentration in the reaction chamber is adjusted by controlling the gas flow rate and pressure. The H2 gas is excited using an energy source such as radio frequency (RF) or microwave, causing it to decompose into a plasma state containing H atoms, H⁺ ions, H2 molecules, and electrons. Under certain temperature and pressure, the H atoms and H⁺ ions in the plasma react with the Ti metal layer on the surface of the first metal layer 610. H atoms can penetrate into the area where the Ti metal layer contacts the source and drain electrodes, while H⁺ ions may promote surface cleaning and activation through bombardment, thereby making it easier to achieve ohmic contact between the first metal layer 610 and the source region 210 and the drain region 230.

[0074] In addition, the first metal layer 610, which has been treated with H2 plasma, has H storage function, which can prevent excessive H from diffusing to the source and drain electrodes of the active layer and affecting the effective channel length of the device.

[0075] Figure 5 This is a sub-flowchart of operation S240 in the fabrication method of a thin-film transistor according to another embodiment of the present invention.

[0076] In one embodiment, plasma treatment of the metal trace layer in operation S240 includes sub-operations S510 to S520.

[0077] Sub-operation 510: A first metal layer 610, a second metal layer, and a third metal layer are sequentially fabricated on the source region 210 and the drain region 230.

[0078] Sub-operation 520: Plasma treatment of multilayer metal layers using reducing gas.

[0079] That is, after the third metal layer is prepared, the multilayer metal layers are subjected to plasma treatment using a reducing gas. Preferably, the multilayer metal layers are treated with H2 plasma.

[0080] In this embodiment, unlike the previous embodiment, H2 plasma treatment is performed after all the multilayer metals of the metal wiring layer have been prepared. Compared with the previous embodiment, the H2 plasma treatment time needs to be adjusted accordingly to ensure the microstructure and chemical composition of the first metal layer 610 and the source / drain contact interface.

[0081] In one embodiment, the temperature at which the metal trace layer is subjected to H2 plasma treatment is greater than or equal to 150°C.

[0082] Figure 6 This is a sub-flowchart of sub-operation S410 in a method for fabricating a thin-film transistor according to an embodiment of the present invention.

[0083] In one embodiment, such as Figure 6 As shown, the active layer obtained by etching and patterning in sub-operation S211 includes sub-operations S610 to S630.

[0084] Sub-operation S610 includes: coating a photoresist layer on a crystalline oxide semiconductor material layer.

[0085] Sub-operation S620: Exposure, transferring the pattern of source region 210 and drain region 230 onto the photoresist.

[0086] Sub-operation S630: Use developer to remove the photoresist from the exposed area, etch and pattern it.

[0087] In this embodiment, physical or chemical methods are used to remove the active layer portions not protected by photoresist to form the desired circuit pattern. The etching process requires precise control to ensure the accuracy of the pattern and the performance of the device.

[0088] According to another aspect of the inventive concept of the present invention, a thin-film transistor is also provided, which is prepared by the thin-film transistor preparation method described in the foregoing embodiments.

[0089] In one embodiment, a thin-film transistor includes: a substrate, and an active layer 200, a gate insulating layer 300, a gate 400, and an interlayer insulating layer 500 sequentially stacked on the substrate. The active layer 200 includes a channel region 220 and a source region 210 and a drain region 230 located on both sides of the channel region 220, respectively. A via is provided on the gate insulating layer 300, and the via connects the source region 210 and the drain region 230. A metal wiring layer is at least partially disposed in the via, and the metal wiring layer and the source region 210 and the metal wiring layer and the drain region 230 are ohmic contacts. The metal wiring layer is capable of storing hydrogen (H) to reduce the diffusion of H to the source and drain regions.

[0090] In one embodiment, the thin-film transistor further includes a buffer layer 100 disposed between the substrate and the active layer 200.

[0091] In this embodiment, the buffer layer 100 can improve the lattice mismatch between the substrate and the active layer 200, thereby improving the performance and stability of the device. Furthermore, the buffer layer also serves to relieve stress, isolate the device, and optimize electrochemical performance. For example, by adjusting the composition and thickness of the buffer layer, the electrical performance of the device can be optimized, such as increasing carrier mobility and reducing resistance.

[0092] Preferably, the cushioning material includes at least one of silicon nitride, silicon dioxide, aluminum oxide, or gallium nitride.

[0093] In one embodiment, the thin-film transistor further includes an interlayer insulating layer 500 disposed on the gate 400 and the gate insulating layer 300. The interlayer insulating layer 500 is made of a material with low dielectric constant and high mechanical strength, such as porous silicon dioxide or an organic polymer, to reduce interlayer capacitance and signal delay. The interlayer insulating layer and the gate insulating layer are etched to form channels (vias) for wiring.

[0094] According to another aspect of the inventive concept of the present invention, a display panel is also provided, including thin-film transistors as described in the foregoing embodiments.

[0095] In one embodiment, the display panel can be either a flexible or a rigid display panel. The light extraction method of the display panel can be either bottom-emitting or top-emitting.

[0096] In one embodiment, the display panel can be applied to any product or component with display functionality, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, navigator, e-book reader, player, laptop computer, in-vehicle computer, desktop computer, or set-top box.

[0097] In one embodiment, the display panel can be applied to a display device, which can be a variety of electronic display products, including but not limited to at least one of mobile phones, tablet computers, e-book readers, media players, digital cameras, laptop computers, in-vehicle computers, desktop computers, set-top boxes, smart TVs, and wearable devices.

[0098] This application also provides a display device. Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 7 As shown, the display device includes the display panel 10 provided in any of the above embodiments.

[0099] In addition, depending on actual needs, the display device may also include other structures such as a touch panel.

[0100] It should be noted that, for clarity, the complete structure of the display panel and display device described above is not presented. To achieve the necessary functions of the display panel or display device, those skilled in the art can configure other structures according to specific application scenarios.

[0101] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a thin-film transistor, characterized in that, include: An active layer, a gate insulating layer, and a gate are sequentially fabricated on a substrate. The active layer includes a channel region and a source region and a drain region located on both sides of the channel region, respectively. Low-dose ion implantation is performed on the source region and the drain region; wherein the dose range of the low-dose ion implantation is 6E11 / cm. 3 ~5E14 / cm 3 ; The gate insulating layer is etched with vias to expose at least a portion of the source region and at least a portion of the drain region; Metal wiring layers are fabricated on the exposed source and drain regions; The metal trace layer is subjected to plasma treatment using a reducing gas.

2. The method for fabricating a thin-film transistor according to claim 1, characterized in that, The procedure further includes, after low-dose ion implantation of the source and drain regions and before via etching of the gate insulating layer: An interlayer insulating layer is prepared on the gate insulating layer and the gate, and via etching is performed on the interlayer insulating layer.

3. The method for fabricating a thin-film transistor according to claim 1, characterized in that, The step of fabricating a metal trace layer on the exposed source and drain regions includes: Multiple metal layers are sequentially fabricated on the exposed source and drain regions; The multiple metal layers are patterned to obtain the metal trace layer.

4. The method for fabricating a thin-film transistor according to claim 3, characterized in that, The metal trace layer comprises a first metal layer, a second metal layer, and a third metal layer stacked sequentially.

5. The method for fabricating a thin-film transistor according to claim 4, characterized in that, The first metal layer is Ti.

6. The method for fabricating a thin-film transistor according to claim 4, characterized in that, The second metal layer is Al.

7. The method for fabricating a thin-film transistor according to claim 4, characterized in that, The third metal layer is Ti.

8. The method for fabricating a thin-film transistor according to claim 4, characterized in that, The plasma treatment of the metal trace layer using a reducing gas includes: After the first metal layer is prepared and before the second metal layer is prepared, the first metal layer is subjected to plasma treatment with a reducing gas; or After the third metal layer is prepared, the multilayer metal layers are subjected to plasma treatment using a reducing gas.

9. The method for fabricating a thin-film transistor according to claim 8, characterized in that, The reducing gas includes at least one of hydrogen plasma and argon-hydrogen mixed plasma.

10. The method for fabricating a thin-film transistor according to claim 9, characterized in that, The plasma treatment temperature is greater than or equal to 150°C.

11. The method for fabricating a thin-film transistor according to claim 1, characterized in that, The fabrication of the active layer, gate insulating layer, and gate on the substrate includes: A crystalline oxide semiconductor material layer is deposited on a substrate, and the active layer is obtained by etching and patterning. A gate insulating layer is prepared on the active layer; Gate metal is deposited on the gate insulating layer, etched and patterned, and a gate structure is formed.

12. The method for fabricating a thin-film transistor according to claim 11, characterized in that, The process further includes, prior to depositing a crystalline oxide semiconductor material layer on the substrate: A buffer layer is deposited on the substrate, wherein the active layer is deposited on the buffer layer.

13. The method for fabricating a thin-film transistor according to claim 11, characterized in that, The deposition of a buffer layer on the substrate includes: A buffer material is deposited on the substrate using chemical vapor deposition or physical vapor deposition.

14. The method for fabricating a thin-film transistor according to claim 13, characterized in that, The buffer material includes at least one of silicon nitride, silicon dioxide, aluminum oxide, and gallium nitride.

15. A thin-film transistor, characterized in that, It is prepared by the method of any one of claims 1 to 14.

16. A display panel, characterized in that, Including the thin-film transistor as described in claim 15.

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