A silicon substrate preparation process of a photovoltaic cell, a photovoltaic cell preparation process and a photovoltaic cell

Abstract

The application discloses a silicon substrate preparation process of a photovoltaic cell, a preparation process of the photovoltaic cell and the photovoltaic cell. The silicon substrate preparation process of the photovoltaic cell comprises a first texturing preparation step: a region of a silicon wafer for forming a first texturing is cleaned and textured to form the first texturing, the distance between the top of the first texturing and the back surface of the photovoltaic cell is less than or equal to the distance between the region without the first texturing and the back surface of the photovoltaic cell, the outer surface of the first texturing comprises a third surface and a fourth surface extending along the axial direction thereof, and the interval between the third surface and the fourth surface gradually decreases in the direction away from the back surface of the photovoltaic cell. The application further comprises a step of electroplating the outer surface of the first texturing to form a grid line. The photovoltaic cell obtained by using the process can fully utilize light energy, greatly improves Isc, and reduces contact resistance. The grid line of the application has a large contact area with the first texturing, has many stress points, and the pull-off force is also improved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a silicon substrate fabrication process for photovoltaic cells, a photovoltaic cell fabrication process, and a photovoltaic cell. Background Technology

[0002] In photovoltaic cells, the mainstream technology still involves screen printing silver paste onto a textured silicon substrate, followed by sintering to form metal electrodes. However, this process results in uneven and irregular grid lines, causing severe diffuse reflection when light shines on them, leading to a significant loss of light energy.

[0003] Furthermore, the light energy reflected by the grid lines of existing photovoltaic cells is not fully and effectively utilized by the photovoltaic cells. A schematic diagram of the shape of existing metal grid lines can be found here. Figure 11 The light will be reflected directly by the top surface of the grid lines and will not reach the light-receiving surface of the photovoltaic cell, resulting in a large amount of wasted light energy.

[0004] Especially in the region of the sub-grid lines, the loss of light energy caused by the grid lines themselves is very serious. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a silicon substrate fabrication process for photovoltaic cells, comprising: a first textured surface preparation step: the first textured surface is used to set grid lines; the area of ​​the silicon wafer used to form the first textured surface is cleaned and textured to form the first textured surface; the distance between the top of the first textured surface and the back surface of the photovoltaic cell is less than or equal to the distance between the area without the first textured surface and the back surface of the photovoltaic cell; the distance between the bottom surface of the first textured surface and the back surface of the photovoltaic cell is less than the distance between the area without the first textured surface and the back surface of the photovoltaic cell, so that the light reflected from the outer surface of the first grid lines formed on the surface of the first textured surface can be maximally irradiated onto the photovoltaic cell; the first textured surface is formed on the side of the silicon wafer closest to the front surface of the photovoltaic cell; the outer contour shape of the first textured surface is cylindrical; the outer surface of the first textured surface includes a third surface and a fourth surface extending along its axial direction; the distance between the third surface and the fourth surface gradually decreases in the direction away from the back surface of the photovoltaic cell. This application utilizes the texturing process in photovoltaic cell manufacturing to form a cylindrical first textured surface. By utilizing the structural and positional settings of the first textured surface, and by electroplating grid lines onto the outer surface of the first textured surface in subsequent processes, light can be reflected back to the photovoltaic cell after illuminating the grid lines, thus enabling full utilization of light energy.

[0006] Furthermore, it also includes: The first mask preparation step on the silicon wafer surface; The selective removal of the first mask involves selectively removing the first mask on both sides of the area where the first textured surface is located, etching the outer surface of the silicon wafer in the maskless area, and forming the first textured surface.

[0007] Furthermore, it also includes the step of removing the entire first mask.

[0008] Furthermore, it also includes a second textured surface preparation step, wherein the second textured surface is located on the outer surface of the silicon wafer, and the distance between the top of the second textured surface (13) and the back of the photovoltaic cell is greater than or equal to the distance between the top of the first textured surface and the back of the photovoltaic cell, and the second textured surface preparation step is located before or after the first textured surface preparation step.

[0009] This invention also provides a photovoltaic cell fabrication process, which includes the aforementioned silicon substrate fabrication process for photovoltaic cells, and further includes a step of electroplating to form grid lines on the outer surface of the first textured surface, wherein the light reflected from the outer surface of the grid lines can be irradiated onto the photovoltaic cell. The photovoltaic cell fabricated using this process exhibits a significantly improved Isc (Inductance Scale) and reduced contact resistance. Furthermore, the grid lines of this invention have a large contact area with the first textured surface, resulting in more stress points and improved pull-out force.

[0010] Furthermore, before the step of electroplating to form gate lines on the outer surface of the first textured surface, a step of selectively forming a second mask in an area outside the area where the first textured surface is formed is included. This exposes the area where the first textured surface is located, facilitating subsequent electroplating to form gate lines.

[0011] Furthermore, prior to the step of electroplating to form grid lines on the outer surface of the first textured surface, the following steps are also included: In the step of setting a target area mask on the outer surface of the first textured surface, after setting the target area mask, silicon nitride is deposited on the entire outer surface of the silicon substrate, and then the target area mask is removed to expose the first textured surface.

[0012] Furthermore, at least one functional layer is disposed on the outer surface of the silicon substrate, which can also cover the first textured surface.

[0013] Furthermore, the gate line includes a copper layer and a metal reflective layer located outside the copper layer. The metal reflective layer may be a silver layer and / or a tin layer.

[0014] The present invention also provides a photovoltaic cell, which is prepared by the silicon substrate preparation process of the photovoltaic cell described above or the preparation process of the photovoltaic cell described above. Attached Figure Description

[0015] Figure 1 This is a process flow diagram of a silicon substrate according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the processing technology of a silicon substrate according to an embodiment of the present invention; Figure 3 This is a process flow diagram of the silicon substrate fabrication according to another embodiment of the present invention; Figure 4 This is a schematic diagram of the processing technology of a silicon substrate according to another embodiment of the present invention; Figure 5 This is a flowchart of the electrode processing technology for a silicon substrate according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the electrode processing technology for a silicon substrate according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the electrode processing technology for a silicon substrate according to another embodiment of the present invention; Figure 8 This is a schematic diagram of the electrode processing technology for a silicon substrate according to another embodiment of the present invention; Figure 9 This is a schematic diagram showing the shape of the electrode and substrate body according to an embodiment of the present invention; Figure 10 This is a three-dimensional structural diagram of the substrate body and the first textured surface according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the external shape of metal grid lines in the prior art.

[0016] In the picture: 1. Substrate body; 11. First textured surface; 111. Third surface; 112. Fourth surface; 2. First grid line; 21. First surface; 22. Second surface; 12. Recessed area; 13. Second napped surface; 3. Electrode; 4. Second grid line. Detailed Implementation

[0017] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0018] Example 1: This embodiment describes a silicon substrate fabrication process for a photovoltaic cell, including a first textured surface 11 fabrication step. The first textured surface 11 is used to set grid lines. The first textured surface 11 fabrication step includes cleaning and texturing the area of ​​the silicon wafer used to form the first textured surface 11 to form the first textured surface 11. The distance between the top of the first textured surface 11 and the back surface of the photovoltaic cell is less than or equal to the distance between the area without the first textured surface 11 and the back surface of the photovoltaic cell. The bottom surface of the first textured surface 11 (… Figure 10The distance between the plane marked P (located on the side of the first textured surface 11 near the back of the photovoltaic cell) and the back of the photovoltaic cell is less than the distance between the area where the first textured surface 1 is not provided and the back of the photovoltaic cell.

[0019] The first textured surface 11 is formed on the front side of the silicon wafer near the photovoltaic cell. The outer contour of the first textured surface 11 is cylindrical. The outer surface of the first textured surface 11 includes a third surface 111 and a fourth surface 112 extending along its axial direction. The distance between the third surface 111 and the fourth surface 112 gradually decreases in the direction away from the back side of the photovoltaic cell.

[0020] This invention gradually reduces the distance between the third surface 111 and the fourth surface 112 of the first textured surface 11 in the direction away from the back of the photovoltaic cell, and the distance between the bottom surface of the first textured surface 11 and the back of the photovoltaic cell is smaller than the distance between the area without the first textured surface 11 and the back of the photovoltaic cell. Therefore, when the grid lines are subsequently formed on the first textured surface 11, the light illuminating the grid lines can be fully utilized by the photovoltaic cell, minimizing the light obstruction caused by the grid lines. Furthermore, this application only sets the first textured surface 11 in the area where the grid lines are set to the aforementioned structure, while other areas of the silicon substrate retain the existing ordinary textured structure of the silicon substrate (e.g., pyramid structure). Therefore, the current transmission path is minimized, ensuring that it does not affect the battery performance, and at the same time, the light obstruction caused by the grid lines is minimized.

[0021] In some embodiments, the outer surface of the first grid line 2 includes a first surface 21 and a second surface 22 extending along the axial direction of the first grid line 2, the first surface 21 and the second surface 22 intersecting directly or indirectly at one end away from the back of the photovoltaic cell. For example, the outer contour of the first grid line 2 is a triangular prism. In some embodiments, the outer surface of the first grid line 2 further includes a fifth surface, which is connected to the first surface 21 and the second surface 22 respectively. The fifth surface can be a plane, an arc surface, a curved surface, or an irregular surface. Accordingly, the outer surface contour of the first grid line 2 can be a prism with a trapezoidal cross-section, a prism with a rounded conical cross-section, or a prism with other irregular cross-sectional shapes.

[0022] In some embodiments, depending on the structural arrangement of the first textured surface 11, the distance between the top of the first textured surface 11 and the back of the photovoltaic cell can be set to be smaller than the distance between the area where the first textured surface 11 is not provided and the back of the photovoltaic cell. For example, the bottom surface where the first textured surface 11 is provided can be set at... Figure 10 The recessed area 12 in the first textured surface 11 is designed so that the light reflected from the outer surface of the first grid line 2 formed on the surface of the first textured surface 11 can be irradiated onto the photovoltaic cell to the greatest extent.

[0023] In other possible implementations, the distance between the top of the first textured surface 11 and the back of the photovoltaic cell can be set to be equal to the distance between the area without the first textured surface 11 and the back of the photovoltaic cell. For example, when the cross-section of the first textured surface 11 is trapezoidal, under the premise of ensuring that the distance between the top of the first textured surface 11 and the back of the photovoltaic cell is equal to the distance between the area without the first textured surface 11 and the back of the photovoltaic cell, the area of ​​the top surface of the first textured surface 11 can be made as small as possible, and the distance between the bottom surface of the first textured surface 11 and the back of the photovoltaic cell is still smaller than the distance between the area without the first textured surface 11 and the back of the photovoltaic cell. Therefore, it can still be ensured that the light reflected by the first textured surface 11 is basically irradiated into the photovoltaic cell.

[0024] In some embodiments, the grid lines disposed on the outer surface of the first velvet surface 11 can be main grid lines or secondary grid lines, and the length direction of the first velvet surface 11 is correspondingly consistent with the setting direction of the grid lines. In other possible embodiments, the border can also be configured with a structure similar to that of the first velvet surface 11.

[0025] In some embodiments, the silicon substrate fabrication process for photovoltaic cells is performed in the following order: A first mask is fabricated on the surface of the silicon wafer. Figure 2 The steps for the regions on the upper and lower outer surfaces of the substrate in Figure (c); The step of selectively removing the first mask: selectively removing the first mask in the area where the first textured surface 11 is located, and etching the outer surface of the silicon wafer in the maskless area. Figure 2 As shown in Figure (d) or Figure 4 (as shown in Figure d), and forms the first nap 11; The step of removing all the first mask.

[0026] In some embodiments, the silicon substrate fabrication process of the photovoltaic cell of the present invention further includes a step of fabricating a second textured surface 13. The second textured surface 13 may be disposed on the upper and lower outer surfaces of the silicon wafer, and the distance between it and the back surface of the photovoltaic cell is greater than or equal to the distance between the first textured surface 11 and the back surface of the photovoltaic cell. The step of fabricating the second textured surface 13 is located before or after the step of fabricating the first textured surface 11.

[0027] See appendix Figure 1 and Figure 2 When the preparation step of the second textured surface 13 is performed before the preparation step of the first textured surface 11, the silicon wafer is directly textured on both sides before the "first mask preparation step of the silicon wafer surface" is performed. As a result, the silicon substrate prepared has several second textured surface 13 structures on the side near the back of the photovoltaic cell and the area near the front of the photovoltaic cell outside the first textured surface 11.

[0028] See appendix Figure 3 and Figure 4 When the preparation step of the second textured surface 13 is after the preparation step of the first textured surface 11, the silicon wafer is first polished on both sides, and after the double-sided polishing, the first mask preparation step is performed on the surface of the silicon wafer. After the first textured surface 11 preparation step is completed, all the first masks are removed, and finally the second textured surface 13 preparation step is performed in the area outside the first textured surface 11.

[0029] In some embodiments, the first textured surface 11 is formed by selectively removing the first mask on both sides of the area where the first textured surface 11 is located, and then using a tank immersion process to etch away the outer surface of the silicon wafer in the maskless area.

[0030] Example 2: This embodiment describes a photovoltaic cell fabrication process, which includes the silicon substrate fabrication process for photovoltaic cells described in Embodiment 1, and further includes a step of electroplating to form grid lines on the outer surface of the first textured surface 11. Light reflected from the outer surface of the grid lines can be irradiated onto the photovoltaic cell. Utilizing the structural shape of the first textured surface 11 of this invention, the shape retention effect during grid line formation by electroplating is improved. At the same time, the grid line structure formed by electroplating further ensures that the light irradiated onto the grid lines is irradiated onto the photovoltaic cell to the maximum extent.

[0031] In some embodiments, the grid line formed on the outer surface of the first velvet surface 11 is the first grid line 2, and the grid line intersecting with the first grid line 2 is the second grid line 4. The second grid line 4 can also be formed by electroplating and electroplating simultaneously with the first grid line 2; or the main body of the second grid line 4 can be prepared by screen printing, and electroplating can be continued on the outside of the main body of the second grid line 4 during the formation of the first grid line 2 to form the structure of the second grid line 4.

[0032] See appendix Figure 5 and 6 In some embodiments, the photovoltaic cell fabrication process of the present invention further includes a step of selectively forming a non-target area mask in a region outside the area where the first textured surface 11 is located, before the step of electroplating to form grid lines on the outer surface of the first textured surface 11. This exposes the area where the first textured surface 11 is located, facilitating subsequent electroplating to form grid lines.

[0033] In some embodiments, the step of selectively forming a second mask in a region other than the area where the first textured surface 11 is formed includes masking the entire outer surface of the silicon substrate where the first textured surface 11 and the second textured surface 13 have been formed, and then removing only the mask in the area where the first textured surface 11 is formed, thereby leaving the mask in the area other than the first textured surface 11, thereby exposing the area where the first textured surface 11 is located.

[0034] For example, after coating the mask onto the outer surface of a silicon substrate using a printing process, a drying and curing process is performed under atmospheric conditions. The drying temperature is 95℃~100℃, the drying time is 400~500 seconds, and the mask thickness is 12μm~14μm. The grid line area pattern is then exposed using an exposure machine. The wavelength range of the exposure light is 355nm~365nm, and the exposure energy range is 145mj / cm²~150mj / cm². The exposed solar cell undergoes a development process. The developer can be a 1.2%~1.5% sodium carbonate solution, the development temperature is 30℃~35℃, the operating spray pressure range is 3.0Kg / cm²~3.5Kg / cm², and the time is 210-240 seconds. This process yields a solar cell with a patterned linewidth of 10~30μm.

[0035] For other possible implementations, see Figure 7 Alternatively, a non-target area mask can be directly fabricated in the area outside the first textured surface 11 of the silicon substrate, thereby directly exposing the area where the first textured surface 11 is located, so as to carry out the subsequent step of electroplating on the first textured surface 11 to form gate lines.

[0036] In some implementations, the non-target area mask is a mask made of organic materials, such as photoresist, insulating ink, wax, etc., which can be fabricated by inkjet printing and exposure development. The non-target area mask can also be an inorganic material, such as silicon nitride or silicon oxide, and formed by PVD or CVD deposition.

[0037] See appendix Figure 8 As shown, before the step of electroplating to form gate lines on the outer surface of the first textured surface 11, the following process can be used to expose the first textured surface 11: a target area mask is set on the outer surface of the first textured surface 11, and after the target area mask is set, silicon nitride is deposited on the entire outer surface of the silicon substrate. Then the target area mask is removed to expose the first textured surface 11, and electroplating can then be performed on the surface of the first textured surface 11.

[0038] For example, the mask setup for the target area can refer to the aforementioned mask setup for the outer surface of the silicon substrate. Silicon nitride deposition is performed using physical vapor deposition (PECVD), with an operating temperature of 180℃–200℃ and an operating pressure of 1.8 Torr–2 Torr. The flow rate ratio of the operating gas precursors—silane (SiH4), ammonia (NH3), and nitrogen (N2)—is SiH4:NH3:N2 = 1:5:5. The radio frequency (RF) power is 5W–50W and the frequency is 13.56MHz, with an operating time of 100–500 seconds. The thickness of the silicon nitride layer is 30nm–100nm.

[0039] After silicon nitride deposition, a mask removal process is performed, with the temperature controlled at 60℃~65℃, sodium carbonate concentration at 2.8%~3%, operating spray pressure at 3.0Kg / cm²~3.5Kg / cm², and operating time at 80 seconds~400 seconds, thereby removing the mask layer of the first textured surface 11 region.

[0040] Electroplating can be performed with or without a seed layer, and can employ plating schemes such as rack plating, horizontal plating, and tank plating; no specific restrictions are imposed here.

[0041] In some embodiments, the grid lines electroplated on the outer surface of the first textured surface 11 include a copper layer. In other possible embodiments, the electroplated grid lines also include a metal reflective layer located outside the copper layer. The metal reflective layer can be a silver layer and / or a tin layer to protect the copper layer while increasing the smoothness of the grid lines and improving their light reflection effect. By providing a metal reflective layer, the light-trapping effect of the photovoltaic cell of the present invention can be made more prominent, and the use of chemical silver (or tin) plating further increases the specular reflection effect of light while protecting the copper layer.

[0042] In some embodiments, the current density for electroplating to form the copper layer is 5 ASD to 20 ASD, the electroplating time is 200 seconds to 2000 seconds, and the electroplating temperature ranges from 30°C to 40°C. The electroplating solution composition is: copper sulfate 130 g / L to 200 g / L; sulfuric acid 40 g / L to 100 g / L; and chloride ions 30 mg / L to 80 mg / L. The thickness of the electroplated copper layer on the first gate line 2 can range from 5 μm to 15 μm.

[0043] In some embodiments, the plating current density during tin plating is 3 ASD to 20 ASD, the plating time is 60 seconds to 600 seconds, the plating temperature ranges from 20°C to 30°C, and the tin layer thickness ranges from 2 μm to 5 μm. The plating solution contains: 50 g / L to 100 g / L stannous sulfate, 40 g / L to 160 g / L sulfuric acid, and a pH value of 2 to 6.

[0044] In some embodiments, the electroplating solution used for silver electroplating has the following composition: silver nitrate 15-25 g / L, KOH 50 g / L-100 g / L, electroplating current density 0.1 ASD-3 ASD, pH between 8 and 9, electroplating time between 30 and 300 seconds, temperature between 20°C and 30°C, and silver layer thickness between 0.1 μm and 5 μm.

[0045] In some embodiments, before gate line electroplating, at least one functional layer may be formed on the outer surface of the silicon substrate. This functional layer can cover the entire outer surface of the silicon substrate and also cover the first textured surface 11 (e.g., the functional layer includes a passivation layer, a doped layer, and an antireflection layer). Thus, according to... Figure 8 The antireflection layer of a photovoltaic cell prepared by this process can simultaneously contain an ITO layer and a silicon nitride layer; while according to Figure 6 and Figure 7 The antireflection layer of the photovoltaic cell prepared by the process is only an ITO layer.

[0046] The photovoltaic cell of the present invention can be a common crystalline silicon solar cell such as a PERC cell, an HJT cell, or a TOPCon cell.

[0047] The performance of the photovoltaic cell of this invention is compared with that of conventional HJT (screen-mesh) cells and conventional (electroplated) cells. The cell uses 210... The 105mm (220.48cm² area after chamfering) HJT solar cell was prepared using the conventional HJT process for the conventional cell (screen mesh) and the electroplating process for the conventional cell (electroplated). The silicon wafer structure remained unchanged, and the prepared cells were used for light injection and testing.

[0048] The difference between this application and the prior art lies in that the aforementioned silicon substrate structure is fabricated during the cleaning and texturing stage, and then an electrode 3 is formed by electroplating on the outer surface of the first textured surface 11. The resulting solar cell is then used for light injection and testing. The comparison results are shown in Table 1. Table 1 Performance comparison of the photovoltaic cells in this application with conventional photovoltaic cells

[0049] As shown in Table 1, the Jsc (short-circuit current) of the photovoltaic cell of this application is significantly increased, while Rs (series resistance) is significantly reduced. Compared with conventional HJT cells using electroplating to form the electrode 3, the performance of the cell of this application is further improved. This is because the structure of the first textured surface 11 of the silicon substrate prepared by the process of this application and the recessed setting on the silicon substrate structure reduce the shading of light caused by the grid lines themselves, thereby maximizing the utilization of solar energy.

[0050] Example 3: This embodiment is a photovoltaic cell, which is prepared by the silicon substrate preparation process of the photovoltaic cell in Embodiment 1 or the photovoltaic cell preparation process in Embodiment 2.

[0051] In some implementations, see Appendix Figure 9-11As shown, the photovoltaic cell of this embodiment includes a substrate body 1 and at least one first grid line 2 disposed on the front side of the substrate body 1 near the photovoltaic cell. The outer surface contour of the first grid line 2 is cylindrical, and the outer surface of the first grid line 2 includes a first surface 21 and a second surface 22 extending along the axial direction of the first grid line 2. The distance between the first surface 21 and the second surface 22 gradually decreases along the direction away from the back side of the photovoltaic cell. The first grid line 2 is formed on the outer surface of the first textured surface 11 by an electroplating process. Therefore, by cleverly utilizing the original outer contour shape of the first textured surface 11 and forming a plating layer on the outer surface of the first textured surface 11, it is easy to achieve a smooth mirror effect on the outer surface of the first grid line 2, and it is also possible to achieve the fabrication effect of ultra-fine grid lines. The outer surfaces of the first surface 21 and the second surface 22 of the first grid line 2 are smooth surfaces, and the light reflected from the outer surface of the first grid line 2 can be irradiated onto the photovoltaic cell.

[0052] In some embodiments, the photovoltaic cell also includes a plurality of second grid lines 4 intersecting with the first grid line 2. The first grid line 2 and the second grid line 4 can be formed by simultaneous electroplating, or the main body of the second grid line 4 can be screen printed and then electroplated together with the first grid line 2, or it can be formed simultaneously with the first grid line 2 during the electroplating process of the metal reflective layer.

[0053] This application minimizes the scattering of sunlight hitting the grid surface by setting the first grid line 2 as a column and setting the first surface 21 and the second surface 22 as smooth surfaces, and allows the sunlight to be fully reflected by the first grid line 2 so that it can be absorbed and utilized by the photovoltaic cell again.

[0054] See appendix for details. Figure 10 In some embodiments, the substrate body 1 has at least one recessed region 12 that is recessed from the front side of the photovoltaic cell to the back side, and each recessed region 12 is provided with at least one first textured surface 11. That is, the location of the first textured surface 11 is recessed from the surface of the substrate body 1 near the front side of the photovoltaic cell to the back side near the photovoltaic cell.

[0055] The bottom surface of the first textured surface 11 is located in the recessed area 12, and the bottom surface of the first textured surface 11 is located closer to the back of the photovoltaic cell than the bottom surface of the second textured surface 13. In some embodiments, the height difference m between the top of the second textured surface 13 and the top of the first textured surface 11 is greater than or equal to 0 (that is, the distance between the top of the first textured surface 11 and the back of the photovoltaic cell is less than or equal to the distance between the top of the second textured surface 13 and the back of the photovoltaic cell). Therefore, the light reflected by the first textured surface 11 can re-enter the photovoltaic cell, achieving full utilization of the light energy incident on the front of the photovoltaic cell with extremely low light loss.

[0056] In some embodiments, the distance W between the outer edge of the first textured surface 11 and the bottom edge of the recessed area 12 is defined as W, the width X of the bottom of the first textured surface 11 is defined as X, where W ≥ 0 μm and X is 5-20 μm, and the width (or diameter) d of the bottom of the second textured surface 13 is defined as d, where d is 1-3 μm. This dimensional configuration of the first textured surface 11 and the second textured surface 13 facilitates the processing of the battery substrate, maximizes the utilization efficiency of solar energy, and improves the overall performance of the battery. In some embodiments, the second textured surface 13 can be pyramidal in shape.

[0057] In some embodiments, a third textured surface 14 is provided on both sides of the first textured surface 11, located on the bottom wall of the recessed area 12. By providing the third textured surface 14, the electrode 3 and the first textured surface 11 can form a more stable force-bearing structure.

[0058] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A process for fabricating a silicon substrate for photovoltaic cells, characterized in that, include: First textured surface (11) preparation steps: The first textured surface (11) is used to set grid lines. The silicon wafer is cleaned and textured to form the first textured surface (11). The distance between the top of the first textured surface (11) and the back of the photovoltaic cell is less than or equal to the distance between the area without the first textured surface (11) and the back of the photovoltaic cell. The distance between the bottom of the first textured surface (11) and the back of the photovoltaic cell is less than the distance between the area without the first textured surface (11) and the back of the photovoltaic cell. The first textured surface (11) is formed on the front side of the silicon wafer near the photovoltaic cell. The outer contour of the first textured surface (11) is cylindrical. The first textured surface (11) extends in a direction parallel to the surface of the silicon wafer. The outer surface of the first textured surface (11) includes a third surface (111) and a fourth surface (112) extending along its axial direction. The distance between the third surface (111) and the fourth surface gradually decreases in the direction away from the back side of the photovoltaic cell.

2. The silicon substrate fabrication process for photovoltaic cells according to claim 1, characterized in that, Also includes: The first mask preparation step on the silicon wafer surface; The step of selectively removing the first mask is as follows: the first mask in the area where the first textured surface (11) is located is selectively removed, the outer surface of the silicon wafer in the unmasked area is etched, and the first textured surface (11) is formed.

3. The silicon substrate fabrication process for photovoltaic cells according to claim 2, characterized in that, It also includes the step of removing the entire first mask.

4. The silicon substrate fabrication process for photovoltaic cells according to claim 2, characterized in that, It also includes a step of preparing a second textured surface (13), which is located on the outer surface of the silicon wafer, and the distance between the top of the second textured surface (13) and the back of the photovoltaic cell is greater than or equal to the distance between the top of the first textured surface (11) and the back of the photovoltaic cell. The step of preparing the second textured surface (13) is located before or after the step of preparing the first textured surface (11).

5. A process for manufacturing photovoltaic cells, characterized in that, The silicon substrate fabrication process for the photovoltaic cell according to any one of claims 1-4 further includes the step of electroplating to form grid lines on the outer surface of the first textured surface (11), wherein the light reflected from the outer surface of the grid lines can be irradiated onto the photovoltaic cell.

6. The photovoltaic cell manufacturing process according to claim 5, characterized in that, Before the step of electroplating to form grid lines on the outer surface of the first textured surface (11), the method further includes a step of selectively forming a non-target area mask in an area outside the setting area of ​​the first textured surface (11).

7. The photovoltaic cell fabrication process according to claim 5, characterized in that, Before the step of electroplating to form grid lines on the outer surface of the first textured surface (11), the following steps are also included: In the step of setting a target area mask on the outer surface of the first textured surface (11), after setting the target area mask, silicon nitride is deposited on the entire outer surface of the silicon substrate, and then the target area mask is removed to expose the first textured surface (11).

8. The photovoltaic cell fabrication process according to claim 6 or 7, characterized in that, At least one functional layer is also disposed on the outer surface of the silicon substrate, which can also cover the first textured surface (11).

9. The photovoltaic cell manufacturing process according to claim 6 or 7, characterized in that, The gate line includes a copper layer and a metal reflective layer located outside the copper layer.

10. A photovoltaic cell, characterized in that, It is prepared by the silicon substrate preparation process of the photovoltaic cell according to any one of claims 1-4 or the photovoltaic cell preparation process according to any one of claims 5-9.

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