Metal semiconductor contact structure and preparation method thereof, solar cell and photovoltaic module

Abstract

The invention relates to the technical field of photovoltaic power generation, in particular to a metal semiconductor contact structure and a preparation method thereof, a solar cell and a photovoltaic module. The metal semiconductor contact structure comprises a metal electrode and a doped polycrystalline silicon layer which are in contact with each other, and a contact area of the metal electrode and the doped polycrystalline silicon layer comprises a first contact area and a second contact area; the surface of the doped polycrystalline silicon layer in the first contact region is of a plane structure, and the first contact region is provided with a first carrier transport structure which comprises conductive metal particles arranged on the plane structure; a pit structure with a pit is arranged on the surface of the doped polycrystalline silicon layer in the second contact region, and a second carrier transport structure is arranged in the pit and comprises a conductive eutectic and a conductive crystal which are connected with each other; the metal electrode, the conductive metal particles and the conductive crystal have the same metal element, and the conductive eutectic comprises a metal element and a silicon element; the ratio of the area S1 of the planar structure in the contact region to the area S2 of the pit structure in the contact region is (40: 60)-(98: 2).

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic power generation, and particularly to a metal-semiconductor contact structure, a preparation method thereof, a solar cell and a photovoltaic module. BACKGROUND

[0002] The doped polysilicon layer plays an important role in transporting carriers and passivating defects in a solar cell. However, when the doped polysilicon layer is arranged on a polished surface of a silicon substrate, the efficiency of the solar cell cannot be effectively improved, especially when the solar cell is applied to a photovoltaic module. The reason is that the contact interface between the doped polysilicon layer and the metal electrode is not good, and it is difficult to balance the carrier transport capacity and passivation capacity, resulting in that the photovoltaic module with the solar cell cannot effectively improve the photoelectric conversion efficiency. SUMMARY

[0003] To solve the above technical problems, the present application discloses a metal-semiconductor contact structure, a preparation method thereof, a solar cell and a photovoltaic module. The contact structure of the planar doped polysilicon layer and the metal electrode is optimized and improved to balance the carrier transport capacity and passivation capacity of the metal-semiconductor contact structure, and effectively improve the photoelectric conversion efficiency of the solar cell.

[0004] In a first aspect, the present application provides a metal-semiconductor contact structure, which comprises a metal electrode and a doped polysilicon layer in contact with each other, and a contact area between the metal electrode and the doped polysilicon layer comprises a first contact region and a second contact region outside the first contact region.

[0005] In the first contact region, the surface of the doped polysilicon layer for contacting the metal electrode is a planar structure, and a first carrier transport structure is arranged in the first contact region, and the first carrier transport structure comprises a plurality of conductive metal particles arranged on the planar structure.

[0006] In the second contact region, the surface of the doped polysilicon layer for contacting the metal electrode is a pit structure with a plurality of pits, and the recess direction of the pits is toward the internal direction of the doped polysilicon layer itself, and a second carrier transport structure is arranged in the pits, and the second carrier transport structure comprises a conductive eutectic body connected to the recess surface of the pits and a conductive crystalline body extending from the conductive eutectic body toward the metal electrode.

[0007] The metal electrode, the conductive metal particles and the conductive crystalline body all have the same metal element, and the conductive eutectic body comprises the metal element and a silicon element.

[0008] The area of the planar structure in the contact region is S1, the area of the pit structure in the contact region is S2, and the range of S1:S2 is (40:60)-(98:2).

[0009] Further, the range of S1:S2 is (70:30)-(90:10); preferably, the range of S1:S2 is 65:35.

[0010] Optionally, the doped polysilicon layer in the first contact region includes a plurality of independent sub-structures, and gaps exist between adjacent sub-structures, and the plurality of sub-structures are spliced to form the planar structure.

[0011] Optionally, the planar structure is a continuous structure.

[0012] Further, the doped polysilicon layer in the first contact region includes a plurality of sub-structures, and the maximum distance between any two points on the outer contour of a single sub-structure is 50-1000 nm in the thickness direction of the doped polysilicon layer.

[0013] Further, a plurality of pits are arranged adjacent to form a pit group, the pit structure includes a plurality of pit groups, and the maximum distance between any two points on the opening outer contour of the pit group is 10-1500 nm in the thickness direction of the doped polysilicon layer.

[0014] Further, the depth of the pit in the thickness direction of the doped polysilicon layer is H, 0 nm<H≤200 nm, the thickness of the doped polysilicon layer is 50-500 nm, and H is less than the thickness of the doped polysilicon layer.

[0015] Further, the metal-semiconductor contact structure further includes a glass phase distributed in the contact region.

[0016] Part of the glass phase is distributed in the first contact region, and the first carrier transport structure further includes a plurality of conductive metal particles wrapped in the glass phase; part of the glass phase is located in the pit.

[0017] Further, the metal element includes a silver element.

[0018] Optionally, the doped element in the doped polysilicon layer is an N-type conductive element or a P-type conductive element.

[0019] Further, the metal-semiconductor contact structure further includes a passivation layer arranged on the doped polysilicon layer, and the metal electrode and the doped polysilicon layer are in contact through the passivation layer.

[0020] In a second aspect, the embodiments of the present application provide a method for preparing the metal-semiconductor contact structure as described in the first aspect, and the method comprises the following steps:

[0021] printing an electrode paste on the doped polysilicon layer; wherein the electrode paste comprises a glass phase, a metal material and an organic carrier, and the softening temperature of the glass phase is 300-400℃;

[0022] low-temperature pre-baking: before or after the step of printing the electrode paste, pre-baking treatment is performed at 100-300℃;

[0023] low-temperature sintering the electrode paste; the low-temperature sintering is performed in stages of a first plateau segment temperature, rising to a first peak segment temperature, and falling to a second plateau segment temperature, the heating temperature of the first plateau segment and the second plateau segment is 250-350℃, the sintering peak temperature of the first peak segment is 300-400℃, and the sintering peak temperature of the first peak segment is greater than the temperature of the first plateau segment and the second plateau segment, and the low-temperature sintering time is 5-20s;

[0024] high-temperature sintering the electrode precursor after low-temperature sintering, so that the electrode precursor is converted into the metal electrode, and the metal-semiconductor contact structure is formed between the metal electrode and the doped polysilicon layer; the high-temperature sintering is performed in stages of a third plateau segment temperature, rising to a second peak segment temperature, and falling to a fourth plateau segment temperature, the heating temperature of the third plateau segment and the fourth plateau segment is 700-800℃, the sintering peak temperature of the second peak segment is 750-850℃, and the sintering peak temperature of the second peak segment is greater than the temperature of the third plateau segment and the fourth plateau segment, and the low-temperature sintering time is 10-20s.

[0025] Optionally, the doped polysilicon layer is prepared by an LPCVD process, and in the metal-semiconductor contact structure, the doped polysilicon layer located in the first contact area comprises a plurality of independent sub-structures, and adjacent sub-structures have boundaries, and a plurality of the sub-structures are spliced to form a flat doped polysilicon layer.

[0026] Optionally, the doped polysilicon layer is prepared by a PECVD process, and in the metal-semiconductor contact structure, the doped polysilicon layer located in the first contact area is a continuous and flat integral structure.

[0027] Further, the preparation method further comprises: before the step of printing the electrode paste on the doped polysilicon layer, a passivation layer is made on the doped polysilicon layer, and the electrode paste is printed on the passivation layer; after the steps of the low-temperature pre-drying, the low-temperature sintering and the high-temperature sintering, at least part of the electrode precursor is in contact with the doped polysilicon layer after passing through the passivation layer.

[0028] In a third aspect, the embodiments of the present application further provide a solar cell, comprising:

[0029] a silicon substrate;

[0030] a doped polysilicon layer on the silicon substrate;

[0031] a metal electrode in contact with the doped polysilicon layer, the metal electrode and the doped polysilicon layer form a metal semiconductor contact structure as described in the first aspect.

[0032] Further, the solar cell further comprises a dielectric layer between the silicon substrate and the doped polysilicon layer, the dielectric layer and the doped polysilicon layer form a passivation contact structure.

[0033] Further, the silicon substrate has a flat area, and the doped polysilicon layer is located in the flat area.

[0034] In a fourth aspect, the embodiments of the present application provide a photovoltaic module, comprising the solar cell as described in the third aspect.

[0035] Compared with the prior art, the present application has at least the following beneficial effects:

[0036] By improving the metal semiconductor contact structure in the solar cell, the present application can achieve a balanced and balanced effect between better passivation performance, lower contact resistance and more stable and reliable carrier transport structure combination capability. This is reflected not only in the improvement of the photoelectric conversion efficiency of the solar cell, but also in the maintenance of the efficiency improvement of the solar cell end after the solar cell is welded and assembled into a photovoltaic module. This is conducive to the large-scale application of such batteries in power stations, improving energy efficiency and reducing power generation costs. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1is a structural schematic diagram of a solar cell according to an embodiment of the present application;

[0039] Figure 2 is Figure 1 is an enlarged schematic diagram of the structure at A in FIG. 1 (directions reversed);

[0040] Figure 3 is an SEM image of a doped polysilicon layer in a metal-semiconductor contact structure according to an embodiment of the present application;

[0041] Figure 4 is an SEM image of a doped polysilicon layer in a solar cell according to an embodiment 1 of the present application;

[0042] Figure 5 is an SEM image of a doped polysilicon layer in a solar cell according to an embodiment 2 of the present application.

[0043] Explanation of Reference Signs:

[0044] 1, silicon substrate; 2, doped polysilicon layer; 21, planar structure; 210, substructure; 211, gap; 22, pit structure; 220, pit group; 221, pit; 3, metal electrode; 4, passivation layer; 5, dielectric layer; 6, semiconductor layer;

[0045] 100, metal-semiconductor contact structure; 100A, first contact region; 100B, second contact region; 110, first carrier transport structure; 111, electrically conductive metal particle; 120, second carrier transport structure; 130, glass phase. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0047] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used for better description of the present application and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0048] Moreover, the above-mentioned terms, in addition to being used to indicate the positional or spatial relationship, can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in this application can be understood according to the specific circumstances.

[0049] In addition, the terms "mount", "set", "provided with", "connected", "connected" should be broadly understood. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication between two devices, elements or components. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0050] In addition, the terms "first", "second", etc. are mainly used to distinguish different devices, elements or components (the specific types and structures can be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise stated, the meaning of "multiple" is two or more.

[0051] In a solar cell, a doped polysilicon layer can be used in combination with a very thin dielectric layer (such as a silicon oxide tunnel oxide layer) as a passivated contact structure in a solar cell, which plays a role in interface passivation. At the same time, the doped polysilicon layer can also be in ohmic contact with the metal electrode, which transports the carriers in the silicon substrate to the metal electrode, and plays a role in carrier transport.

[0052] However, the applicant found that the application of the doped polysilicon layer to the polished silicon substrate flat surface process did not achieve the desired efficiency of the solar cell. Especially after assembling the solar cell into a photovoltaic module, the efficiency of the photovoltaic module was not significantly improved.

[0053] The surface of the silicon substrate is polished to form a flat surface without obvious protrusions instead of a textured surface such as a pyramid structure. The doped polysilicon layer formed on the flat surface is also a flat film structure. However, after the metal electrode is formed on the flat doped polysilicon layer to form a metal-semiconductor contact structure, a large number of ablation pits are formed on the surface of the doped polysilicon layer due to the formation of the metalized electrode, so that the originally flat surface of the doped polysilicon layer becomes uneven. Although the uneven surface increases the surface area of the doped polysilicon layer and provides more attachment surfaces for carrier transport structures, which is beneficial to improve the conductivity of the metal-semiconductor contact structure and reduce the contact resistance, the large-area structural damage leads to serious recombination of carriers at the contact interface between the doped polysilicon layer and the metal electrode, resulting in poor passivation performance of the solar cell, and ultimately the photoelectric conversion efficiency of the solar cell cannot be effectively improved.

[0054] After a large amount of research and exploration, the applicant proposes a new structure of a metal-semiconductor contact structure and a preparation method thereof, a solar cell, and a photovoltaic module to solve the above problems. Since the metal-semiconductor contact structure of the embodiments of the present application is applied to a solar cell (especially to a crystalline silicon solar cell), the metal-semiconductor contact structure will be introduced when the solar cell of the embodiments of the present application is introduced below, and the metal-semiconductor contact structure will not be described again.

[0055] The embodiments of the present application provide a solar cell with a metal-semiconductor contact structure. In combination with Figure 1 and Figure 2 shown, Figure 1 is a structural schematic diagram of a first solar cell according to an embodiment of the present application, Figure 2 is Figure 1 an enlarged schematic diagram of the structure at A.

[0056] The solar cell comprises:

[0057] a silicon substrate 1;

[0058] a doped polysilicon layer 2, the doped polysilicon layer 2 being arranged on the silicon substrate 1;

[0059] a metal electrode 3, the metal electrode 3 being in contact with the doped polysilicon layer 2.

[0060] That is, the mutual contact between the doped polysilicon layer 2 and the metal electrode 3 forms a metal semiconductor contact structure 100. Here, the mutual contact between the doped polysilicon layer 2 and the metal electrode 3 is a physical contact, that is, a direct contact between the two structures. It can be understood that the mutual contact between the doped polysilicon layer 2 and the metal electrode 3 can be a partial or full mutual contact between the doped polysilicon layer 2 and the metal electrode 3. For example, when the doped polysilicon layer 2 is provided as a full layer on the silicon substrate 1, the metal electrode 3 is a patterned structure, and thus part of the structure of the doped polysilicon layer 2 is in contact with the metal electrode 3. For another example, when the doped polysilicon layer 2 is provided as a patterned layer on the silicon substrate 1, the metal electrode 3 is provided on the patterned doped polysilicon layer 2, and thus the patterned regions of the doped polysilicon layer 2 and the metal electrode 3 can be provided correspondingly, that is, full mutual contact between the doped polysilicon layer 2 and the metal electrode 3, or the width of the doped polysilicon layer 2 is slightly greater than that of the metal electrode 3, that is, most of the doped polysilicon layer 2 is used to contact the metal electrode 3.

[0061] In the metal semiconductor contact structure 100, the doped polysilicon layer 2 is a film layer in which a doping element is doped into a polysilicon layer, and the doping element can enhance the transport capacity of the doped polysilicon layer 2 for electron carriers or hole carriers. The doping element can be an N-type conductive element or a P-type conductive element. For example, the doped polysilicon layer 2 is an N-type doped polysilicon layer 2, and the doping element of the N-type doped polysilicon layer 2 can include at least one of a phosphorus element, an antimony element or an arsenic element; for another example, the doped polysilicon layer 2 is a P-type doped polysilicon layer 2, and the doping element of the P-type doped polysilicon layer 2 can include at least one of a boron element, an indium element or a gallium element. In addition, the metal electrode 3 can be a silver electrode, that is, the main metal element of the metal electrode 3 is a silver element. It can be understood that the metal electrode 3 can also contain a trace amount of impurity elements in addition to the main metal element, for example, the silver electrode can contain a trace amount of metal aluminum impurities (for example, less than or equal to 0.1wt% of metal aluminum impurities in the silver electrode).

[0062] In the metal semiconductor contact structure 100, the doped polysilicon layer 2 is a film layer in which a doping element is doped into a polysilicon layer, and the doping element can enhance the transport capacity of the doped polysilicon layer 2 for electron carriers or hole carriers. The doping element can be an N-type conductive element or a P-type conductive element. For example, the doped polysilicon layer 2 is an N-type doped polysilicon layer 2, and the doping element of the N-type doped polysilicon layer 2 can include at least one of a phosphorus element, an antimony element or an arsenic element; for another example, the doped polysilicon layer 2 is a P-type doped polysilicon layer 2, and the doping element of the P-type doped polysilicon layer 2 can include at least one of a boron element, an indium element or a gallium element. In addition, the metal electrode 3 can be a silver electrode, that is, the main metal element of the metal electrode 3 is a silver element. It can be understood that the metal electrode 3 can also contain a trace amount of impurity elements in addition to the main metal element, for example, the silver electrode can contain a trace amount of metal aluminum impurities (for example, less than or equal to 0.1wt% of metal aluminum impurities in the silver electrode). Figure 2 Figure 2 is Figure 1 an enlarged schematic view of the structure at position A in FIG. 1, and is explained more conveniently in combination with the accompanying drawings, Figure 2 is Figure 1 the structure on the back surface of the silicon substrate in FIG. 1 is inverted. The contact region between the metal electrode 3 and the doped polysilicon layer 2 includes a first contact region 100A and a second contact region 100B outside the first contact region 100A.

[0063] ​In the first contact region 100A, the surface of the doped polysilicon layer 2 for contacting the metal electrode 3 is a planar structure 21, and the first contact region 100A has a first carrier transport structure 110, which includes a plurality of conductive metal particles 111 arranged on the planar structure 21. The surface of the doped polysilicon layer 2 for contacting the metal electrode 3 (which can also be understood as the contact interface between the doped polysilicon layer 2 and the metal electrode 3) in this contact region is a structurally complete planar structure 21, which has the advantages of fewer surface defects and fewer recombination centers, thereby enabling the doped polysilicon layer 2 to exhibit excellent passivation performance. At the same time, the first contact region has a first carrier transport structure 110 for transporting carriers, which includes a plurality of conductive metal particles 111 arranged on the planar structure 21. Although these conductive metal particles 111 can play a certain role in carrier transport, the bonding strength between them and the doped polysilicon layer 2 is generally low. This relatively low mechanical bonding capability affects the degree of improvement in the carrier transport capability of the solar cell, especially in the component end. In the process of welding a plurality of solar cells to form a photovoltaic module, the above-mentioned conductive metal particles 111 are prone to fall off from the doped polysilicon layer 2 due to the welding conditions, so that the efficiency improvement effect of the solar cell cannot be effectively gained in the photovoltaic module.

[0064] For the above-mentioned situation, the present application solves the problem by setting the relevant structure of the second contact region 100B and controlling the area ratio of the relevant structures in the first contact region 100A and the second contact region 100B.

[0065] In the second contact region 100B, the surface of the doped polysilicon layer 2 for contacting the metal electrode 3 is a pit structure 22 having a plurality of pits 221, and the recess direction of the pits 221 is toward the interior of the doped polysilicon layer 2 itself, and the second contact region 100B has a second carrier transport structure 120 in the pits 221, which includes a conductive eutectic crystal connected to the recess surface of the pits 221 and a conductive crystalline body extending from the conductive eutectic crystal toward the metal electrode 3.

[0066] Among them, the metal electrode 3, the conductive metal particles 111, and the conductive crystalline body all have the same metal element, and the conductive eutectic crystal includes the above-mentioned metal element and a silicon element. Taking silver as an example, the metal electrode 3 can be a silver electrode, the conductive metal particles 111 can be silver nanoparticles, and the conductive crystalline body can be crystalline metal silver formed by crystallization of silver. This crystalline metal silver has higher carrier transport capability than silver nanoparticles. In addition, the conductive eutectic crystal includes silver and silicon, i.e., the conductive eutectic crystal is a eutectic crystal formed by co-crystallization of silver and silicon, which also has higher carrier transport capability than silver nanoparticles.

[0067] As can be seen, in the second contact region 100B, since the second carrier transport structure 120 in the pit 221 adopts the structure of the conductive eutectic and the conductive crystal extending from the conductive eutectic and growing towards the metal electrode 3, on the one hand, the carrier transport capacity of the two structures is stronger than that of the conductive metal particles 111 in the first contact region 100A, so that the second carrier transport structure 120 can serve as the main structure for carrier transport, and the first carrier transport structure 110 serves as the auxiliary structure for carrier transport, which can effectively improve the conductivity between the doped polysilicon layer 2 and the metal electrode 3 and reduce the contact resistance; on the other hand, the binding stability between the conductive eutectic and the recessed surface of the pit 221 is stronger than that between the metal conductive particles and the surface of the doped polysilicon layer 2, which makes the mechanical binding performance between the second carrier transport structure 120 and the doped polysilicon layer 2 better, thereby facilitating the performance improvement at the end of the solar cell to be maintained and amplified at the end of the assembly.

[0068] As for the influence of the surface of the doped polysilicon layer 2 for contacting the metal electrode 3 in the second contact region 100B due to the pit structure 22 on the passivation performance, the embodiment of the present application controls the planar structure 21 of the first contact region 100A and the pit structure 22 of the second contact region 100B within a certain area ratio range after a large number of studies. Specifically, the area of the planar structure 21 in the contact region is S1, the area of the pit structure 22 in the contact region is S2, and the range of S1:S2 is (40:60)~(98:2). It can be understood that the ratio of S1 to S2 includes any point value within the above range, for example, S1:S2 is 40:60, 45:55, 50:50, 55:45, 60:40, 70:30, 75:25, 80:20, 85:15, 90:10, 95:5 or 98:2. Controlling the ratio of S1 to S2 within the above range can greatly preserve the passivation performance of the doped polysilicon layer 2 of the first contact region 100A and promote the effective improvement of the open-circuit voltage and other performances of the solar cell. At the same time, the second carrier transport structure 120 of the second contact region 100B can be used to greatly reduce the contact resistance between the doped polysilicon layer 2 and the metal electrode 3 and improve the stability of the mechanical structure, thereby reducing the series resistance of the solar cell and improving the fill factor and other performances.

[0069] In general, through the joint action of the above structural improvement and the area ratio control, the metal-semiconductor contact structure 100 can achieve a balanced effect between better passivation performance, lower contact resistance, and more stable and reliable carrier transport structure combination capability. This is reflected in not only the improvement of the photoelectric conversion efficiency of the solar cell, but also the maintenance of the efficiency improvement effect of the solar cell end in the module end after the solar cell is welded and assembled into a photovoltaic module. This is further conducive to the large-scale application of such cells in power stations, improving energy efficiency and reducing power generation costs.

[0070] Preferably, the range of S1:S2 is (70:30) to (90:10). When the area ratio of the planar structure 21 and the pit structure 22 is further controlled within the above range, the planar structure 21 of the doped polysilicon layer 2 can be maintained in integrity to a greater extent, and the pit 221 and the second carrier transport structure 120 can also be provided to reduce the contact resistance. In particular, when the range of S1:S2 is 65:35, the effect is better.

[0071] It can be understood that the above S1 and S2 can be obtained by shooting a scanning electron microscope image of the doped polysilicon layer 2 in a specified area of the contact region, and then measuring and calculating. For example, the doped polysilicon layer 2 in an arbitrary 5.6 μm x 4.2 μm contact region is selected for shooting, and the specified area of the doped polysilicon layer 2 in the contact region is 23.52 μm 2 The area of the pit structure 22 in the contact region is measured and calculated, and then the area of the planar structure 21 and the area ratio of the two structures are calculated. Specifically, five different positions of 5.6 μm x 4.2 μm regions can be selected, the area of the pit structure 22 in the corresponding contact region is measured and calculated, and the average value of the areas of these different positions is taken, which reflects the area of the pit structure 22 in the contact region. Then, the area of the planar structure 21 and the area ratio of the two structures are obtained by subtracting the area of the pit structure 22 from the specified area of the contact region. Of course, the area of the planar structure 21 in the contact region can be measured and calculated first, and then the area of the pit structure 22 and the area ratio of the two structures are calculated. The measurement method of S1 and S2 is not limited in the present application.

[0072] In the embodiment of the present application, the doped polysilicon layer 2 located in the first contact region 100A includes a substructure 210. According to the connection relationship of the substructure 210, the doped polysilicon layer 2 in the first contact region 100A can have different structural forms.

[0073] In one embodiment, further in combination with Figure 2 and Figure 3As shown, the doped polysilicon layer 2 located in the first contact region 100A includes several independent substructures 210, with gaps 211 between adjacent substructures 210. The substructures 210 are assembled to form a flat planar structure 21. Viewed along the thickness direction of the doped polysilicon layer 2 (i.e., along...) Figure 3 (Viewed from a direction perpendicular to the paper), these substructures 210 are mostly irregular polygons, with obvious gaps 211 between adjacent substructures 210, making each substructure 210 separate from each other and become an independent structure. However, when these substructures 210 are spliced ​​together, they form the planar structure 21 of the first contact area 100A.

[0074] Furthermore, observing along the thickness direction of the doped polysilicon layer 2, the maximum distance between any two points on the outer contour of a single substructure 210 is 50 nm to 1000 nm. This maximum distance can roughly reflect the size level of the substructure 210. The size of the substructure 210 within this range is beneficial to better ensure the film density of the doped polysilicon layer 2 in the first contact region 100A and the uniformity of the distribution of doped elements in the doped polysilicon layer 2, which is beneficial to further improve the conductivity and passivation performance of the metal semiconductor contact structure 100. The maximum distance between any two points on the outer contour of a single substructure 210 is 50 nm to 1000 nm, which includes any point value within this range. For example, the maximum distance between any two points on the outer contour of a single substructure 210 is 50 nm, 80 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 800 nm, or 1000 nm.

[0075] In another implementation, combined Figure 5 As shown, unlike the form of a planar structure 21 formed by combining several independent substructures 210, in this embodiment, the planar structure 21 located in the first contact area 100A is a continuous structure. It can also be understood that the substructures 210 are connected to each other without obvious and numerous gaps 211, thus forming a continuous planar structure 21 without numerous dividing boundaries.

[0076] In the second contact area 100B of this application embodiment, refer to the reference... Figure 2 and Figure 3The plurality of pits 221 are adjacently arranged to form a pit group 220, and the pit structure 22 comprises a plurality of such pit groups 220. In the thickness direction of the doped polysilicon layer 2, the maximum distance between any two points on the opening outer contour of the pit group 220 is 10 nm to 1500 nm. The maximum distance can generally reflect the size level of the pit group 220, and the pit group 220 size in this range is conducive to better balancing the influence of the second carrier contact structure on the improvement of the conductive performance and the interface passivation performance. The maximum distance between any two points on the opening outer contour of the pit group 220 is 10 nm to 1500 nm, including any point value in this numerical range, for example, the maximum distance between any two points on the opening outer contour of the pit group 220 is 10 nm, 50 nm, 80 nm, 100 nm, 200 nm, 300 nm, 500 nm, 700 nm, 900 nm, 1200 nm or 1500 nm.

[0077] It can be understood that for the second contact region 100B, the surface of the doped polysilicon layer 2 for contacting the metal electrode 3 is the pit structure 22, and the pit structure 22 comprises a plurality of pits 221. These pits 221 are formed by etching the surface of the doped polysilicon layer 2 during the process of manufacturing the metal electrode 3, so these pits 221 can be adjacent pits 221 connected to each other, or adjacent pits 221 with a small gap (the gap is the flat surface of the doped polysilicon layer 2 which is not etched) between the pits 221, but overall these pits 221 are densely distributed to form a pit group 220, and a plurality of such pit groups 220 further form the pit structure 22 in the second contact region 100B. In addition, it can also be seen from this that for the case where adjacent pits 221 have a small gap, the gap is a flat surface of the doped polysilicon layer 2, but it should not be understood as the planar structure 21 of the first contact region 100A, but as a structure in the second contact region 100B. For example Figure 3 As shown, the first contact region 100A is a relatively large area of a whole unetched region, and although the small gap between the adjacent pits 221 of the second contact region 100B is relatively flat, the small gap belongs to the second contact region 100B.

[0078] Further, the recessed depth of the recess 221 along the thickness direction of the doped polysilicon layer 2 is H, 0nm < H ≤ 200nm; the thickness of the doped polysilicon layer 2 is 50nm-500nm, and H is less than the thickness of the doped polysilicon layer 2. The recessed depth of the recess 221 and the thickness of the doped polysilicon layer 2 are controlled so that the recess 221 does not burn through the doped polysilicon layer 2 and does not have an excessively deep etching effect. Such a recess structure 22 has less impact on the contact interface performance of the metal-semiconductor contact structure 100 and less impact on the passivation performance than a hole structure that directly burns through the doped polysilicon layer 2 and reaches the silicon substrate 1. 0nm < H ≤ 200nm includes any point value in the numerical range, for example, H is 10nm, 20nm, 30nm, 50nm, 60nm, 70nm, 90nm, 100nm, 120nm, 150nm, 180nm or 200nm. The thickness of the doped polysilicon layer 2 is 50nm-500nm, which includes any point value in the numerical range, for example, the thickness of the doped polysilicon layer 2 is 50nm, 60nm, 80nm, 100nm, 150nm, 200nm, 300nm, 400nm or 500nm.

[0079] Further, referring back to Figure 2 The metal-semiconductor contact structure 100 of the embodiment of the present application further includes glass phase 130 distributed in the contact region. Part of the glass phase 130 is distributed in the first contact region 100A, and the first carrier transport structure 110 further includes a plurality of conductive metal particles 111 wrapped in the glass phase 130; part of the glass phase 130 is located in the recess 221.

[0080] The glass phase 130 is one of the components of the paste used to form the metal electrode 3 on the doped polysilicon layer 2, and is mainly used to etch away the functional film layers such as the passivation layer 4, so that the metal components in the paste can contact the doped polysilicon layer 2 and promote the formation of the metal-semiconductor contact structure 100. In the embodiment of the present application, part of the glass phase 130 is distributed in the first contact region 100A and is located on the doped polysilicon layer 2 without etching the surface thereof, so that the surface of the doped polysilicon layer 2 in the first contact region 100A can maintain the planar structure 21. In addition, the glass phase 130 in the first contact region 100A also wraps a plurality of conductive metal particles 111, and the spacing between these conductive metal particles 111 is very small, satisfying the tunneling effect, so that in the first contact region 100A, in addition to the conductive metal particles 111 that directly contact the doped polysilicon layer 2 and can be used to transport carriers, the conductive metal particles 111 wrapped in the glass phase 130 can also transport carriers through the tunneling effect, improving the conductivity of the first carrier transport structure 110.

[0081] Further, the metal-semiconductor contact structure 100 of the embodiment of the present application further comprises a passivation layer 4 disposed on the doped polysilicon layer 2, and the metal electrode 3 penetrates through the passivation layer 4 and contacts the doped polysilicon layer 2. The passivation layer 4 can further improve the passivation performance of the solar cell. The passivation layer 4 can comprise one or more composite layers, and the passivation layer 4 comprises aluminum oxide, silicon nitride, silicon oxynitride or silicon oxide and other materials capable of playing a passivation role.

[0082] The preparation method of the metal-semiconductor contact structure 100 will be further described below.

[0083] The preparation method of the metal-semiconductor contact structure 100 comprises the following steps:

[0084] Printing electrode paste on the doped polysilicon layer 2; wherein the electrode paste comprises a glass phase 130, a metal material and an organic carrier, and the softening temperature of the glass phase 130 is 300-400℃;

[0085] Low-temperature pre-drying: before or after the step of printing the electrode paste, pre-drying treatment is performed at 100-300℃;

[0086] Low-temperature sintering of the electrode paste; the low-temperature sintering is heated according to the stages of a first platform segment temperature, rising to a first peak segment temperature, and falling to a second platform segment temperature, the heating temperature of the first platform segment and the second platform segment is 250-350℃, the sintering peak temperature of the first peak segment is 300-400℃, and the sintering peak temperature of the first peak segment is greater than the temperature of the first platform segment and the second platform segment, and the low-temperature sintering time is 5-20s;

[0087] High-temperature sintering of the electrode precursor after low-temperature sintering, so that the electrode precursor is converted into the metal electrode 3, and the metal-semiconductor contact structure 100 is formed between the metal electrode 3 and the doped polysilicon layer 2; the high-temperature sintering is heated according to the stages of a third platform segment temperature, rising to a second peak segment temperature, and falling to a fourth platform segment temperature, the heating temperature of the third platform segment and the fourth platform segment is 700-800℃, the sintering peak temperature of the second peak segment is 750-850℃, and the sintering peak temperature of the second peak segment is greater than the temperature of the third platform segment and the fourth platform segment, and the low-temperature sintering time is 10-20s.

[0088] Through the control and cooperation of the process conditions such as temperature and time of the above steps, the embodiment of the present application realizes the control of the ablation degree of the glass phase 130, so that the surface of the doped polysilicon layer 2 of the first contact area 100A is not ablated and maintains the planar structure 21, and the surface of the doped polysilicon layer 2 of the second contact area 100B is etched to form a plurality of pits 221 and form the pit structure 22.

[0089] Specifically, in the preparation method of the embodiments of the present application, only the temperature control means of pre-baking, low-temperature sintering in stages, high-temperature sintering in stages, etc. are used to control the surface structure of the doped polysilicon layer 2 in different contact areas, and the means of laser-induced contact treatment is not used, neither high laser power is injected nor reverse bias voltage is applied.

[0090] For the step of low-temperature pre-baking, in an alternative embodiment, the step can be performed before the step of printing the electrode paste on the doped polysilicon layer. For example, for the case that the doped polysilicon layer is located on the back surface of the solar cell, the electrode paste for the light-receiving surface can be printed on the emitter of the light-receiving surface first, and then pre-baking is performed to convert the electrode paste for the light-receiving surface into the electrode precursor for the light-receiving surface, so as to ensure that the subsequent printing of the electrode paste is not affected; then, the electrode paste for the back surface is printed on the doped polysilicon layer of the back surface, and then the low-temperature sintering and high-temperature sintering of the electrode precursor for the light-receiving surface and the electrode paste for the back surface are performed.

[0091] In another alternative embodiment, the pre-baking can be performed after the step of printing the electrode paste on the doped polysilicon layer. This operation makes the organic carrier in the electrode paste volatilize, and the glass phase 130 effectively adheres to the doped polysilicon layer 2 with the metal material wrapped therein, and the glass phase 130 does not significantly soften. On the basis of this operation, the low-temperature sintering of the electrode paste is performed first, the sintering mode is to increase the temperature from the platform segment temperature to the peak segment temperature and then decrease the temperature to the platform segment temperature, and the temperature of the entire low-temperature sintering process is controlled to be close to the softening temperature range of the glass phase 130, so that the glass phase 130 and the metal material wrapped therein in the electrode paste are more uniformly distributed, and the glass phase 130 remains in the softened state. Then, the high-temperature sintering of the electrode precursor with the glass phase 130 in the softened state is performed, the sintering mode is still to increase the temperature from the platform segment temperature to the peak segment temperature and then decrease the temperature to the platform segment temperature, and the temperature of the entire high-temperature sintering process is controlled to be above 700°C, so that part of the surface of the doped polysilicon layer 2 forms the pit structure 22 due to the corrosion of the glass phase 130, and the surface of another part of the doped polysilicon layer 2 still remains the planar structure 21.

[0092] It can be understood that the light-receiving surface and the back surface of the solar cell usually use different types of electrode paste, for example, one is a P-type electrode paste suitable for a P+ emitter, and the other is an N-type electrode paste suitable for an N-type doped conductive layer (for example, an N-type doped polysilicon layer). Although the system of the electrode paste includes a glass phase, a metal material, and an organic carrier, the specific components of the P-type electrode paste and the N-type electrode paste can be different. In the conventional P-type electrode paste and the conventional N-type electrode paste, the present application selects the corresponding electrode paste with a glass phase having a softening temperature of 300°C to 400°C.

[0093] Further, the doped polysilicon layer 2 can be obtained by different processes. In one alternative embodiment, the doped polysilicon layer 2 is obtained by an LPCVD process. In the metal-semiconductor contact structure 100, the doped polysilicon layer 2 at the first contact region 100A comprises a plurality of independent sub-structures 210 with gaps 211 between adjacent sub-structures 210, and the plurality of sub-structures 210 are combined to form a planar structure 21. In another alternative embodiment, the doped polysilicon layer 2 is obtained by a PECVD process, and in the metal-semiconductor contact structure 100, the planar structure 21 at the first contact region 100A is a continuous structure.

[0094] Further, the method for preparing the metal-semiconductor contact structure 100 further comprises the following steps: before the step of printing the electrode paste on the doped polysilicon layer 2, a passivation layer 4 is first formed on the doped polysilicon layer 2, and then the electrode paste is printed on the passivation layer 4; after the steps of low-temperature pre-drying, low-temperature sintering and high-temperature sintering, at least part of the electrode precursors pass through the passivation layer 4 and contact the doped polysilicon layer 2.

[0095] In the steps of low-temperature pre-drying and low-temperature sintering, the glass phase 130 can only adhere to the passivation layer 4 and is in a softened state due to temperature control. In the step of high-temperature sintering, the glass phase 130 has corrosion ability due to the influence of high-temperature conditions, can burn through part of the passivation layer 4 to reach the doped polysilicon layer 2, and can also make the metal material reach the doped polysilicon layer 2. These metal materials form conductive metal particles 111 on the planar structure 21 of the doped polysilicon layer 2, and participate in the recrystallization process in the pit structure 22 of the doped polysilicon layer 2 to form conductive eutectic crystals and conductive crystalline grown on the conductive eutectic crystals.

[0096] In addition to the above-mentioned metal-semiconductor contact structure 100, the solar cell of the embodiments of the present application further comprises a dielectric layer 5 arranged between the silicon substrate 1 and the doped polysilicon layer 2, and the dielectric layer 5 and the doped polysilicon layer 2 form a passivated contact structure. Through the cooperation of the dielectric layer 5 and the doped polysilicon layer 2, the doped polysilicon layer 2 can better exert the conductive performance and passivation performance. In some embodiments, the solar cell can be a passivated contact solar cell, and the above-mentioned passivated contact structure can be arranged on the back surface of the silicon substrate 1 or on both surfaces of the silicon substrate 1. In another embodiment, the solar cell can be a TBC type back contact solar cell, and the above-mentioned passivated contact structure can be arranged on the back surface of the silicon substrate 1 in a patterned structure.

[0097] In addition, the silicon substrate 1 in the solar cell of the embodiment of the present application has a flat region, and the doped polysilicon layer 2 is located on the flat region. The flat region of the silicon substrate 1 refers to a region that is more flat and looks closer to a plane compared with a textured region of the silicon substrate 1. For example, the silicon substrate 1 can be textured on the surface to form a textured structure. This region is a textured region, not a flat region. The silicon substrate 1 can also be treated on the surface by polishing or other treatment methods to make the surface look more flat. The flat region can be located on the back surface of the silicon substrate 1 or the light receiving surface of the silicon substrate 1. For example, the light receiving surface of the silicon substrate 1 is patterned to make part of the region have a texture to become a textured region, and another part of the region have a plane to become a flat region. The doped polysilicon layer 2 is arranged on the flat region of the silicon substrate 1, so that the surface of the doped polysilicon layer 2 also has a flat structure. In this way, the metal electrode 3 is made on the doped polysilicon layer 2, and the special metal semiconductor contact structure 100 of the embodiment of the present application is more easily obtained.

[0098] In addition, in addition to the above structure, the solar cell of the embodiment of the present application can also include other conventional film layers, such as a semiconductor layer 6 having a different conductivity type from the doped polysilicon layer 2, an anti-reflection layer, and the like, which are not limited by the present application.

[0099] The embodiment of the present application also provides a photovoltaic module, which includes the solar cell as described above. A plurality of the above solar cells are connected in series and / or in parallel and encapsulated to form the photovoltaic module.

[0100] The embodiment of the present application is further described below in combination with specific examples and test results. In addition, the reagents used in the following examples, such as sodium hydroxide, TS40 type additive, electrode paste, etc., can be obtained by commercial purchase.

[0101] Example 1

[0102] The embodiment provides a solar cell with a metal semiconductor contact structure, and a preparation method thereof is as follows:

[0103] (1) cleaning and texturing: in a tank device, the surface of the silicon substrate is first polished and cleaned, and then textured;

[0104] (2) boron diffusion: the silicon substrate after cleaning and texturing is placed in a boron diffusion furnace, BCl3 and oxygen are introduced at 800-1050°C for boron diffusion to form a P+ emitter;

[0105] (3) BSG removal and back surface alkali polishing:

[0106] (3.1) BSG removal: the back surface and the edge of the silicon substrate after boron diffusion are etched by HF to remove the BSG on the back surface and the edge;

[0107] (3.2) Backside Alkali Etching: Alkali etching and cleaning on the backside of the silicon substrate;

[0108] (4) Preparation of dielectric layer and doped polysilicon layer: the structure after backside alkali etching is placed in an LPCVD device, oxygen is introduced to grow a dielectric layer at 400-650°C, then SiH4 is introduced to grow an intrinsic polysilicon layer at 450-700°C, then the above structure is placed in a phosphorus diffusion furnace tube to diffuse POCl3 at 750-1050°C to form an N-type doped polysilicon layer;

[0109] (5) PSG removal and cleaning: a chain-type HF device is used to remove PSG formed by phosphorus diffusion; a tank-type device is used to clean the silicon substrate with the above structure by using sodium hydroxide and an additive of TS40 at a volume ratio of 7:1, the temperature is maintained at 80°C, and the time is 7 min;

[0110] (6) Deposition of passivation layer: an ALD device is used to deposit aluminum oxide on the light-receiving surface and the backside as part of the passivation layer, a PECVD device is used to deposit silicon oxynitride on the backside also as part of the passivation layer, the aluminum oxide layer and the silicon oxynitride layer on the backside constitute a first passivation layer; a PECVD device is used to deposit a stack of silicon oxide, silicon oxynitride, and silicon nitride on the light-receiving surface as a passivation layer anti-reflection layer, the aluminum oxide layer and the stack of silicon oxide, silicon oxynitride, and silicon nitride on the light-receiving surface constitute a second passivation layer;

[0111] (7) Fabrication of metal-semiconductor contact structure:

[0112] (7.1) Printing P-type electrode paste on the surface of the P+ emitter on the light-receiving surface; wherein the P-type electrode paste includes glass phase, metal material, and organic carrier, the softening temperature of the glass phase is 300-400°C;

[0113] (7.2) Low-temperature pre-drying: pre-drying treatment of the P-type electrode paste in a drying oven at 100-300°C to form a light-receiving surface electrode precursor;

[0114] (7.3) Printing N-type electrode paste on the doped polysilicon layer; wherein the N-type electrode paste includes glass phase, metal material, and organic carrier, the softening temperature of the glass phase is 300-400°C;

[0115] (7.4) low-temperature sintering of the light-receiving surface electrode precursor and the N-type electrode paste; the low-temperature sintering is performed by heating in stages of a first plateau temperature, rising to a first peak temperature, and falling to a second plateau temperature, the heating temperature of the first plateau and the second plateau is 250-350°C, the sintering peak temperature of the first peak is 300-400°C, and the sintering peak temperature of the first peak is higher than the temperature of the first plateau and the second plateau, and the low-temperature sintering time is 5-20s;

[0116] (7.5) high-temperature sintering of the light-receiving surface electrode precursor and the back light surface electrode precursor after the low-temperature sintering, so that the corresponding electrode precursors are respectively converted into light-receiving surface metal electrodes and back light surface metal electrodes, wherein the back light surface metal electrodes and the doped polysilicon layer form a back light surface metal-semiconductor contact structure; the high-temperature sintering is performed by heating in stages of a third plateau temperature, rising to a second peak temperature, and falling to a fourth plateau temperature, the heating temperature of the third plateau and the fourth plateau is 700-800°C, the sintering peak temperature of the second peak is 750-850°C, and the sintering peak temperature of the second peak is higher than the temperature of the third plateau and the fourth plateau, and the low-temperature sintering time is 10-20s.

[0117] Referring back to Figure 4 Fig. 4 is an SEM image of the N-type doped polysilicon layer on the silicon substrate after the metal electrode and the second passivation layer of the back light surface metal-semiconductor contact structure are peeled off in the embodiment.

[0118] Example 2

[0119] The difference between the embodiment and Example 1 is that in step (4), the medium layer and the doped polysilicon layer are prepared by using a PECVD device, specifically: a tubular PECVD device is used to grow a medium layer and a phosphorus-doped amorphous silicon layer on the back light surface of the silicon substrate in sequence, and annealing is performed to convert the phosphorus-doped amorphous silicon layer into a phosphorus-doped polysilicon layer, i.e., an N-type doped polysilicon layer. Referring back to Figure 5 Fig. 4 is an SEM image of the N-type doped polysilicon layer on the silicon substrate after the metal electrode and the second passivation layer of the back light surface metal-semiconductor contact structure are peeled off in the embodiment.

[0120] Example 3

[0121] The main difference from Example 1 is that the ratio of S1 to S2 is different, as shown in Table 1.

[0122] Comparative Examples 1-2

[0123] The main difference from Example 1 is that the ratio of S1 to S2 is different, as shown in Table 1.

[0124] Performance test description:

[0125] Open circuit voltage, fill factor, photoelectric conversion efficiency test:

[0126] The performance test of open circuit voltage, fill factor, photoelectric conversion efficiency, etc. is carried out using a halm test sorting device. The halm machine is a device simulating sunlight, and is equipped with an electronic load, a data acquisition and calculation device, etc. for testing the electrical performance of photovoltaic devices (including solar cells). The silicon wafer of the solar cell controlled in the test is 182 size, and the calibrated light intensity is 1000±5 W / m 2 .

[0127] Contact resistance rate test: the contact resistance performance test is carried out using a contact resistance tester (such as TLM-STD of MEGAWATT PV). The characteristic impedance of the transmission line is determined by measuring the current and voltage, and then the value of the contact resistance is derived according to the characteristic impedance by a calculation formula.

[0128] The S1 and S2 area ratio and the cell performance test results of each embodiment and the comparative example in Table 1

[0129]

[0130] By comparing example 1 to example 3, and comparative example 1 to comparative example 2, it can be seen that when the S1:S2 in the metal semiconductor contact structure is within the range of the present application, the passivation performance and the contact resistance can be better balanced, and the photoelectric conversion efficiency of the solar cell is obviously improved.

[0131] Among them, comparative example 1 to example 3, and comparative example 1 can be seen that with the increase of S1 area ratio, the decrease of S2 area ratio, the corrosion degree of the surface of the doped polysilicon layer is reduced, and the open circuit voltage of the solar cell is improved, but the contact resistance rate also begins to increase, and the fill factor decreases. When S1:S2 is 99:1 of comparative example 1, the overall photoelectric conversion efficiency of the solar cell is even less than 24%.

[0132] Among them, comparative example 1 to example 3, and comparative example 2 can be seen that with the increase of S2 area ratio, the contact resistance rate decreases, but the corrosion degree of the surface of the doped polysilicon layer is increased, and the open circuit voltage of the solar cell is low. When S1:S2 is 5:95 of example 2, the overall photoelectric conversion efficiency of the solar cell is also low.

[0133] The above has introduced the technical solutions disclosed in the embodiments of the present application in detail. In this paper, specific examples are applied to explain the principles and implementation modes of the present application. The above example is only used to help understand the technical solutions and core invention points of the embodiments of the present application. At the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A metal-semiconductor contact structure, characterized by, The metal-semiconductor contact structure comprises a metal electrode and a doped polysilicon layer in contact with each other, and a contact area of the metal electrode and the doped polysilicon layer comprises a first contact region and a second contact region outside the first contact region; In the first contact region, a surface of the doped polysilicon layer for contacting the metal electrode is a planar structure, and a first carrier transport structure is provided in the first contact region, the first carrier transport structure comprising a plurality of conductive metal particles arranged on the planar structure; In the second contact region, a surface of the doped polysilicon layer for contacting the metal electrode is a pit structure having a plurality of pits, and a recess direction of the pits is towards an internal direction of the doped polysilicon layer, and a second carrier transport structure is provided in the pits, the second carrier transport structure comprising a conductive eutectic crystal connected to a recessed surface of the pits and a conductive crystalline crystal arranged in a direction extending from the conductive eutectic crystal to the metal electrode; The metal electrode, the conductive metal particles and the conductive crystalline crystal all have the same metal element, and the conductive eutectic crystal comprises the metal element and a silicon element. An area of the planar structure in the contact area is S1, an area of the pit structure in the contact area is S2, and a range of S1:S2 is (40:60) to (98:2).

2. The metal-semiconductor contact structure of claim 1, wherein, A range of S1:S2 is (70:30) to (90:10); preferably, a range of S1:S2 is 65:

35.

3. The metal-semiconductor contact structure of claim 1, wherein, The doped polysilicon layer in the first contact region comprises a plurality of independent substructures, and gaps are provided between adjacent substructures, and the plurality of substructures are spliced to form the planar structure; or The planar structure is a continuous structure.

4. The metal-semiconductor contact structure of claim 3, wherein, The doped polysilicon layer in the first contact region comprises a plurality of substructures, and a maximum distance between any two points on an outer contour of a single substructure in a thickness direction of the doped polysilicon layer is 50nm to 1000nm.

5. The metal-semiconductor contact structure of claim 1, wherein, A plurality of pits are arranged adjacently to form a pit group, the pit structure comprises a plurality of pit groups, and a maximum distance between any two points on an opening outer contour of the pit group in a thickness direction of the doped polysilicon layer is 10nm to 1500nm; and / or A recess depth of the pits in the thickness direction of the doped polysilicon layer is H, 0nm 6. The metal-semiconductor contact structure of any of claims 1 to 5, wherein, The metal-semiconductor contact structure further comprises a glass phase distributed in the contact area; Part of the glass phase is distributed in the first contact region, and the first carrier transport structure further comprises a plurality of conductive metal particles wrapped in the glass phase; and part of the glass phase is located in the pits.

7. The metal-semiconductor contact structure of any one of claims 1 to 5, wherein the metal-semiconductor contact structure is a metal-semiconductor-metal contact structure. The metal element comprises a silver element; and / or The doped element in the doped polysilicon layer is an N-type conductive element or a P-type conductive element; and / or The metal-semiconductor contact structure further comprises a passivation layer disposed on the doped polysilicon layer, and the metal electrode is in contact with the doped polysilicon layer through the passivation layer.

8. A method for preparing a metal-semiconductor contact structure as described in any one of claims 1 to 7, characterized in that, The preparation method comprises the following steps: printing an electrode paste on the doped polysilicon layer; wherein the electrode paste comprises a glass phase, a metal material and an organic carrier, and the softening temperature of the glass phase is 300-400℃; low-temperature pre-baking: pre-baking treatment is performed at 100-300℃ before or after the step of printing the electrode paste; low-temperature sintering of the electrode paste; the low-temperature sintering is performed in stages of a first plateau segment temperature, rising to a first peak segment temperature, and falling to a second plateau segment temperature, the heating temperature of the first plateau segment and the second plateau segment is 250-350℃, the sintering peak temperature of the first peak segment is 300-400℃, and the sintering peak temperature of the first peak segment is greater than the temperature of the first plateau segment and the second plateau segment, and the low-temperature sintering time is 5-20s; high-temperature sintering of the electrode precursor after low-temperature sintering, so that the electrode precursor is converted into the metal electrode, and the metal-semiconductor contact structure is formed between the metal electrode and the doped polysilicon layer; the high-temperature sintering is performed in stages of a third plateau segment temperature, rising to a second peak segment temperature, and falling to a fourth plateau segment temperature, the heating temperature of the third plateau segment and the fourth plateau segment is 700-800℃, the sintering peak temperature of the second peak segment is 750-850℃, and the sintering peak temperature of the second peak segment is greater than the temperature of the third plateau segment and the fourth plateau segment, and the low-temperature sintering time is 10-20s.

9. The production method according to claim 8, characterized by, The doped polysilicon layer is prepared by an LPCVD process, and in the metal-semiconductor contact structure, the doped polysilicon layer in the first contact area comprises a plurality of independent substructures, adjacent substructures have boundaries, and a plurality of the substructures are spliced to form a flat doped polysilicon layer; or the doped polysilicon layer is prepared by a PECVD process, and in the metal-semiconductor contact structure, the doped polysilicon layer in the first contact area is a continuous and flat integral structure. And / or, The preparation method further comprises the following steps: before the step of printing the electrode paste on the doped polysilicon layer, a passivation layer is prepared on the doped polysilicon layer, and then the electrode paste is printed on the passivation layer; After the steps of low-temperature pre-baking, low-temperature sintering and high-temperature sintering, at least part of the electrode precursor is in contact with the doped polysilicon layer through the passivation layer.

10. A solar cell, characterized by The solar cell comprises: a silicon substrate; a doped polysilicon layer on the silicon substrate; a metal electrode in contact with the doped polysilicon layer, and the metal electrode and the doped polysilicon layer form the metal-semiconductor contact structure according to any one of claims 1-7.

11. The solar cell according to claim 10, characterized in that, The solar cell further comprises a dielectric layer between the silicon substrate and the doped polysilicon layer, and the dielectric layer and the doped polysilicon layer form a passivation contact structure; and / or, The silicon substrate has a flat region, and the doped polysilicon layer is located on the flat region.

12. A photovoltaic module, characterized by The photovoltaic module comprises a solar cell as claimed in claim 10 or 11.

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