一种嵌入式芯片封装方法及封装设备
By combining a laser etching reference coordinate system and a fiber optic sensing array in embedded chip packaging, a dynamic position compensation model and a filling path planning matrix are constructed, which solves the problems of microbump coplanarity offset and interface defects, and achieves high-precision and high-reliability chip packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG TAIJIN SEMICON TECH CO LTD
- Filing Date
- 2025-10-24
- Publication Date
- 2026-07-17
AI Technical Summary
In existing embedded chip packaging technologies, the coplanar misalignment of microbumps under thermal stress leads to a high risk of solder joint failure. Insufficient precision of optical alignment systems and the lack of real-time monitoring and feedback mechanisms result in reduced reliability and lifespan of packaged devices.
A reference coordinate system is formed by laser etching and embedded with a fiber optic sensor array. Combined with a scanner and a micro-CT system, a dynamic position compensation model and a filling path planning matrix are constructed to achieve real-time compensation and precise control. Strain data is monitored through the fiber optic sensor array to iteratively optimize chip mounting and dispensing.
It achieves high-precision and high-reliability flip-chip packaging, effectively solving the problems of microbump coplanarity misalignment and interface defects, and improving the performance and lifespan of packaged devices.
Smart Images
Figure CN121398664B_ABST