A detection circuit and lidar

Abstract

This application provides a detection circuit and a lidar, relating to the field of lidar technology, for improving the ranging accuracy of lidar. The detection circuit provided in this application includes: a plurality of first input sub-circuits, each with its first terminal connected to an output node, the output node being connected to the output terminal of the detection circuit; a plurality of first input sub-circuits, each with its second terminal connected to the first terminal of a current control sub-circuit; a third terminal of each first input sub-circuit configured to receive a photon trigger signal; a second terminal of the current control sub-circuit connected to a first voltage signal terminal; the first input sub-circuits configured to conduct in response to the received photon trigger signal, thereby connecting the output terminal of the detection circuit to the first voltage signal terminal, and the output terminal of the detection circuit outputting a first photon signal; and the current control sub-circuit configured to control the current flowing through the current control sub-circuit within a preset range.

Description

Technical Field

[0001] This invention relates to the field of lidar technology, and more particularly to a detection circuit and a lidar. Background Technology

[0002] LiDAR is a commonly used system for distance detection. The working principle of LiDAR is to emit one or more pulsed laser beams towards the object being detected. The laser pulses propagate through space, and when they encounter the object, part of the light wave is reflected. By measuring the time difference between the emission of the laser pulse and the reception of the reflected pulse, and combining this with the speed of light, the distance between the LiDAR and the object can be calculated. Since electrical signals are easier to process and measure, the photon signal needs to be converted into an electrical signal when calculating the time difference, and then the time difference measurement is performed at the electrical signal level.

[0003] Because the intensity and direction of reflected light depend on factors such as the material, shape, and surface roughness of the object being detected, when the reflected light is strong, such as when the object is close to the lidar or has a high reflectivity, the laser receiver may receive multiple photons simultaneously. In this case, the delay after conversion into an electrical signal differs significantly from the delay during single-photon triggering, making it impossible to accurately determine the time difference and consequently resulting in low accuracy of the measured distance. Summary of the Invention

[0004] This application provides a detection circuit and a lidar for improving the ranging accuracy of lidar.

[0005] A first aspect of this application provides a detection circuit, including a plurality of first input sub-circuits connected in parallel and a current control sub-circuit; the first terminals of the plurality of first input sub-circuits are all connected to an output node, the output node is connected to the output terminal of the detection circuit, the second terminals of the plurality of first input sub-circuits are all connected to the first terminals of the current control sub-circuit, and the third terminal of each first input sub-circuit is configured to receive a photon trigger signal; the second terminal of the current control sub-circuit is connected to a first voltage signal terminal; the first input sub-circuits are configured to be turned on in response to the received photon trigger signal, so that the output terminal of the detection circuit is connected to the first voltage signal terminal, and the output terminal of the detection circuit outputs a first photon signal; the current control sub-circuit is configured to control the current flowing through the current control sub-circuit within a preset range.

[0006] The detection circuit provided in this application includes multiple first input sub-circuits connected in parallel and a current control sub-circuit. The current control sub-circuit can control the discharge current within a preset range. In this way, regardless of how many first input sub-circuits are turned on, the magnitude of the current flowing in the circuit is always within the preset range, that is, the discharge speed in the circuit is the same or approximately the same. Consequently, the switching speed of the output node is the same or approximately the same, and the delay of the first photon signal output by the output terminal of the detection circuit is also basically fixed, thereby ensuring the ranging accuracy of the lidar.

[0007] In conjunction with the first implementation of the first aspect, the detection circuit further includes a plurality of second input sub-circuits connected in series; in the plurality of second input sub-circuits, the second terminal of the preceding second input sub-circuit is connected to the first terminal of the following second input sub-circuit, the first terminal of the first second input sub-circuit is connected to the second voltage signal terminal, and the second terminal of the last second input sub-circuit is connected to the output node; the third terminal of each second input sub-circuit is configured to receive a photon trigger signal; there is a potential difference between the voltage signals output by the first voltage signal terminal and the second voltage signal terminal; the second input sub-circuit is configured to be turned on when no photon trigger signal is received, so that the output terminal of the detection circuit is connected to the second voltage signal terminal.

[0008] In conjunction with the second implementation of the first aspect, the first input sub-circuit includes an NMOS transistor, and the second input sub-circuit includes a PMOS transistor; the first voltage signal terminal is configured to output a low voltage signal, and the second voltage signal terminal is configured to output a high voltage signal.

[0009] In conjunction with the third implementation of the first aspect, the current control circuit includes an NMOS transistor.

[0010] In conjunction with the fourth implementation of the first aspect, the first input sub-circuit includes a PMOS transistor, and the second input sub-circuit includes an NMOS transistor; the first voltage signal terminal is configured to output a high voltage signal, and the second voltage signal terminal is configured to output a low voltage signal.

[0011] In conjunction with the fifth implementation method of the first aspect, the current control circuit includes a PMOS transistor.

[0012] In conjunction with the sixth implementation method of the first aspect, the detection circuit also includes an inverter, and the output node is connected to the output terminal of the detection circuit through the inverter.

[0013] In conjunction with the seventh implementation of the first aspect, the control circuit includes a first transistor, the first terminal of the first transistor is connected to the first terminal of the control circuit, and the second terminal of the first transistor is connected to the second terminal of the control circuit; the control terminal of the first transistor is configured to receive a first control signal, the first control signal being used to make the first transistor operate in the saturation region.

[0014] In conjunction with the eighth implementation of the first aspect, the current control circuit includes a current mirror circuit and a second transistor; the first terminal of the current mirror circuit is connected to the current signal terminal, the second terminal of the current mirror circuit is connected to the second terminal of the current control circuit, and the third terminal of the current mirror circuit is connected to the control electrode of the second transistor; the current value of the current signal output by the current signal terminal is within a preset range; the first electrode of the second transistor is connected to the first terminal of the current control circuit, and the second electrode of the second transistor is connected to the second terminal of the current control circuit.

[0015] A second aspect of this application provides a lidar, including a laser emitter, a laser receiver, a processor, and a detection circuit provided in the first aspect and its possible implementations; the laser emitter and the detection circuit are respectively connected to the processor, and the detection circuit is also connected to the laser receiver; the laser emitter is configured to emit photon signals; the laser receiver is configured to receive photon signals reflected back by a target object and output a photon trigger signal to the detection circuit; the detection circuit is configured to output a first photon signal based on the photon trigger signal; and the processor is configured to determine the distance between the lidar and the target object based on the first photon signal.

[0016] The beneficial effects described in the second aspect can be referred to in the analysis of the beneficial effects in the first aspect, and will not be repeated here. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.

[0018] Figure 1 This is a schematic diagram of the structure of a lidar provided in an embodiment of this application;

[0019] Figure 2 A schematic diagram illustrating the output of the first photon signal provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of a non-circuit structure provided in the embodiments of this application;

[0021] Figure 4 A simplified schematic diagram of a NOR circuit provided for an embodiment of this application;

[0022] Figure 5 This application provides a schematic diagram of the structure of a single-photon triggered time-of-flight NOR circuit.

[0023] Figure 6 A schematic diagram of a NOR circuit for simultaneous triggering by two photons is provided in an embodiment of this application.

[0024] Figure 7 A schematic diagram of a first photon signal delay provided in an embodiment of this application;

[0025] Figure 8 A histogram corresponding to a single-photon triggered pulse waveform provided in an embodiment of this application;

[0026] Figure 9 A histogram corresponding to a multiphoton-triggered pulse waveform provided in an embodiment of this application;

[0027] Figure 10 A delay relationship curve of the first photon signal is provided for an embodiment of this application;

[0028] Figure 11 A schematic diagram of a detection circuit provided in an embodiment of this application. Figure 1 ;

[0029] Figure 12 A schematic diagram of current flow in a detection circuit provided in this application embodiment;

[0030] Figure 13 A schematic diagram of a detection circuit provided in an embodiment of this application. Figure 2 ;

[0031] Figure 14 A schematic diagram of a detection circuit provided in an embodiment of this application. Figure 3 ;

[0032] Figure 15 A schematic diagram of a detection circuit provided in an embodiment of this application. Figure 4 ;

[0033] Figure 16 A schematic diagram of a detection circuit provided in an embodiment of this application. Figure 5 ;

[0034] Figure 17 A schematic diagram of a current control sub-circuit provided in an embodiment of this application. Figure 1 ;

[0035] Figure 18 A schematic diagram of a current control sub-circuit provided in an embodiment of this application. Figure 2 ;

[0036] Figure 19 A schematic diagram of a current control sub-circuit provided in an embodiment of this application. Figure 3 ;

[0037] Figure 20 A schematic diagram of a current control sub-circuit provided in an embodiment of this application. Figure 4 ;

[0038] Figure 21 A schematic diagram of a current control sub-circuit provided in an embodiment of this application. Figure 5 ;

[0039] Figure 22 A schematic diagram of a current control sub-circuit provided in an embodiment of this application. Figure 6 . Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0042] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, when describing pipelines, the terms "connected" and "linked" as used in this application have the meaning of establishing electrical connection. The specific meaning needs to be understood in conjunction with the context.

[0043] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0044] Before providing a detailed explanation of the embodiments of this application, some terms involved in the embodiments of this application will be explained.

[0045] An N-channel metal-oxide-semiconductor (NMOS) is a type of metal-oxide-semiconductor (MOS) field-effect transistor (FET) based on an N-type channel. An N-channel MOS transistor consists of a p-type substrate and two high-concentration n-diffusion regions. When the transistor is turned on, an n-type conductive channel is formed in the two high-concentration n-diffusion regions. NMOS transistors can control current flow under specific conditions. The voltage applied between the gate and source of an NMOS transistor controls the channel conductivity between the gate and source: when the gate voltage is low, the channel conductivity is low, the drain-source current is very small or almost zero, and the NMOS transistor is in the cutoff state. When the gate voltage is high, the channel conductivity increases, the drain-source current increases, and the NMOS transistor is in the on state.

[0046] A P-channel metal-oxide-semiconductor (PMOS) is a type of metal-oxide-semiconductor (MOS) field-effect transistor (FET) based on a P-type channel. A PMOS transistor mainly consists of a source, drain, gate, and a silicon substrate. The source and drain are made of p-type semiconductor material, while the gate is isolated from and covered by an insulating oxide layer. The silicon substrate is made of n-type semiconductor material. This structure allows the PMOS transistor to control its conduction state by adjusting the gate voltage under specific conditions.

[0047] A single-photon avalanche diode (SPAD) is a photoelectric avalanche diode with single-photon detection capability. SPADs can detect a single photon with extremely high sensitivity; their time accuracy can reach tens to hundreds of picoseconds, making them suitable for applications requiring high-precision time measurement.

[0048] A time-to-digital converter (TDC) is used to measure time intervals or time differences and convert the measured time length into digital code.

[0049] Analog front-end circuits (AFEs) are used to perform preliminary signal processing, such as width adjustment of analog / digital pulses, to improve the signal-to-noise ratio and processability of the signal.

[0050] Time-Correlated Single Photon Counting (TCSPC) is a method for detecting and recording low-intensity, high-repetition-rate photon signals. This technique boasts extremely high temporal resolution and sensitivity. The basic principle of TCSPC is as follows: a transmitter emits a light signal, and the time it takes for the light signal to return to its original position after being reflected by the detected object and received by the receiver is detected. This time is proportionally converted into corresponding voltage pulses by a time-to-digital converter (TDC), and then the electrical pulses are fed into a multi-channel analyzer via an analog-to-digital converter (ADC). In the multi-channel analyzer, these output pulses are sequentially sent to each channel for accumulation and storage, ultimately obtaining a histogram consistent with the original waveform.

[0051] LiDAR (Light Detection and Ranging) is a type of radar that uses a laser as its radiation source. It is a product of the combination of laser and radar technologies.

[0052] For example, please refer to Figure 1 The lidar 10 includes: a laser emitter 11, a laser receiver 12, a detection circuit 13, a time-to-digital converter 14, and a processor 15.

[0053] In this embodiment, the laser emitter 11 is used to emit a laser signal toward the object being detected. It is understood that the laser signal is essentially composed of a large number of photons with the same frequency, phase, polarization state, and propagation direction.

[0054] In some embodiments, the laser receiver 12 may include a SPAD array capable of detecting photon signals reflected back from the object being detected, generating a photon trigger signal and sending it to the detection circuit 13.

[0055] In some embodiments, since lidar may need to operate under different environmental conditions, such as indoor, outdoor, different lighting conditions, etc., or different lidar systems have different performance specifications, such as maximum measurement distance, measurement accuracy, frame rate, etc.

[0056] like Figure 1 As shown, the detection radar may also include an AFE array 16, which can process and optimize the photon signal received by the laser receiver 12 and send the processed photon trigger signal to the detection circuit 13.

[0057] AFE can also perform further processing on digital pulses, including pulse width adjustment. By adjusting the pulse width, the lidar can better adapt to different scenarios, ensuring that the system meets different specifications and improving the stability and reliability of measurements.

[0058] In this embodiment of the application, the detection circuit 13 is used to convert the received photon trigger signal into a first photon signal.

[0059] The time-to-digital converter 14 is used to determine the time difference between the time of laser signal emission and the time of receiving the first photon signal based on the delay of the first photon signal, and then convert it into digital code.

[0060] In this embodiment, the processor 15, after receiving the digital code from the time-to-digital converter 14, organizes the time interval data in the digital code into a histogram. The horizontal axis of the histogram represents time (typically converted to distance), and the vertical axis represents the number of photons or pulses received within a specific time period. In the constructed histogram, the processor searches for peaks. The time (or converted distance) corresponding to a peak typically represents the shortest time required for a laser pulse to travel from the laser radar emission point to the object being detected and back. Once a peak is detected, the processor can calculate the distance to the detected object based on the time corresponding to the peak.

[0061] In some embodiments, the processor 15 may be composed of a microcontroller unit (MCU), an advanced reduced instruction set computing machine (ARM), or a logic device such as a complex programmable device (CPLAD) or a field programmable gate array (FPGA).

[0062] In some embodiments, the processor 15 can also apply forces of different magnitudes to the laser emitter 11 or the laser receiver 12 via a motor to adjust the polarization state of the light signal emitted by the laser emitter 11 or the light signal received by the laser receiver 12. Alternatively, the processor 15 can send instructions (codes) to the laser emitter 11 or the laser receiver 12 via software to adjust the polarization state of the light signal emitted by the laser emitter 11 or the light signal received by the laser receiver 12.

[0063] It should be pointed out that, Figure 1The structure shown does not constitute a limitation on the lidar. In other embodiments, the lidar may include fewer or more components than shown, or combine certain components, or have different component arrangements. This application does not impose any limitations on this.

[0064] Please see Figure 2 The detection circuit in the related technology can be regarded as an n-input OR gate circuit. After receiving a photon signal, each SPAD in the array of n SPADs of the laser receiver will send a photon trigger signal (SPAD1, SPAD2...SPADn) to the corresponding input terminal of the detection circuit through the corresponding AFE among the n AFEs of the AFE array. No matter how many photon trigger signals are received at a certain point in time, the detection circuit will only output (OUT) one first photon signal to the TDC.

[0065] When the object being detected is close to the lidar, or when the object has a high reflectivity, the reflected light from the object is strong. In this case, the laser receiver may receive multiple photon signals simultaneously, meaning it is triggered by multiple photons at the same time and sends multiple photon trigger signals to the detection circuit. Because the output delay of the detection circuit exhibits the following instability: the more input ports that simultaneously transition, the smaller the circuit delay, the greater the difference in delay between the first photon signal output by the detection circuit in single-photon and multi-photon triggering scenarios.

[0066] The instability of the output delay of the detection circuit is due to the following reasons (for ease of description, this application uses a logic circuit that is valid only for the rising edge):

[0067] Understandably, the detection circuit can be viewed as an n-input OR gate, such as... Figure 3 The two OR gate structures are shown. In the structure of an n-input OR gate circuit, the OR and NOT circuits that are valid for the rising edge are the same, as shown below. Figure 3 The circuit shown in the dashed box is as follows.

[0068] It should be understood that Figure 3 VDD is used to identify the positive power supply (especially logic high voltage), ZN is the output node of the circuit, and OUT is the output terminal of the circuit.

[0069] As can be seen, this NOR circuit consists of n NMOS transistors connected in parallel. The main function of an NMOS transistor is as an electronic switch, controlled by an Ai (i = 1, 2, ..., n) signal (photon trigger signal) to maintain its "on" or "off" state. Specifically, when a positive voltage is applied to the gate (receiving the Ai signal) and exceeds a certain threshold voltage (Vth), the NMOS transistor forms a conductive channel between its source and drain, allowing current to flow from the source to the drain; in this state, the transistor is "on". Conversely, when the gate voltage is below the threshold voltage, the conductive channel disappears, no current flows between the source and drain, and the transistor is "off". In other words, when the gate receives a photon signal, the transistor is "off", and current can flow from the source to the drain.

[0070] The width and resistance of the conductive channel formed between the source and drain of an NMOS transistor, depending on the voltage received at the gate, affect the magnitude of the current flowing through the NMOS transistor. Therefore, an NMOS transistor can also be regarded as a current source.

[0071] In other words, such as Figure 4 As shown, an NMOS transistor can be considered as a switch controlled by a signal Ai (i = 1, 2, ..., n) connected in series with a current source. When Ai is high (i.e., logic 1), the switch is closed; when Ai is low (i.e., logic 0), the switch is open. Figure 4 In this context, ZN is the output node of the circuit, and Cpar is the parasitic capacitance of the output node ZN.

[0072] It should be understood that parasitic capacitance, also known as stray capacitance, refers to the capacitance unintentionally generated in electronic devices and circuits. It is usually caused by factors such as electric field between conductors, mutual inductance, insulating materials between layers of printed circuit boards, and connectors, and can be used to store electric charge.

[0073] When all Ai (i = 1, 2, ..., n) are 0, the circuit is in a static state, and ZN is a high level (1). Please refer to [link / reference]. Figure 5 When any input terminal changes from 0 to 1, the corresponding switch closes. At this time, the current source in the closed branch discharges to ZN, that is, the charge flow in the parasitic capacitance of the output node ZN flows out through the switch and current source in the closed branch, making ZN become low level 0 and outputting the first photon signal.

[0074] Please continue reading. Figure 5 In a single-photon triggered scenario, where one input changes from 0 to 1, the corresponding switch closes, and the current flows in the circuit as follows: Figure 5As shown by the middle arrow. In a scenario where two photons trigger simultaneously, meaning both input terminals switch from 0 to 1, the corresponding switch closes, and the current flow in the circuit is as follows: Figure 6 As indicated by the middle arrow.

[0075] In other words, if m photons trigger simultaneously and m input terminals switch at the same time, there will be m current sources discharging ZN in the circuit. The larger m is, the larger the discharge current, the faster ZN switches, and the smaller the output delay.

[0076] Based on this, such as Figure 7 As shown, when the laser receiver is triggered by a single photon, i.e., SPAD2 receives the photon signal, the delay of the first photon signal output by the detection circuit is td1. When the laser receiver is triggered by two photons simultaneously, i.e., SPAD1 and SPAD2 receive the photon signal at the same time, the delay of the first photon signal output by the detection circuit is td2. It can be seen that the signal delay td2 of two photons triggered simultaneously is smaller than the signal delay td1 of a single photon trigger.

[0077] During ranging, the TCSPC process and the resulting histogram in the case of single-photon triggering are as follows: Figure 8 As shown, the generated histogram contains only one photon counting peak, allowing the processor to accurately locate the peak and achieve high-precision ranging. However, when the reflected light is strong, the laser receiver may be triggered by multiple photons simultaneously. In this case, the histogram generated by TCSPC may exhibit a double-peak (or even multi-peak) phenomenon, as shown below. Figure 9 As shown, the histogram may simultaneously contain the pulse waveform and corresponding photon count peaks during multi-photon triggering, and the pulse waveform and corresponding photon count peaks during single-photon triggering. In this case, the processor has difficulty determining the valid peak position, and therefore cannot accurately determine the distance to the detected object.

[0078] In other words, due to the instability of the output delay of the detection circuit, the delay of the first photon signal output is different when triggered by a single photon or multiple photons. As a result, the histogram may have a double peak (or even multiple peaks), making it impossible to determine the effective peak position and thus failing to guarantee the ranging accuracy of the lidar.

[0079] Based on this, this application provides a detection circuit to ensure the stability of the delay of the first photon signal output by the detection circuit. In single-photon triggering or multi-photon triggering scenarios, the delay of the first photon signal output is the same, thereby ensuring the ranging accuracy of the lidar.

[0080] For example, please refer to Figure 10 In related technologies, the detection circuit, under ideal conditions, has a delay in outputting the first photon signal and a number of input terminals that simultaneously jump, such as... Figure 10The first curve in the figure shows a linear relationship. Figure 10 The horizontal axis of the curve represents the number of simultaneously switching input terminals, and the vertical axis represents the delay of the first photon signal. However, in practice, when the detection circuit receives the photon trigger signal, due to the channel length modulation and speed saturation of the NMOS transistor, and the fact that the NMOS transistor undergoes a transition from the saturation region to the linear region (i.e., a change in the operating region), it can only function as a current controller when it is in the saturation region. Therefore, in practical applications, the actual curve of the delay of the output first photon signal versus the number of simultaneously switching input terminals, as shown in the second curve, exhibits an exponential decay-like trend. However, the detection circuit provided in this application, where the delay of the output first photon signal is independent of the number of simultaneously switching input terminals, shows... Figure 10 As shown in the third curve, the delay of the output first photon signal remains unchanged regardless of how the number of input terminals that jump simultaneously changes.

[0081] Please see Figure 11 The detection circuit provided in this application embodiment includes: a plurality of first input sub-circuits 111 connected in parallel, and a current control sub-circuit 112.

[0082] like Figure 11 As shown, the first terminals 111a of multiple first input sub-circuits 111 are all connected to the output node ZN, and the output node ZN is connected to the output terminal OUT of the detection circuit; the second terminals 111b of multiple first input sub-circuits 111 are all connected to the first terminal 112a of the current control sub-circuit 112, and the third terminal 111c of each first input sub-circuit 111 is configured to receive photon trigger signals Ai (A1, A2...An); the second terminal 111b of the current control sub-circuit 112 is connected to the first voltage signal terminal 113.

[0083] The first input sub-circuit 111 is configured to be turned on in response to the received photon trigger signal Ai (A1, A2...An) so that the output of the detection circuit is connected to the current control sub-circuit and the output of the detection circuit outputs the first photon signal.

[0084] In other words, when the third terminal of the first input sub-circuit 111 receives the photon trigger signal, the first terminal and the second terminal are connected, so that the output terminal OUT of the detection circuit is connected to the first voltage signal terminal 113, thereby causing the output terminal OUT of the detection circuit to output the first photon signal.

[0085] It should be understood that the embodiments of this application do not limit the specific structure of the first input sub-circuit 111. In actual application, the type of transistor in the first input sub-circuit 111 can be determined according to the requirements. As one feasible implementation, the first input sub-circuit 111 may include an NMOS transistor. As another feasible implementation, the first input sub-circuit 111 may include a PMOS transistor. The embodiments of this application do not specifically limit the type of transistor in the first input sub-circuit 111.

[0086] In this embodiment of the application, the current control sub-circuit 112 is configured to control the current flowing through it to be within a preset range when it is connected to the output terminal OUT of the detection circuit.

[0087] It should be understood that the preset range in this embodiment refers to the current fluctuation range of the reference current value I corresponding to the discharge of the current control circuit 112 to the output node ZN. The reference current value I is an ideal current value calculated based on the voltage of the output node ZN, excluding the influence of factors such as power supply instability, deviation of electronic components in the circuit, and external ambient temperature. Therefore, the preset range is a current fluctuation range obtained by considering the influence of factors such as power supply instability, deviation of electronic components in the circuit, and external ambient temperature. For example, as a feasible implementation, the reference current value can be 200μA, and the preset range can be [200μA-5μA, 200μA+5μA].

[0088] The preset range can be a relatively small numerical range. Therefore, controlling the current flowing through the current control circuit 112 to be within the preset range can be considered as controlling the current flowing through the current control circuit 112 to remain constant or basically constant.

[0089] For example, taking the discharge of output node ZN to the current control sub-circuit 112 as an example, such as Figure 12 As shown, when the detection circuit does not receive a photon trigger signal Ai (A1, A2…An), that is, when all the first input sub-circuits 111 are in the off state and 0 first input sub-circuits 111 are on, no current flows through the current control sub-circuit 112. When one first input sub-circuit 111 is on, the parasitic capacitance C of the output node ZN… parDischarging through the first input sub-circuit 111 and the current control sub-circuit 112, the current value in the circuit remains within a preset range because the current control sub-circuit 112 limits the magnitude of the current flowing through it. When all (n) first input sub-circuits 111 are conducting, the parasitic capacitance Cpar of the output node ZN discharges through the n conducting first input sub-circuits 111 and the current control sub-circuit 112. At this time, the current value in each first input sub-circuit 111 may not be within the preset range, but the magnitude of the current output from the parasitic capacitance Cpar and the magnitude of the current flowing through the current control sub-circuit 112 are both within the preset range. In other words, regardless of how many first input sub-circuits 111 are conducting, the magnitude of the current flowing through the current control sub-circuit 112 is always within the preset range. This means that the discharge rate of the parasitic capacitance Cpar of the output node ZN is the same or approximately the same, resulting in the same or approximately the same transition speed of the output node ZN. Consequently, the delay of the first photon signal output by the output terminal OUT of the detection circuit remains essentially fixed.

[0090] As can be seen, in the detection circuit provided in this application embodiment, when one first input sub-circuit receives a photon trigger signal or multiple first input sub-circuits receive a photon trigger signal, the discharge speed in the circuit is the same or approximately the same, and thus the switching speed of the output node is the same or approximately the same. The delay of the first photon signal output by the output end of the detection circuit is also basically fixed, thereby ensuring the ranging accuracy of the lidar.

[0091] In some embodiments, in digital circuits, signals are represented in binary form, i.e., high level (typically logic 1) and low level (typically logic 0). Since some noise interference may exist in the circuit, noise typically manifests as small voltage fluctuations, while obvious level transitions are more easily identified and distinguished by the circuit. Therefore, the circuit needs to use high-low level transitions to identify and distinguish whether the desired signal has been received, and then output the signal. In other words, the output node of the detection circuit needs a level transition to output the first photon signal; that is, the level state of the output node differs depending on whether a photon trigger signal is received or not.

[0092] As one feasible approach, please continue reading. Figure 11 The detection circuit provided in this application embodiment further includes: a plurality of second input sub-circuits 114 connected in series.

[0093] like Figure 11As shown, in the plurality of second input sub-circuits 114, the second terminal 114b of the previous second input sub-circuit 114 is connected to the first terminal 114a of the next second input sub-circuit 114, the first terminal 114a of the first second input sub-circuit 114 is connected to the second voltage signal terminal 115, and the second terminal 114b of the last second input sub-circuit 114 is connected to the output node ZN; the third terminal 114c of each second input sub-circuit 114 is configured to receive photon trigger signals Ai (A1, A2...An).

[0094] The second input sub-circuit 114 is configured to be turned on when no photon trigger signal Ai (A1, A2…An) is received, so that the output node ZN is connected to the second voltage signal terminal 115. There is a potential difference between the voltage signals output by the first voltage signal terminal 113 and the second voltage signal terminal 115.

[0095] In other words, when no photon trigger signal Ai (A1, A2...An) is received, multiple series-connected second input sub-circuits 114 are turned on, so that the output terminal OUT of the detection circuit is connected to the second voltage signal terminal 115; when the photon trigger signal Ai (A1, A2...An) is received, the second input sub-circuit 114 is turned off, and the first input sub-circuit 111 is turned on, so that the output terminal OUT of the detection circuit is connected to the first voltage signal terminal 113 through the current control sub-circuit 112.

[0096] That is, when the photon trigger signal is received, the connection state of the output terminal of the detection circuit changes from the second voltage signal terminal 115 to the first voltage signal terminal 113. Since there is a potential difference between the voltage signals output by the first voltage signal terminal 113 and the second voltage signal terminal 115, a level jump occurs when the photon trigger signal Ai (A1, A2...An) is received, and then the output terminal OUT of the detection circuit outputs the first photon signal.

[0097] In some embodiments, different laser receivers (such as photodiodes, avalanche photodiodes, etc.) respond to photon signals differently, which affects the shape and characteristics of the converted electrical signal. Some laser receivers may generate a fast voltage pulse when they receive a photon; the beginning of this pulse can be considered a "rising edge." In this case, the photon trigger signal received by the detection circuit is a rising edge signal, that is, the level state of the third terminal of the first input sub-circuit and the third terminal of the second input sub-circuit transitions from low to high (i.e., from 0 to 1), indicating that a photon trigger signal has been received.

[0098] Based on this, as a feasible implementation method, such as Figure 13As shown, in the detection circuit provided in this application embodiment, when the photon reflection signal received by the detection circuit is a rising edge signal, the first input sub-circuit 111 includes an NMOS transistor, and the second input sub-circuit 114 includes a PMOS transistor; the first voltage signal terminal 113 is configured to output a low voltage signal (e.g., ...). Figure 13 As shown in GND), the second voltage signal terminal 115 is configured to output a high voltage signal (as shown in GND). Figure 13 (as shown in VDD).

[0099] Understandably, a PMOS transistor will conduct when its source (S) voltage is higher than its gate (G) voltage, and the absolute value of the voltage difference (VGS) between the two is greater than the threshold voltage (Vth) of the PMOS transistor. In other words, a PMOS transistor is in the conducting state when its gate is at a lower potential (low level) than its source.

[0100] Therefore, the second input sub-circuit includes a PMOS transistor. The second voltage signal terminal 115 outputs a high voltage signal, so that when no photon trigger signal is received, the third terminal 114c of the second input sub-circuit is at a low level, and the second input sub-circuit is in a conducting state. The output terminal OUT of the detection circuit is connected to the second voltage signal terminal 115, receiving the high voltage signal output by the second voltage signal terminal 115, making the level of the output terminal OUT of the detection circuit high. When a photon trigger signal is received, the level of the third terminal 114c of the second input sub-circuit jumps from low level to high level, and the second input sub-circuit 114 is in a disconnected state.

[0101] An NMOS transistor will turn on when its gate voltage (VGS) is higher than its threshold voltage (Vth). In other words, an NMOS transistor is in the on state when its gate is at a high level.

[0102] Therefore, when the photon trigger signal is a rising edge signal, the first input sub-circuit 111 includes an NMOS transistor, so that when no photon trigger signal is received, the level of the third terminal 111c of the first input sub-circuit is at a low level, and the first input sub-circuit 111 is in an off state. When the photon trigger signal is received, when the level of the third terminal 111c of the first input sub-circuit transitions from a low level to a high level, the first input sub-circuit 111 is turned on, the output terminal OUT of the detection circuit is connected to the first voltage signal terminal 113, and the low voltage signal output by the first voltage signal terminal 113 is received, causing the level of the output terminal OUT of the detection circuit to transition from a high level to a low level, thereby outputting the first photon signal.

[0103] As can be seen, in this embodiment, when the output level of the detection circuit transitions from high to low, it outputs the first photon signal, which is a falling edge signal. However, in some embodiments, the signal required by the TDC is a rising edge signal. That is, when the first photon signal is not received, the input level of the TDC is low, and when the first photon signal is received, the input level of the TDC transitions from low to high.

[0104] Based on this, as a feasible implementation method, such as Figure 14 As shown, the detection circuit provided in this embodiment of the application also includes an inverter 116, and the output node is connected to the output terminal of the detection circuit through the inverter 116.

[0105] Inverter 116 is used to reverse the phase of the input signal by 180 degrees, that is, if the input is high, the output is low; if the input is low, the output is high.

[0106] Therefore, by setting an inverter 116 between the output node ZN and the output terminal OUT of the detection circuit, the phase of the first photon signal can be reversed by 180 degrees when the output node transitions from a high level to a low level and outputs a low-level first photon signal, so that the level of the first photon signal becomes a high level, that is, the output first photon signal is a rising edge signal.

[0107] In other embodiments, the photon trigger signal received by the detection circuit is a falling edge signal, that is, the level state of the third terminal of the first input sub-circuit and the third terminal of the second input sub-circuit is a transition from high level to low level (i.e., a transition from 1 to 0), indicating that a photon trigger signal has been received.

[0108] Based on this, as a feasible implementation method, please refer to Figure 15 The detection circuit provided in this application embodiment, when the photon reflection signal received by the detection circuit is a falling edge signal, includes a first input sub-circuit comprising a PMOS transistor and a second input sub-circuit comprising an NMOS transistor; the first voltage signal terminal 113 is configured to output a high voltage signal (e.g., ...). Figure 15 As shown in VDD), the second voltage signal terminal 115 is configured to output a low voltage signal (e.g., VDD). Figure 15 (As shown in GND).

[0109] Since the gate of the NMOS transistor is in a high-level state (conducting), the second input sub-circuit 114 includes an NMOS transistor. This ensures that when no photon trigger signal Ai (A1, A2…An) is received, the third terminal of the second input sub-circuit is at a high level, the second input sub-circuit is conducting, and the output terminal OUT of the detection circuit is connected to the second voltage signal terminal 115. The detection circuit receives the low-voltage signal output from the second voltage signal terminal 115, causing the output terminal OUT of the detection circuit to be at a low level. When a photon trigger signal Ai (A1, A2…An) is received, the level of the third terminal of the second input sub-circuit changes from high to low, and the second input sub-circuit 114 is in a disconnected state.

[0110] When the gate of a PMOS transistor is at a lower potential (low level) than its source, it is in the ON state. Therefore, the first input sub-circuit 111 includes a PMOS transistor such that when no photon trigger signal Ai (A1, A2...An) is received, the level of the third terminal of the first input sub-circuit is high, and the first input sub-circuit 111 is in the OFF state.

[0111] When a photon trigger signal is received, the level of the third terminal of the first input sub-circuit changes from high to low, the first input sub-circuit 111 is in the conducting state, the output terminal OUT of the detection circuit is connected to the first voltage signal terminal 113, and the high voltage signal output by the first voltage signal terminal 113 is received, causing the output terminal OUT of the detection circuit to change from low to high, thereby outputting the first photon signal.

[0112] As can be seen, in this embodiment, when the output level of the detection circuit transitions from low to high, it outputs the first photon signal, which is a rising edge signal. However, in some embodiments, the signal required by the TDC is a falling edge signal. That is, when the first photon signal is not received, the input level of the TDC is high, and when the first photon signal is received, the input level of the TDC transitions from high to low.

[0113] Based on this, as a feasible implementation method, such as Figure 16 As shown, the detection circuit provided in this embodiment of the application also includes an inverter 116, and the output node is connected to the output terminal of the detection circuit through the inverter 116.

[0114] Inverter 116 is used to reverse the phase of the input signal by 180 degrees, that is, if the input is high, the output is low; if the input is low, the output is high.

[0115] Therefore, by setting an inverter 116 between the output node ZN and the output terminal OUT of the detection circuit, when the level state of the output node ZN changes from low to high and outputs a low-level first photon signal, the phase of the first photon signal is reversed by 180 degrees, so that the level state of the first photon signal becomes low, that is, the output first photon signal is a falling edge signal.

[0116] In some embodiments, a core characteristic of transistors is that their conductivity can be precisely adjusted by controlling the gate voltage. When the gate voltage changes, the concentration of charge carriers (electrons or holes) in the transistor channel changes, thus affecting the channel's conductivity. This controllable conductivity allows transistors to be used as current controllers, controlling the amount of current flowing through the transistor by adjusting the gate voltage. Furthermore, transistors have high input impedance and low output impedance under normal operating conditions. High input impedance means the transistor has less influence on the input signal and can more accurately reflect changes in the input signal; while low output impedance allows the transistor to drive load circuits more effectively. This characteristic enables transistors to provide more stable and reliable current control when used as current controllers. Therefore, current controller circuits can be designed based on the characteristics of transistors.

[0117] As one feasible implementation, the current control circuit 112 includes a first transistor, the first terminal of which is connected to the first terminal of the current control circuit, and the second terminal of which is connected to the second terminal of the current control circuit; the control terminal of the first transistor is configured to receive a first control signal, which is used to make the first transistor operate in the saturation region.

[0118] In the saturation region, the transistor's output current has reached or is close to its maximum value, and the relationship between this current value and the input current weakens. In other words, by having the control electrode of the first transistor receive a first control signal, and adjusting the voltage value of the first control signal, the first transistor operates in the saturation region. This ensures that the current flowing through the first transistor remains within a preset range, achieving the effect of current control.

[0119] As a feasible implementation method, when the photon trigger signal received by the detection circuit is a rising edge, the first transistor can be an NMOS transistor.

[0120] For example, when the first transistor is an NMOS transistor, the structure of the current control circuit 112 can be as follows: Figure 17 As shown, the first terminal 112a of the first transistor is connected to the first terminal of the control circuit, and the second terminal 112b of the first transistor is connected to the second terminal of the control circuit; the control terminal 112c of the first transistor is configured to receive the first control signal.

[0121] When an NMOS transistor operates in the saturation region, the drain current (Id) is primarily controlled by the voltage difference (Vgs) between the gate (i.e., control electrode 112c) and the source (i.e., first electrode 112a), and is largely independent of the voltage difference (Vds) between the source and drain (i.e., second electrode 112b). This is because, in the saturation state, the channel is pinched off near the drain, causing the drain current to tend towards saturation and no longer significantly increase with increasing Vds. Therefore, when the first transistor is an NMOS transistor, the voltage of the first control signal can be greater than or equal to the threshold voltage (Vth), allowing the NMOS transistor to operate in the saturation region. This ensures that the current flow rate through the first transistor remains within a preset range, achieving current control.

[0122] As a feasible implementation method, when the photon trigger signal received by the detection circuit is a falling edge, the first transistor can be a PMOS transistor.

[0123] For example, when the first transistor is a PMOS transistor, the structure of the control sub-circuit can be as follows: Figure 18 As shown, the first terminal 112a of the first transistor is connected to the first terminal of the control circuit, and the second terminal 112b of the first transistor is connected to the second terminal of the control circuit; the control terminal 112c of the first transistor is configured to receive the first control signal.

[0124] When a PMOS transistor operates in the saturation region, the channel is pinched off near the drain, causing the drain current to saturate. At this point, even if the drain voltage continues to increase, the drain current cannot increase further due to the channel pinch-off limitation. Therefore, when the first transistor is a PMOS transistor, the difference between the voltage of the first control signal and the source voltage (Vgs-Vs) needs to be higher than the threshold voltage (Vth) to ensure the PMOS transistor operates in the saturation region. This allows the current flow rate through the first transistor to be kept within a preset range, achieving current control.

[0125] In other embodiments, since a current mirror is a standard component widely used in analog integrated circuits, it utilizes the current replication characteristic of transistors to mirror or replicate the input current of an active device to the output of other active devices. This allows the current of multiple current branches to be indirectly controlled by controlling a single current signal terminal, thereby achieving precise current distribution and regulation.

[0126] Therefore, as another feasible implementation method, the current control circuit includes a current mirror circuit and a second transistor.

[0127] The first terminal of the current mirror circuit is connected to the current signal terminal, the second terminal of the current mirror circuit is connected to the second terminal of the current control circuit, and the third terminal of the current mirror circuit is connected to the control electrode of the second transistor. The current value of the current signal output by the current signal terminal is within a preset range. The first electrode of the second transistor is connected to the first terminal of the current control circuit, and the second electrode of the second transistor is connected to the second terminal of the current control circuit.

[0128] A current mirror is used to precisely replicate or scale current. The basic idea is to use the equality of the gate-source voltages of two or more transistors (typically MOS transistors) to ensure that the currents flowing through them are equal or proportional. The principle behind current mirroring is based on the gate-source voltage control characteristics of transistors. When the gate-source voltage of a transistor exceeds its threshold voltage, the transistor begins to conduct, and its current is proportional to the square of the gate-source voltage (in the saturation region). Since the transistor gates in a current mirror are interconnected, their gate-source voltages are equal. If their threshold voltages are also equal (or very close), the currents flowing through them will also be equal (or proportional).

[0129] Therefore, by controlling the current value output from the current signal terminal connected to the current mirror circuit to be within a preset range, the magnitude of the current flowing through the first transistor can be controlled, so that the magnitude of the current flowing from the output node to the first voltage signal terminal is within the preset range.

[0130] In some embodiments, when the photon trigger signal received by the detection circuit is a rising edge, as a feasible implementation method, please refer to [link to relevant documentation]. Figure 19 The second transistor M1 in the current control circuit can be an NMOS transistor, and the current mirror circuit ( Figure 19 The structure shown in the dashed box can be a current mirror circuit composed of an NMOS transistor M2.

[0131] like Figure 19 As shown, M1 and M2 have the same gate-source voltage VGS. Ideally, if the two transistors have the same dimensions (e.g., aspect ratio W / L) and process constants, then their drain currents will also be the same. That is, the current in M1 is actually a mirror image of the current in M2, and their corresponding current values ​​are equal.

[0132] As another feasible implementation method, please refer to Figure 20 The current control circuit may include two NMOS transistors and a common-source cascode current mirror circuit. Figure 20 (As shown in the dashed box). Figure 20 As shown, the common-source cascode current mirror circuit can be either a first common-source cascode current mirror circuit or a second common-source cascode current mirror circuit.

[0133] like Figure 20As shown, the structure of a common-source, common-gate current mirror mainly consists of two NMOS transistors, two voltage dividers, and some connecting wires: The first transistor (usually called a common-source transistor) consists of a source junction and a gate junction, used to acquire the input current. The second NMOS transistor (usually called a common-gate transistor) also consists of a source junction and a gate junction, used to output the regulated current. The two voltage dividers are responsible for distributing a small portion of the input current as a reference for the output current. The connecting wires are used to connect the input and output transistors together, forming a closed loop.

[0134] The common-source cascode current mirror has a simple structure, is easy to implement, and has high stability, feedback strength, and current mirror accuracy. It can efficiently convert the input current into an almost equal output current.

[0135] In a cascode current mirror, the gate voltage of the transistor (especially the common-gate transistor) is crucial for maintaining normal circuit operation and achieving accurate current replication. The stability and accuracy of the gate voltage directly affect the transistor's conduction state and the magnitude of the output current. Therefore, as a feasible implementation, the cascode current mirror circuit can also be connected to a voltage signal terminal, such as... Figure 20 The voltage signal terminal VB in the second cascode current mirror circuit is used to provide a stable voltage to the gate of the transistor, so that the cascode current mirror can stably replicate the current.

[0136] In other embodiments, where the photon trigger signal received by the detection circuit is a falling edge, as one feasible implementation, please refer to [link to relevant documentation]. Figure 21 The second transistor in the current control circuit can be a PMOS transistor M1, and the current mirror circuit can be a current mirror circuit composed of a PMOS transistor M2.

[0137] like Figure 21 As shown, M1 and M2 have the same gate-source voltage VGS. Ideally, if the two transistors have the same dimensions (e.g., aspect ratio W / L) and process constants, then their drain currents will also be the same. That is, the current in M1 is actually a mirror image of the current in M2, and their corresponding current values ​​are equal.

[0138] As another feasible implementation method, please refer to Figure 22 The current control circuit can include two PMOS transistors and a common-source, common-gate current mirror circuit. For example... Figure 22 As shown, the common-source cascode current mirror circuit can be a third or fourth common-source cascode current mirror circuit.

[0139] like Figure 22As shown, the structure of a common-source, common-gate current mirror mainly consists of two PMOS transistors, two voltage dividers, and some connecting wires: The first PMOS transistor (usually called a common-source transistor) is composed of a source junction and a gate junction, used to acquire the input current. The second PMOS transistor (usually called a common-gate transistor) is also composed of a source junction and a gate junction, used to output the regulated current. The two voltage dividers are responsible for distributing a small portion of the input current as a reference for the output current. The connecting wires are used to connect the input and output transistors together, forming a closed loop.

[0140] The common-source cascode current mirror has a simple structure, is easy to implement, and has high stability, feedback strength, and current mirror accuracy. It can efficiently convert the input current into an almost equal output current.

[0141] As a feasible implementation method, the cascode current mirror circuit can also be connected to a voltage signal terminal, such as... Figure 22 The voltage signal terminal VB in the fourth cascode current mirror circuit is used to provide a stable voltage to the gate of the transistor, so that the cascode current mirror can stably replicate the current.

[0142] This application also provides a lidar, including a laser emitter, a laser receiver, a time-to-digital converter, a processor, and a detection circuit provided in any of the above embodiments.

[0143] The system comprises a laser emitter and a time-to-digital converter (TD-SCDMA) connected to a processor, and a detection circuit connected to both a laser receiver and the TD-SCDMA. The laser emitter is configured to emit photon signals. The laser receiver is configured to receive photon signals reflected back from the target object and output a photon trigger signal to the detection circuit. The detection circuit is configured to output a first photon signal based on the photon trigger signal. The TD-SCDMA is used to determine the time difference between emitting and receiving the first photon signal based on the delay of the first photon signal, and converts the time difference into a digital code to be sent to the processor. The processor is configured to determine the distance between the lidar and the target object based on the digital code.

[0144] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0147] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0148] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0149] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A detection circuit, characterized in that, It includes multiple first input sub-circuits connected in parallel, and a current control sub-circuit; The first terminals of the plurality of first input sub-circuits are all connected to the output node, the output node is connected to the output terminal of the detection circuit, the second terminals of the plurality of first input sub-circuits are all connected to the first terminal of the current control sub-circuit, and the third terminal of each first input sub-circuit is configured to receive a photon trigger signal. The second terminal of the current control sub-circuit is connected to the first voltage signal terminal; The first input sub-circuit is configured to turn on in response to the received photon trigger signal, so that the output terminal of the detection circuit is connected to the first voltage signal terminal, and the output terminal of the detection circuit outputs the first photon signal; The current control sub-circuit is configured to control the current flowing through it within a preset range.

2. The detection circuit according to claim 1, characterized in that, The detection circuit also includes a plurality of second input sub-circuits connected in series; In the plurality of second input sub-circuits, the second terminal of the preceding second input sub-circuit is connected to the first terminal of the following second input sub-circuit, the first terminal of the first second input sub-circuit is connected to the second voltage signal terminal, and the second terminal of the last second input sub-circuit is connected to the output node; the third terminal of each second input sub-circuit is configured to receive the photon trigger signal; there is a potential difference between the voltage signals output by the first voltage signal terminal and the second voltage signal terminal; The second input sub-circuit is configured to turn on when the photon trigger signal is not received, so that the output of the detection circuit is connected to the second voltage signal terminal.

3. The detection circuit according to claim 2, characterized in that, The first input sub-circuit includes an NMOS transistor, and the second input sub-circuit includes a PMOS transistor; The first voltage signal terminal is configured to output a low voltage signal, and the second voltage signal terminal is configured to output a high voltage signal.

4. The detection circuit according to claim 3, characterized in that, The current control sub-circuit includes an NMOS transistor.

5. The detection circuit according to claim 2, characterized in that, The first input sub-circuit includes a PMOS transistor, and the second input sub-circuit includes an NMOS transistor; The first voltage signal terminal is configured to output a high voltage signal, and the second voltage signal terminal is configured to output a low voltage signal.

6. The detection circuit according to claim 5, characterized in that, The current control circuit includes a PMOS transistor.

7. The detection circuit according to any one of claims 1-6, characterized in that, The detection circuit also includes an inverter, and the output node is connected to the output terminal of the detection circuit through the inverter.

8. The detection circuit according to any one of claims 1-6, characterized in that, The current control sub-circuit includes a first transistor, the first terminal of which is connected to a first terminal of the current control sub-circuit, and the second terminal of which is connected to a second terminal of the current control sub-circuit. The control electrode of the first transistor is configured to receive a first control signal, which is used to make the first transistor operate in the saturation region.

9. The detection circuit according to any one of claims 1-6, characterized in that, The current control sub-circuit includes a current mirror circuit and a second transistor; The first terminal of the current mirror circuit is connected to the current signal terminal, the second terminal of the current mirror circuit is connected to the second terminal of the current control sub-circuit, and the third terminal of the current mirror circuit is connected to the control electrode of the second transistor; the current value of the current signal output by the current signal terminal is within a preset range. The first terminal of the second transistor is connected to the first terminal of the current control circuit, and the second terminal of the second transistor is connected to the second terminal of the current control circuit.

10. A lidar, characterized in that, Includes a laser emitter, a laser receiver, a time-to-digital converter, a processor, and a detection circuit as described in any one of claims 1-9; The laser emitter and the time-to-digital converter are respectively connected to the processor, and the detection circuit is respectively connected to the laser receiver and the time-to-digital converter; The laser emitter is configured to emit photon signals; The laser receiver is configured to receive the photon signal reflected back by the target object and output a photon trigger signal to the detection circuit; The detection circuit is configured to output a first photon signal based on the photon trigger signal; The time-to-digital converter is used to determine the time of transmitting the photon signal and the time difference of receiving the first photon signal based on the delay of the first photon signal, and convert the time difference into a digital code and send it to the processor; The processor is configured to determine the distance between the lidar and the target object based on the digital code.

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