Data acquisition method and device, electronic equipment and readable storage medium

Abstract

Embodiments of the present application provide a data acquisition method and device, electronic equipment and readable storage medium, in the case where the first cache does not contain target data, the first cache sends a data acquisition request corresponding to the target data to the second cache; the cache level of the first cache is higher than that of the second cache; if the difference between the current time and the sending time of the data acquisition request is greater than the average access delay, the target adjacent data is acquired based on the target data address indicated by the data acquisition request and the preset prefetch granularity; and the target adjacent data is cached to the second cache. In this way, it can be predicted whether the target data is missing in the second cache, without explicitly determining whether the target data is missing in the second cache. In the case where the difference is greater than the average access delay, the target adjacent data of the target data is directly prefetched, the prefetching opportunity is advanced, the additional waiting time caused by waiting to confirm the missing data of the second cache is avoided, and the data access delay is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a data acquisition method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] In modern high-performance processors, a tiered cache hierarchy, such as L1, L2, and L3 caches, is commonly used to mitigate the significant speed difference between the processor core (CPU) and main memory (DRAM). L1 and L2 caches are typically integrated within the processor core, offering lower access latency, while L3 caches are usually located off-core, offering larger capacity but significantly increased access latency.

[0003] In related technologies, to reduce the overhead caused by data retrieval misses, considering the temporal and spatial locality of the program itself, access patterns are often learned based on the missing information in the L1 or L2 caches. This predicts the data that may be accessed next and then retrieves it in advance; this process is called prefetching. However, this prefetching method often results in L1 or L2 caches generating prefetches over long distances, which are then sent to L3. This requires waiting for the target level cache (L3) to return whether the data is missing along with the target data, and then using that missing information for prefetching. This results in relatively high data access latency, increasing bus pressure and power consumption. Summary of the Invention

[0004] To overcome the problems existing in related technologies, the present invention provides a data acquisition method, apparatus, electronic device, and readable storage medium.

[0005] In a first aspect, the present invention provides a data acquisition method, the method comprising: If the first cache does not contain the target data, the first cache sends a data retrieval request corresponding to the target data to the second cache; the cache level of the first cache is higher than that of the second cache. If the difference between the current time and the time when the data acquisition request was sent is greater than the average access latency, then target neighboring data is acquired based on the target data address indicated by the data acquisition request and the preset prefetch granularity. The target proximity data is cached in the second cache.

[0006] In a second aspect, the present invention provides a data acquisition device, the device comprising: The first sending module is used to send a data retrieval request corresponding to the target data from the first cache to the second cache when the first cache does not contain the target data; the cache level of the first cache is higher than the cache level of the second cache; The first acquisition module is used to acquire target neighbor data based on the target data address indicated by the data acquisition request and a preset prefetching granularity if the difference between the current time and the sending time of the data acquisition request is greater than the average access delay. The first caching module is used to cache the target proximity data to the second cache.

[0007] Thirdly, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the data acquisition method described in any one of the first aspects above.

[0008] Fourthly, the present invention provides a readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform steps in the data acquisition method as described in any of the embodiments of the first aspect above.

[0009] In this embodiment of the invention, when the first cache does not contain the target data, a data retrieval request corresponding to the target data is sent from the first cache to the second cache. The cache level of the first cache is higher than that of the second cache. If the difference between the current time and the time when the data retrieval request is sent is greater than the average access latency, then the target's neighboring data is retrieved based on the target data address indicated by the data retrieval request and a preset prefetch granularity. The target's neighboring data is then cached in the second cache. In this way, the difference between the current time and the time when the data retrieval request is sent can be used to predict whether the target data indicated by the data retrieval request is missing in the second cache. Without explicitly stating whether the target data is missing in the second cache, the target's neighboring data is directly prefetched when the difference is greater than the average access latency. This advances the prefetching timing, avoiding the extra waiting time caused by waiting to confirm the second cache's missing data, and effectively reducing data access latency. Simultaneously, advance prefetching can satisfy subsequent data requests faster, reducing performance loss caused by cache misses, enabling the system to process data access tasks more efficiently, and significantly improving overall performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of the steps of a data acquisition method provided in an embodiment of the present invention; Figure 2This is a flowchart of a prefetching process provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a STATE state machine transition provided in an embodiment of the present invention; Figure 4 This is a flowchart of a data backfilling process provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the framework of a data prefetcher provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a dynamic prefetch granularity adjustment strategy provided in an embodiment of the present invention; Figure 7 This is a structural diagram of a data acquisition device provided in an embodiment of the present invention; Figure 8 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] Figure 1 This is a flowchart of the steps of a data acquisition method provided in an embodiment of the present invention, as follows: Figure 1 As shown, the method may include: Step 101: If the first cache does not contain the target data, the first cache sends a data retrieval request corresponding to the target data to the second cache; the cache level of the first cache is higher than that of the second cache.

[0014] In this embodiment of the invention, when the first cache receives a data retrieval request, it searches the first cache to see if it contains the target data indicated by the data retrieval request. If the first cache does not contain the target data, it sends a data retrieval request to the lower-level cache, namely the second cache, to search for the target data in the second cache. The first cache has a higher cache level than the second cache. The first cache can be a cache within the processor core, and the second cache can be a cache located below the first cache and outside the processor core. For example, taking a three-level cache (L1, L2, L3 cache) as an example, the first cache can be an L2 cache, and the second cache can be an L3 cache.

[0015] For example, when a memory access request is missing at the current cache level (i.e., the required data is not in the current cache), the request will be sent to the next level cache to retrieve the data. At this time, the current cache level needs to temporarily store this memory access request to maintain the missing state; this is the role of the MissQueue. Therefore, if the first cache does not contain the target data, i.e., when the access request to the first cache is missing, it will enter the MissQueue and be allocated a Miss State Handle Register (MSHR), and then the MissQueue will send the access request to the next level cache.

[0016] Optionally, after step 101, the embodiments of the present invention may further include the following steps: Step 201: Update the missing clock value corresponding to the data acquisition request in the first cache data prefetcher to the current time.

[0017] Step 202: Set the data acquisition status corresponding to the data acquisition request to a missing status.

[0018] In this embodiment of the invention, while the first cache sends a data fetch request to the second cache, the data fetch information corresponding to the data fetch request can be recorded in the data prefetcher (Next-level Adjacent Prefetch, NAP) in the first cache. The data fetch information may include the time when the first cache sends the data fetch request to the second cache and the data fetch status. For example, the missing clock value (missClock) corresponding to the target data address indicated by the data fetch request in the data prefetcher can be set to the current clock (currClock), and the data fetch status (state) of the STATE state machine can be set to the missing state (MISS).

[0019] In this way, by recording the missing clock value as the current time, the moment when the data is missing can be clearly identified, which facilitates subsequent analysis of time intervals; setting the data acquisition status to missing status allows for a direct assessment of the data acquisition situation.

[0020] Step 102: If the difference between the current time and the time when the data acquisition request was sent is greater than the average access delay, then acquire the target neighbor data based on the target data address indicated by the data acquisition request and the preset prefetch granularity.

[0021] In this embodiment of the invention, if the difference between the current time (currClock) and the time when the data acquisition request was sent (missClock) is greater than the average access latency, it indicates a high probability that the target data in the second cache is missing. Therefore, the predicted data that may be accessed next can be prefetched. Based on the target data address indicated by the data acquisition request and the preset prefetch granularity, the data that may be accessed next, i.e., the prefetch address of the target's neighboring data, is calculated, and the target's neighboring data is obtained based on the prefetch address.

[0022] The average access latency can be determined based on the historical latency of the data retrieval process between the first cache and the second cache. The average access latency can be recorded by a register "L3 HitLatency" in the data prefetcher. If the difference between the current time and the sending time is greater than the average access latency, it means that the data retrieval request sent from the first cache to the second cache has exceeded the normal access latency between the first cache and the second cache. The probability of retrieving the target data in the second cache is reduced, that is, the probability of missing the target data in the second cache is increased. Therefore, prefetching can be performed in advance to reduce the high latency caused by cache miss.

[0023] The preset prefetch granularity can be set according to actual needs. For example, the preset prefetch granularity can be 256 bytes. For instance, if the difference between the current time and the time when the data retrieval request is sent is greater than the average access latency, indicating that the data retrieval request to access the second cache has a very high probability of missing, then the 256-byte address aligned with the miss address, i.e., the target data address indicated by the data retrieval request, can be used as the prefetch address, and the target adjacent data corresponding to the prefetch address, i.e., the 256 bytes of data after the prefetch address, can be retrieved.

[0024] Step 103: Cache the target proximity data into the second cache.

[0025] In this embodiment of the invention, the target's neighboring data is cached in a second cache. By caching the target's neighboring data in advance in the second cache, it becomes easier to hit the target's neighboring data block in the second cache next time, avoiding misses and thus saving data retrieval time.

[0026] In summary, in this embodiment of the invention, when the first cache does not contain the target data, a data retrieval request corresponding to the target data is sent from the first cache to the second cache. The cache level of the first cache is higher than that of the second cache. If the difference between the current time and the time when the data retrieval request is sent is greater than the average access latency, then target neighboring data is retrieved based on the target data address indicated by the data retrieval request and the preset prefetch granularity. The target neighboring data is then cached in the second cache. In this way, the difference between the current time and the time when the data retrieval request is sent can be used to predict whether the target data indicated by the data retrieval request is missing in the second cache. Without explicitly stating whether the target data is missing in the second cache, if the difference is greater than the average access latency, the target neighboring data is directly prefetched, advancing the prefetching timing and avoiding the extra waiting time caused by waiting to confirm the missing data in the second cache, effectively reducing data access latency. Simultaneously, early prefetching can satisfy subsequent data requests faster, reducing the performance loss caused by cache misses, enabling the system to process data access tasks more efficiently, and significantly improving overall performance.

[0027] Furthermore, by using targeted data prefetching (i.e., prefetching data that is likely to be missing in the second cache), the bandwidth consumption caused by invalid prefetch data transmission due to unconditional prefetching can be reduced, making more reasonable use of bandwidth resources and improving the overall performance and efficiency of the system.

[0028] Furthermore, when the second cache is located outside the core, the embodiments of the present invention can be fully implemented within the core without any modification to the IP (Intellectual Property) of the second cache. This is applicable to SoC designs where the second cache is located outside the core or provided by third-party IP, reducing the difficulty of engineering implementation and development costs.

[0029] Optionally, step 102 may include the following steps: Step 301: Obtain the data acquisition status corresponding to the target data.

[0030] In this embodiment of the invention, the data acquisition status corresponding to the data acquisition request recorded in the data prefetcher is obtained.

[0031] Step 302: If the data acquisition status is missing, and the difference between the current time and the time when the data acquisition request was sent is greater than the average access delay, then the prefetch address is determined based on the target data address indicated by the data acquisition request and the preset prefetch granularity.

[0032] In this embodiment of the invention, it is determined whether the data acquisition status is in a missing state. If so, it means that the first cache has not yet acquired the target data during the process of speculating the hit delay. That is, the first cache has not received the target data during the period from marking the data acquisition status as missing to determining that "the difference between the current time and the sending time of the data acquisition request is greater than the average access delay". When the data acquisition status is in a missing state, it is determined whether the difference between the current time and the sending time of the data acquisition request is greater than the average access delay. If the data prefetcher of the first cache determines that the difference between the current time and the sending time of the data acquisition request is greater than the average access delay, then the prefetch address is determined based on the target data address indicated by the data acquisition request and the preset prefetch granularity.

[0033] Step 303: Send a prefetch request to the second cache based on the prefetch address to obtain the target neighbor data corresponding to the prefetch address.

[0034] In this embodiment of the invention, a prefetching request is generated based on a prefetching address by a data prefetcher of a first cache, and the prefetching request is sent to a second cache. The second cache responds to the prefetching address indicated by the prefetching request and obtains the target neighbor data corresponding to the prefetching address.

[0035] For example, Figure 2 A flowchart illustrating the steps of a prefetching process is shown, such as... Figure 2 As shown, the difference between the current time and the time the data retrieval request was sent is used to infer whether the second cache is missing. If it is missing, a prefetch request is generated. If the data retrieval status is MISS, it means that no data was received within the inferred hit delay. Therefore, based on the target data address indicated by the data retrieval request and the preset prefetch granularity, a prefetch request is generated and sent to the second cache, and the data retrieval status of the data corresponding to the adjacent data of the target is updated to the prefetch status (PREFETCH).

[0036] In this embodiment of the invention, by first obtaining the target data acquisition status, and if it is in a missing state and the time difference exceeds the average access latency, the prefetch address is determined and a request is sent to obtain nearby data. This can filter out the cases where data truly needs to be prefetched, avoid blindly prefetching existing data, reduce invalid operations, reduce bandwidth waste, and improve prefetching efficiency.

[0037] Optionally, embodiments of the present invention may further include the following steps: Step 401: When the first cache receives the target data, set the data acquisition status corresponding to the target data to the filling status.

[0038] In this embodiment of the invention, if the target data is not contained in the first cache, the target data will be obtained through the second cache or memory. If the target data is received in the first cache, the target data can be backfilled, and the data acquisition status of the target data in the first cache will be updated from the missing status to the filled status (REFILL) to avoid repeated prefetching.

[0039] For example, Figure 3 A schematic diagram of a STATE state machine transition is shown. When the first buffer does not contain the target data, the state of the target data is updated to MISS. If L3 data is missing, it is inferred from the difference between the current time and the time the data retrieval request was sent. Therefore, prefetching is required, and the state of the prefetched neighboring data is updated to PREFETCH. When the target data is refilled into the first buffer, the state of the corresponding data is updated to REFILL.

[0040] Step 402: Update the average access delay based on the first access delay corresponding to the target data; the first access delay is used to characterize the time interval from the first time when the first cache sends a data retrieval request to the second cache to the second time when the first cache receives the target data.

[0041] In this embodiment of the invention, the average access delay is updated based on the first access delay corresponding to the target data. The first access delay characterizes the time interval between the first cache sending a data retrieval request to the second cache and the second time the first cache receives the target data; that is, the access delay from the first cache issuing the data retrieval request to receiving the target data. The average access delay is updated based on the relationship between the first access delay and the original average access delay.

[0042] Optionally, step 402 may include the following steps: Step 501: If the absolute value of the difference between the first access delay and the average access delay is less than a preset difference, update the average access delay to a moving average of the first access delay and the average access delay.

[0043] In this embodiment of the invention, it is determined whether the absolute value of the difference between the first access delay and the average access delay is less than a preset difference. If the absolute value of the difference between the first access delay and the average access delay is less than the preset difference, the average access delay can be updated to a moving average of the first access delay and the average access delay, that is, the register is updated based on the original value in the register and the moving average of the first access delay. The preset difference can be 10, meaning the difference between the first access delay and the average access delay is within 10 ticks. The new average access delay can be recorded using a moving average calculation component that combines addition and right shift.

[0044] Step 502: If the average access delay is greater than the first access delay and the difference between the average access delay and the first access delay is greater than or equal to the preset difference, update the average access delay to the first access delay.

[0045] In this embodiment of the invention, when the average access delay is greater than the first access delay and the difference between the average access delay and the first access delay is greater than or equal to a preset difference, the average access delay is directly updated to the first access delay, that is, the value in the register is updated to the first access delay.

[0046] It is understandable that when the average access delay is 0, the first access delay can be directly assigned to the average access delay, that is, the average access delay can be directly updated to the first access delay, that is, the value in the register can be updated to the first access delay.

[0047] This method of updating the average access latency allows for adjustment of the average access latency during multiple data retrieval processes. This ensures that the average access latency can represent the general access latency of data retrieval requests sent from the first cache to the second cache that successfully hit data in the second cache. Specifically, since the hit latency of the first cache (i.e., the target data can be directly retrieved from the second cache) is much smaller than the miss latency (i.e., the target data is not contained in the second cache and needs to be retrieved using other methods), when the first access latency is less than the average access latency, the first access latency will be closer to the hit latency. Furthermore, if the absolute value of the difference between the first access latency and the average access latency is less than a preset difference, it may indicate that this difference is due to errors caused by fluctuations. Adjusting with a moving average allows the average access latency to reflect the true hit latency between the first and second caches. Furthermore, when the difference between the current time and the time when the data retrieval request is sent is greater than the average access latency, it indicates that the elapsed time has exceeded the actual hit latency between the first cache and the second cache. The probability of a data hit is greatly reduced, while the probability of a data miss is greatly increased. Therefore, using the difference between the current time and the time when the data retrieval request is sent being greater than the average access latency as a prefetching trigger condition can more accurately determine the situation where prefetching is truly needed.

[0048] For example, the following illustrates a process for updating the average access latency: Assuming the first cache is L2 and the second cache is L3, then: (1) Initial: L3HitLatency (average access latency) = 0; Since L3 is initially empty, the result of L2 sending a data retrieval request to L3 is also missing. At this time, accessLatency (first access delay) = 175, so L3HitLatency is updated to 175.

[0049] (2) The data acquisition process of L2 sending a data acquisition request to L3 for the second time. Since L3 has not yet warmed up, the result of the data acquisition request is also missing. At this time, accessLatency=173, and L3HitLatency is updated to 174.

[0050] (3) The data acquisition process in which L2 sends a data acquisition request to L3 for the third time. At this time, L3 is assumed to have been warmed up. At this time, L2's data acquisition request hits L3. At this time, accessLatency=37, so L3HitLatency is updated to 37.

[0051] (4) The fourth time L2 sends a newer data retrieval request to L3, L3 is missing. At this time, accessLatency=176, so L3HitLatency remains unchanged at 37.

[0052] (5) The data acquisition process of L2 sending a data acquisition request to L3 for the fifth time. When L3 hits the target data, accessLatency=35, then L3HitLatency is updated to 36.

[0053] The above example shows that during the later data acquisition process, the average access latency value will be updated and adjusted mainly based on the hit latency value, so that the average access latency will get closer and closer to the actual hit latency state between the first cache and the second cache.

[0054] For example, Figure 4 A flowchart of the data backfilling process, such as Figure 3As shown, when the first cache is filled with target data, the data acquisition state (state) and the average access latency (L3HitLatency) are updated. Specifically, the first access latency (accessLatency) = the second time (currClock) when the first cache receives the target data - the first time (missClock) when the first cache sends a data acquisition request to the second cache. The data acquisition state is updated to the filling state. When the average access latency (L3HitLatency) is 0, the average access latency (L3HitLatency) is directly assigned to the first access latency (accessLatency); when the absolute value of the difference between the first access latency and the average access latency is less than a preset difference (range), the average access latency is updated to the moving average of the first access latency and the average access latency; when the average access latency is greater than the first access latency (since it has been determined in the previous step that the absolute value of the difference between the first access latency and the average access latency is not less than the preset difference, the condition "the difference between the average access latency and the first access latency is greater than or equal to the preset difference" is hidden in this step), the average access latency is directly updated to the first access latency, that is, the value in the register is updated to the first access latency.

[0055] For example, Figure 5 The diagram illustrates a framework for a data prefetcher. Assuming the first cache is L2 and the second cache is L3, when L2 does not contain the target data, the MissQueue in L2 temporarily stores the demand miss request. Simultaneously, the data prefetcher sets the corresponding miss clock value (missClock) and data acquisition state (state) for that data acquisition request. The data prefetcher infers whether L3 is missing target data based on the difference between the current time and the time the data acquisition request was sent. If missing, a prefetch request is generated. When L2 acquires the target data (i.e., when the data is backfilled), the data acquisition state (state) and average access latency (L3HitLatency) are updated simultaneously.

[0056] In this embodiment of the invention, by updating the average access delay based on the actual first access delay, the average access delay can be made to better reflect the actual situation, providing an accurate basis for subsequent judgments, avoiding invalid prefetching and other operations due to deviations in the average value, and improving the efficiency of the caching system.

[0057] Optionally, embodiments of the present invention may further include the following steps: Step 601: For any granularity adjustment period, obtain the number of times the data retrieval request corresponding to the first cache with missing data matches the data prefetch request sent by the first cache to the second cache, and use this as the historical prefetch hit count.

[0058] In this embodiment of the invention, a dynamic prefetch granularity adjustment strategy can be set based on a sandbox. Specifically, it can be: using the number of items in the miss queue as a granularity adjustment period. When the first cache does not contain the target data, it will enter the miss queue; that is, the first cache generates a demand miss request, and the demand access will be temporarily stored in the miss queue. When a demand miss request with the same number of items as the miss queue is generated, it is considered a period node. At the period node, the preset prefetch granularity is adjusted.

[0059] Within a granularity adjustment period, the data prefetch requests sent by the statistical prefetcher are counted. For any data prefetch request, the hash value of the prefetch address corresponding to the data prefetch request is recorded as an index, and the historical prefetch hit count (cnt) of whether the prefetch is valid and the data demand miss request corresponding to the first cache with a data missing state is recorded as the item content.

[0060] A data retrieval request with a missing data result in the first cache matches a data prefetch request sent from the first cache to the second cache. This means the address corresponding to the data retrieval request with a missing data result in the first cache is the same as the prefetch address of the data prefetch request sent from the first cache to the second cache. In other words, whenever a data retrieval request in the first cache results in a missing data result, if the data address corresponding to that data retrieval request is the same as the prefetch address corresponding to any recorded data prefetch request, the historical prefetch hit count corresponding to that prefetch address is incremented by 1. The historical prefetch hit count can be used to characterize the efficiency gains brought by prefetching; the larger the historical prefetch hit count, the more times the prefetched data is retrieved subsequently, and the more effective the prefetch mechanism is.

[0061] For example, suppose the record prefetch addresses include a, b, and c. The first cache receives a data retrieval request for address c, but the first cache does not contain the data for address c. The data retrieval result is data missing. In this case, address c is the same as prefetch address c, so the historical prefetch hit count corresponding to prefetch address c is incremented by 1.

[0062] Within a granularity adjustment period, the sum of the historical prefetch hits for each prefetch address is determined as the total prefetch hit count. The total prefetch hit count is used to characterize the total efficiency gain brought by the prefetch operation within a granularity adjustment period.

[0063] Step 602: If the total number of prefetch hits is greater than the first preset threshold, the preset prefetch granularity is determined as the first granularity.

[0064] In this embodiment of the invention, when the total number of prefetch hits exceeds a first preset threshold, it indicates that prefetching can bring certain benefits, and the preset prefetch granularity can be determined as the first granularity. The first preset threshold can be determined based on the number of items in the missing queue (missQueue.num), for example, it can be 1 / 2 * missQueue.num. The first granularity can be set according to actual needs, for example, it can be 256 bytes. For example, if the total number of prefetch hits is greater than 1 / 2 * missQueue.num, it means that within this granularity adjustment period, half of the missing data addresses in the first cache have hit the prefetch address. The data retrieval process for this half may all be due to the prefetch mechanism, allowing direct retrieval in the second cache, improving data retrieval efficiency. Therefore, this indicates that prefetching brings certain benefits, and thus the preset prefetch granularity can be set to a larger granularity.

[0065] Step 603: If the total number of prefetch hits is less than or equal to the first preset threshold and greater than the second preset threshold, the preset prefetch granularity is determined as the second granularity.

[0066] In this embodiment of the invention, if the total number of prefetch hits is less than or equal to a first preset threshold and greater than a second preset threshold, it indicates that prefetching may yield a small benefit, and the preset prefetch granularity can be determined as the second granularity. The second preset threshold can also be determined based on the number of items in the missing queue (missQueue.num), for example, it can be 1 / 4 * missQueue.num. The second granularity can be set according to actual needs, for example, it can be 128 bytes.

[0067] Step 604: If the total number of prefetch hits is less than the second preset threshold, the preset prefetch granularity is determined as the third granularity; the first granularity is greater than the second granularity, and the second granularity is greater than the third granularity.

[0068] In this embodiment of the invention, when the total number of prefetch hits is less than a second preset threshold, it indicates that prefetching has no benefit or minimal benefit, and the preset prefetch granularity is determined as a third granularity. The third granularity can be set according to actual needs, for example, it can be 0 bytes.

[0069] In this embodiment of the invention, the prefetch granularity is dynamically determined by comparing the total number of prefetch hits under the statistical granularity adjustment period with a preset threshold. This enables the large granularity to fully acquire data in high-hit scenarios, thereby improving efficiency; and the small granularity to reduce invalid transmissions in low-hit scenarios, thereby avoiding bandwidth waste and effectively balancing bandwidth usage and prefetch hit rate.

[0070] Optionally, embodiments of the present invention may further include the following steps: Step 701: When the preset prefetch granularity is the third granularity, configure the routing control information of the data prefetch request generated by the first cache corresponding to the next granularity adjustment period as the first routing control information; the first routing control information is used to indicate that the data prefetch request sent by the first cache is temporarily intercepted by the sandbox.

[0071] In this embodiment of the invention, when the preset prefetch granularity is the third granularity, the actual prefetch operation can be disabled, but the sandbox prefetch operation can still be maintained so that the prefetch operation can be re-enabled if the prefetch effect is good. That is, when the preset prefetch granularity is the third granularity, the routing control information of the data prefetch request generated by the first cache corresponding to the next granularity adjustment cycle can be configured as the first routing control information. The first routing control information is used to instruct the sandbox to temporarily intercept the data prefetch request sent by the first cache, instead of sending it to the second cache. For example, when changing the on / off state of the actual prefetch operation, a signal can be added to the data prefetch request generated by the first cache to change the routing control information.

[0072] Step 702: When the routing control information is the first routing control information, and the number of matches between the data retrieval request with missing data and the data prefetch request intercepted by the sandbox is greater than a preset matching threshold, the routing control information corresponding to the next granularity adjustment cycle is configured as the second routing control information; the second routing control information is used to instruct that the data prefetch request generated by the first cache be sent to the sandbox and the second cache.

[0073] In this embodiment of the invention, when the routing control information is the first routing control information, i.e., the actual prefetch operation is disabled, the second cache does not receive data prefetch requests, but the sandbox still collects data prefetch requests. The sandbox counts the data prefetch requests. If the number of matches between the data prefetch requests intercepted by the sandbox and the data retrieval requests corresponding to missing data in the first cache is greater than a preset matching threshold, it indicates that if the actual prefetch operation is enabled in this granularity adjustment period, the prefetching effect is good, and the actual prefetch operation can be enabled in the next granularity adjustment period, i.e., the routing control information is configured as the second routing control information. The second routing control information is used to instruct that the data prefetch requests generated by the first cache be sent to both the sandbox and the second cache simultaneously.

[0074] In this embodiment of the invention, by dynamically adjusting the routing control information according to the granularity adjustment cycle, the actual prefetching operation can be dynamically allocated, which can ensure prediction accuracy and take into account response speed to a certain extent.

[0075] For example, Figure 6A schematic diagram of a dynamic prefetch granularity adjustment strategy is shown, such as... Figure 6 As shown, the demand miss request (DMR) in L2 is matched with the prefetch address recorded in the sandbox. If the hash values ​​of the addresses are the same, it indicates a hit, and the historical prefetch hit count (cnt) corresponding to that address is incremented. If the first cache sends a data prefetch request to the second cache, the prefetch address corresponding to the data prefetch request is added as a new item to the table, and the validity (valid) and historical prefetch hit count (cnt) of the prefetch address are recorded.

[0076] Figure 7 This is a schematic diagram of the structure of a data acquisition device provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the device may specifically include: The first sending module 801 is used to send a data retrieval request corresponding to the target data from the first cache to the second cache when the first cache does not contain the target data; the cache level of the first cache is higher than the cache level of the second cache. The first acquisition module 802 is used to acquire target neighbor data based on the target data address indicated by the data acquisition request and a preset prefetching granularity if the difference between the current time and the sending time of the data acquisition request is greater than the average access delay. The first cache module 803 is used to cache the target proximity data to the second cache.

[0077] This invention provides a data acquisition device. When a first cache does not contain target data, the first cache sends a data acquisition request corresponding to the target data to a second cache. The first cache has a higher cache level than the second cache. If the difference between the current time and the time the data acquisition request was sent is greater than the average access latency, then target neighboring data is acquired based on the target data address indicated by the data acquisition request and a preset prefetch granularity. This target neighboring data is then cached in the second cache. In this way, the difference between the current time and the time the data acquisition request was sent can predict whether the target data indicated by the data acquisition request is missing in the second cache. Without explicitly stating whether the target data is missing in the second cache, if the difference is greater than the average access latency, the target neighboring data is directly prefetched, advancing the prefetching timing and avoiding the extra waiting time caused by waiting to confirm missing data in the second cache, effectively reducing data access latency. Simultaneously, early prefetching can satisfy subsequent data requests faster, reducing performance loss caused by cache misses, enabling the system to process data access tasks more efficiently, and significantly improving overall performance.

[0078] Optionally, the first acquisition module 802 includes: The first acquisition submodule is used to acquire the data acquisition status corresponding to the target data; The first determining module is used to determine the prefetch address based on the target data address indicated by the data acquisition request and the preset prefetch granularity when the data acquisition status is missing and the difference between the current time and the sending time of the data acquisition request is greater than the average access delay. The first sending submodule is used to send a prefetch request to the second cache based on the prefetch address in order to obtain the target neighbor data corresponding to the prefetch address.

[0079] Optionally, the device further includes: The first update module is used to update the missing clock value corresponding to the data acquisition request of the data prefetcher in the first cache to the current time; The first setting module is used to set the data acquisition status corresponding to the data acquisition request to a missing status.

[0080] Optionally, the device further includes: The second setting module is used to set the data acquisition status corresponding to the target data to a filling state when the first cache receives the target data. The second update module is used to update the average access delay based on the first access delay corresponding to the target data; the first access delay is used to characterize the time interval from the first time when the first cache sends a data retrieval request to the second cache to the second time when the first cache receives the target data.

[0081] Optionally, the second update module includes: The first update submodule is used to update the average access delay to a moving average of the first access delay and the average access delay when the absolute value of the difference between the first access delay and the average access delay is less than a preset difference. The second update submodule is used to update the average access delay to the first access delay when the average access delay is greater than the first access delay and the difference between the average access delay and the first access delay is greater than or equal to the preset difference.

[0082] Optionally, the device further includes: The second acquisition module is used to acquire, for any granularity adjustment period, the number of times the data acquisition request corresponding to the first cache with missing data and the data prefetch request sent from the first cache to the second cache match, as the total number of prefetch hits; The second determining module is used to determine the preset prefetch granularity as the first granularity when the total number of prefetch hits is greater than the first preset threshold. The third determining module is used to determine the preset prefetch granularity as the second granularity when the total number of prefetch hits is less than or equal to the first preset threshold and greater than the second preset threshold. The fourth determining module is used to determine the preset prefetch granularity as a third granularity when the total number of prefetch hits is less than the second preset threshold; the first granularity is greater than the second granularity, and the second granularity is greater than the third granularity.

[0083] Optionally, the device further includes: The first configuration module is configured to configure the routing control information of the data prefetch request generated by the first cache in the next granularity adjustment period as the first routing control information when the preset prefetch granularity is the third granularity; the first routing control information is used to indicate that the data prefetch request sent by the first cache is temporarily intercepted by the sandbox. The second configuration module is used to configure the routing control information corresponding to the next granularity adjustment cycle as the second routing control information when the routing control information is the first routing control information and the number of matches between the data retrieval request with missing data and the data prefetch request intercepted by the sandbox is greater than a preset matching threshold. The second routing control information is used to instruct the data prefetch request generated by the first cache to be sent to the sandbox and the second cache.

[0084] The present invention also provides an electronic device, see [link to relevant documentation]. Figure 8 It includes: a processor 901, a memory 902, and a computer program 9021 stored in the memory and executable on the processor. When the processor executes the program, it implements the data acquisition method of the foregoing embodiments.

[0085] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the data acquisition method of the foregoing embodiments.

[0086] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0087] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0088] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0089] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0090] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0091] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0092] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0093] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0094] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0095] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A data acquisition method, characterized in that, The method includes: If the first cache does not contain the target data, the first cache sends a data retrieval request to the second cache to obtain the target data; the cache level of the first cache is higher than that of the second cache. If the difference between the current time and the time when the data acquisition request was sent is greater than the average access latency, then based on the target data address indicated by the data acquisition request and the preset prefetch granularity, the target's neighboring data is prefetched in advance; the difference between the current time and the time when the data acquisition request was sent is used to predict whether the target data is missing in the second cache, and the average access latency is determined based on the historical latency of historical data acquisition requests sent from the first cache to the second cache; The target proximity data is cached in the second cache.

2. The method according to claim 1, characterized in that, If the difference between the current time and the sending time of the data acquisition request is greater than the average access latency, then based on the target data address indicated by the data acquisition request and the preset prefetch granularity, target neighboring data is acquired, including: Obtain the data acquisition status corresponding to the target data; If the data acquisition status is missing, and the difference between the current time and the time when the data acquisition request was sent is greater than the average access delay, then the prefetch address is determined based on the target data address indicated by the data acquisition request and the preset prefetch granularity. A prefetch request is sent to the second cache based on the prefetch address to obtain the target neighbor data corresponding to the prefetch address.

3. The method according to claim 1, characterized in that, After the first cache sends a data retrieval request corresponding to the target data to the second cache, the method further includes: Update the missing clock value corresponding to the data acquisition request in the first cache data prefetcher to the current time; Set the data acquisition status corresponding to the data acquisition request to a missing status.

4. The method according to claim 1, characterized in that, The method further includes: When the first cache receives the target data, the data acquisition status corresponding to the target data is set to the fill status; The average access latency is updated based on the first access latency corresponding to the target data; the first access latency is used to characterize the time interval from the first time when the first cache sends a data retrieval request to the second cache to the second time when the first cache receives the target data.

5. The method according to claim 4, characterized in that, The step of updating the average access latency based on the first access latency corresponding to the target data includes: If the absolute value of the difference between the first access delay and the average access delay is less than a preset difference, the average access delay is updated to a moving average of the first access delay and the average access delay. If the average access latency is greater than the first access latency and the difference between the average access latency and the first access latency is greater than or equal to the preset difference, the average access latency is updated to the first access latency.

6. The method according to claim 1, characterized in that, The method further includes: For any granularity adjustment period, the number of times the data retrieval request corresponding to the first cache with missing data and the data prefetch request sent from the first cache to the second cache are matched is taken as the total number of prefetch hits; If the total number of prefetch hits is greater than a first preset threshold, the preset prefetch granularity is determined as the first granularity; If the total number of prefetch hits is less than or equal to the first preset threshold and greater than the second preset threshold, the preset prefetch granularity is determined as the second granularity. If the total number of prefetch hits is less than the second preset threshold, the preset prefetch granularity is determined as the third granularity; the first granularity is greater than the second granularity, and the second granularity is greater than the third granularity.

7. The method according to claim 6, characterized in that, The method further includes: When the preset prefetch granularity is the third granularity, the routing control information of the data prefetch request generated by the first cache corresponding to the next granularity adjustment period is configured as the first routing control information; the first routing control information is used to indicate that the data prefetch request sent by the first cache is temporarily intercepted by the sandbox; When the routing control information is the first routing control information, and the number of matches between the data retrieval request with missing data and the data prefetch request intercepted by the sandbox is greater than a preset matching threshold, the routing control information corresponding to the next granularity adjustment cycle is configured as the second routing control information; the second routing control information is used to instruct that the data prefetch request generated by the first cache be sent to the sandbox and the second cache.

8. A data acquisition device, characterized in that, The device includes: A first sending module is configured to send a data retrieval request for retrieving the target data from the first cache to the second cache when the first cache does not contain the target data; the cache level of the first cache is higher than that of the second cache. The first acquisition module is used to prefetch target neighboring data in advance based on the target data address indicated by the data acquisition request and a preset prefetch granularity if the difference between the current time and the sending time of the data acquisition request is greater than the average access latency; the difference between the current time and the sending time of the data acquisition request is used to predict whether the target data is missing in the second cache; the average access latency is determined based on the historical latency of historical data acquisition requests sent from the first cache to the second cache. The first caching module is used to cache the target proximity data to the second cache.

9. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the data acquisition method as described in any one of claims 1-7.

10. A readable storage medium, characterized in that, When the instructions in the readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the data acquisition method according to any one of claims 1-7.

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