Pulse neuron circuit with temperature stability and regulation method thereof

Abstract

The application discloses a kind of pulse neuron circuit with temperature stability and its regulation method, it is related to semiconductor technical field.The pulse neuron circuit includes: the drain electrode of ferroelectric transistor FeFET is connected with power supply, source electrode is connected with the drain electrode of MOSFET device;The source electrode of MOSFET device is grounded;One end of capacitor C is connected with the source electrode of ferroelectric transistor FeFET and the drain electrode of MOSFET device respectively, and the other end is grounded.The method includes: introducing carrier mobility temperature empirical model and threshold voltage empirical model into pre-constructed regulation model;By adjusting FeFET gate voltage and MOSFET gate voltage, realize individual control pulse neuron circuit and firing frequency.The application introduces carrier mobility temperature empirical model and threshold voltage empirical model, ensures the functional stability of entire pulse neuron circuit in certain temperature range.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a temperature-stable spiking neuron circuit and its control method. Background Technology

[0002] With the rapid development of artificial intelligence, the Internet of Things, and edge computing, the demand for low-power, high-efficiency computing architectures is becoming increasingly urgent. Traditional von Neumann architectures, due to their separation of memory and computation and energy efficiency bottlenecks, struggle to meet the demands of real-time data processing and intelligent inference. Neuromorphic computing, drawing inspiration from the structure and working principles of biological nervous systems, employs parallel, event-driven computation methods, exhibiting extremely high energy efficiency and real-time processing capabilities, thus becoming one of the important computing paradigms in the post-Moore's Law era.

[0003] Spiking Neural Networks (SNNs), as third-generation neural networks, more closely resemble the information processing mechanisms of biological nervous systems. Employing pulse-based temporal coding and dynamic synaptic plasticity, they are particularly suitable for processing spatiotemporal information and unsupervised learning tasks. The core unit of a hardware-implemented SNN is the neuron circuit, whose performance directly affects the energy efficiency, area, and functional accuracy of the entire network. Currently, most widely studied neuron circuits are based on the Leaky Integrate-and-Fire (LIF) model. This model has a simple structure and is easy to implement using CMOS circuits. However, such models have significant limitations. Most LIF neurons can only realize excitatory dynamics and cannot simulate the excitation-inhibition balance that is prevalent in biological neurons, which is the foundation for stable computation and sparse coding in cortical networks. Furthermore, LIF neurons require an external reset circuit after firing a pulse, increasing area and power consumption. Moreover, LIF neurons cannot simulate complex neural dynamics such as bursts and tremors, limiting their application in simulating reliable biological networks.

[0004] In recent years, ferroelectric field-effect transistors (FeFETs) have been introduced into the field of neuromorphic computing due to their non-volatility, low power consumption, CMOS compatibility, and steep subthreshold swing. Ferroelectric neuron circuit models can simulate the dynamics of Izhikevich neurons, achieving dual-mode control of excitation and inhibition. However, while this model can achieve excitation / inhibition switching, it lacks a systematic optimization method for frequency, amplitude, and temperature stability. Summary of the Invention

[0005] The purpose of this invention is to provide a temperature-stable pulsating neuron circuit and its control method, aiming to solve or improve at least one of the above-mentioned technical problems.

[0006] To achieve the above objectives, the present invention provides the following solution: A temperature-stable spiking neuron circuit, comprising: The drain of the ferroelectric transistor (FeFET) is connected to the power supply, and the source is connected to the drain of the MOSFET device; the source of the MOSFET device is grounded. One end of capacitor C is connected to the source of the ferroelectric transistor FeFET and the drain of the MOSFET device, respectively, and the other end is grounded.

[0007] Furthermore, the ferroelectric layer in the ferroelectric transistor FeFET is either Zr-doped HfO2 or Si-doped HfO2.

[0008] Furthermore, the thickness is 10 nm when Zr is doped with HfO2, and 15 nm when Si is doped with HfO2.

[0009] A modulation method applied to the above-mentioned spiking neuron circuit includes: The empirical models of carrier mobility temperature and threshold voltage are introduced into the pre-constructed regulation model; By adjusting the gate voltage of the FeFET and the gate voltage of the MOSFET, the spiking neuron circuit and firing frequency can be controlled individually.

[0010] Furthermore, empirical models for carrier mobility at temperature include: Carrier mobility, expressed as: ; In the formula, The carrier mobility; This is the current operating temperature; For reference temperature; The mobility temperature index reflects the dominant role of phonon scattering in carrier mobility. As temperature increases, lattice vibrations intensify, scattering is enhanced, and mobility decreases.

[0011] Furthermore, the threshold voltage empirical model includes: Threshold voltage, expressed as: ; In the formula, Threshold voltage; This is the current operating temperature; For reference temperature; This is the temperature coefficient of the threshold voltage. For MOSFETs, as temperature increases, the absolute value of the threshold voltage decreases.

[0012] Furthermore, the process of constructing the regulation model includes: The current equation across capacitor C is the starting point of the control model, and its expression is: ; In the formula, The voltage across capacitor C is denoted by ; C is the film capacitance. and These are the drain currents of the ferroelectric transistor FeFET and the MOSFET, respectively. The drain current of FeFET and MOSFET is expressed as follows: ; ; In the formula, and , respectively, represent the transconductance of the FeFET and MOSFET; s is the switching state variable; and These are the gate voltages of the FeFET and MOSFET, respectively; and These are the threshold voltages of FeFET and MOSFET, respectively; The expressions for the transconductance of FeFET and MOSFET are: ; ; In the formula, The aspect ratio of the FeFET channel; The aspect ratio of the MOSFET channel; and The carrier mobility is denoted as FeFET and MOSFET, respectively. and These are the gate oxide capacitances per unit area for FeFET and MOSFET, respectively. Based on the expressions for the transconductance of FeFET and MOSFET, a constant is introduced. K M and K F The expression is: ; ; The expression for the current is obtained as follows: ; ; ; Furthermore, by adjusting the FeFET gate voltage and MOSFET gate voltage, the spiking neuron circuit and firing frequency can be individually controlled, including: The charging time of the capacitor in the spiking neuron circuit is obtained based on the switching state of the FeFET. T onand discharge time T off ; Based on the charging and discharging times, the complete time-domain expression for the capacitor voltage and the frequency of the spiking neuron circuit are obtained. f , T = T on + T off ,frequency f =1 / T .

[0013] Furthermore, the charging time of the capacitor in the spiking neuron circuit is obtained based on the switching state of the FeFET. T on and discharge time T off ,include: Charging phase: The FeFET is turned on, capacitor C is charged, and... I DM and I DF Substituting the expression into the current equation of capacitor C, we can obtain the charging start time. t I and charging deadline t H Then the charging time T on = t H - t I Charging start time t I and charging deadline t H The expression is: ; ; ; In the formula, α This refers to the ratio of current drive capability. V X1 High threshold voltage; V X2 Low threshold voltage; Discharge phase: FeFET is off, only the drain current of the MOSFET is present. I DM Discharging capacitor C will I DM Substituting the expression into the current equation of capacitor C, the discharge time can be obtained. T off : .

[0014] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects: This invention discloses a temperature-stable spiking neuron circuit and its control method. The method introduces an empirical model of carrier mobility temperature and an empirical model of threshold voltage. Temperature-induced changes in the underlying circuit parameters are absorbed by the dynamic characteristics of the spiking neuron circuit, ensuring the functional stability of the entire spiking neuron circuit within a certain temperature range. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the spiking neuron circuit structure of the present invention; Figure 2 This is a schematic diagram of the ferroelectric transistor FeFET in this embodiment; Figure 3 This is a schematic diagram of the working process of the spiking neuron circuit in this embodiment; Figure 4 This is a temperature simulation diagram of the spiking neuron circuit in this embodiment; the two sub-figures in the first row show the gate voltage V of the ferroelectric transistor FeFET in the cases of Zr-doped HfO2 (HZO) and Si-doped HfO2 (HSO). GF and the gate voltage V of the MOSFET device GM The diagram illustrates the changes; the second to fifth subplots show the capacitor charging and discharging waveforms at different temperatures within the 300K to 330K temperature range. V S A schematic diagram of Spikes variation in digital pulse sequences; Figure 5 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The purpose of this invention is to provide a temperature-stable pulsating neuron circuit and its control method, aiming to solve or improve at least one of the above-mentioned technical problems.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Glossary TCAD (Technology Computer Aided Design) refers to semiconductor process simulation and device simulation tools.

[0021] like Figure 1 As shown, the present invention provides a temperature-stable pulse neuron circuit, comprising: The drain of the ferroelectric transistor (FeFET) is connected to the power supply, and the source is connected to the drain of the MOSFET device; the source of the MOSFET device is grounded. One end of capacitor C is connected to the source of the ferroelectric transistor FeFET and the drain of the MOSFET device, respectively, and the other end is grounded.

[0022] Appendix Figure 1 middle, V DD For power supply; I DF and I DM This refers to the drain current of ferroelectric transistors (FeFETs) and MOSFETs. V GF This is the gate voltage of the ferroelectric transistor FeFET; V GM C is the gate voltage of the MOSFET device; C is the capacitance. V S Let be the voltage across capacitor C.

[0023] like Figure 2 As shown, the structure of a ferroelectric transistor (FeFET) includes: a substrate, a buried oxide layer, a source, a channel, a drain, a gate oxide layer, a metal layer, a ferroelectric layer, and a metal gate. A buried oxide layer is disposed on the substrate; the source, channel, and drain are disposed on the buried oxide layer, with the channel located between the source and drain; a gate oxide layer, a metal layer, a ferroelectric layer, and a metal gate are stacked sequentially and disposed on the channel; The ferroelectric layer is made of HfO2 doped material, preferably Zr-doped HfO2 (HZO) and Si-doped HfO2 (HSO). The thickness is preferably 10 nm when Zr-doped HfO2 is used and 15 nm when Si-doped HfO2 is used. The thickness is optimized by TCAD simulation to obtain a suitable coercive voltage while ensuring ferroelectricity.

[0024] The aforementioned spiking neuron circuit utilizes the gate voltage of the ferroelectric transistor FeFET. V GF Controls the excitation of neurons (low gate voltage) V GF ) and suppression (high gate voltage) V GF ), its ferroelectric capacitance ( C FE This is the key factor that causes lag.

[0025] Gate voltage of MOSFET devices V GM It can be used to adjust the oscillation frequency, that is, the firing frequency of neurons.

[0026] Capacitance C represents the membrane capacitance of the neuron, and voltage... V S Simulates changes in membrane potential. The charging and discharging process of capacitor C directly corresponds to the integration (charging) and reset (discharging) phases of the neuron.

[0027] The pulse neuron circuit of the present invention is based on a ferroelectric relaxation oscillator with a 2T structure, which eliminates the need for a complex reset circuit.

[0028] like Figure 3 The diagram shown illustrates the workflow of a spiking neuron circuit; in the diagram, t I This refers to the charging start time; t H This is the charging deadline. t L This is the charging start time for the next work cycle; V X1 High threshold voltage; V X2 It is a low threshold voltage.

[0029] A method for controlling a temperature-stable spiking neuron circuit, comprising: Pre-built regulatory models, including: The current equation across capacitor C is the starting point of the control model, and its expression is: ; In the formula, The voltage across capacitor C is denoted by ; C is the film capacitance. and These are the drain currents of the ferroelectric transistor FeFET and the MOSFET, respectively. The drain current of FeFET and MOSFET is expressed as follows: ; ; In the formula, and , respectively, represent the transconductance of the FeFET and MOSFET; s is the switching state variable; and These are the gate voltages of the FeFET and MOSFET, respectively; and These are the threshold voltages of FeFET and MOSFET, respectively; The expressions for the transconductance of FeFET and MOSFET are: ; ; In the formula, The aspect ratio of the FeFET channel; The aspect ratio of the MOSFET channel; and The carrier mobility is denoted as FeFET and MOSFET, respectively. and These are the gate oxide capacitances per unit area for FeFET and MOSFET, respectively. Based on the expressions for the transconductance of FeFET and MOSFET, a constant is introduced. K M and K F The expression is: ; ; The expression for the current is obtained as follows: ; ; ; Step 1 involves incorporating the empirical models of carrier mobility temperature and threshold voltage into the pre-built control model, including: Carrier mobility, expressed as: ; In the formula, The carrier mobility; This is the current operating temperature; For reference temperature; The mobility temperature index reflects the dominant role of phonon scattering in carrier mobility. As temperature increases, lattice vibrations intensify, scattering is enhanced, and mobility decreases.

[0030] Threshold voltage, expressed as: ; In the formula, Threshold voltage; This is the temperature coefficient of the threshold voltage. For MOSFETs, as temperature increases, the absolute value of the threshold voltage decreases.

[0031] In this embodiment, k 1 = 1.2; k 2 = 0.5 mV / K; T R =300K.

[0032] Step 2, by adjusting the FeFET gate voltage and MOSFET gate voltage, individually control the spiking neuron circuit and firing frequency, including the following steps: Step 21: Obtain the charging and discharging times of the capacitor in the spiking neuron circuit based on the switching state of the FeFET, including: Charging phase: The FeFET is turned on, capacitor C is charged, and... I DM and I DF Substituting the expression into the current equation of capacitor C, we can obtain the charging start time. t I and charging deadline t H Then the charging time T on = t H - t I Charging start time t I and charging cutoff time t H The calculation formula is: ; ; In the formula, α The expression is: ; Discharge phase: FeFET is off, only the drain current of the MOSFET is present. I DM Discharging capacitor C will I DMSubstituting the expression into the current equation of capacitor C, the discharge time can be obtained. T off : .

[0033] Step 22: Based on the charging and discharging times, obtain the complete time-domain expression for the capacitor voltage and the frequency of the spiking neuron circuit. f , T = T on + T off ,frequency f =1 / T .

[0034] The specific simulation and verification steps are shown below: TCAD Simulation Calibration: First, the electrical characteristics of the 28 nm FDSOI MOSFET were simulated using the Sentaurus TCAD tool and calibrated against industry standard data to ensure the accuracy of the device's basic model.

[0035] Ferroelectric model verification: The Landau-Khalatnikov (LK) equations were used to model and verify the polarization-electric field (PE) hysteresis loop of the ferroelectric capacitor to ensure accurate reproduction of the ferroelectric properties.

[0036] Compact Model Simulation: By substituting the calibrated MOSFET parameters and LK model parameters into the self-developed stable compact model, the capacitor charging and discharging waveforms of the FeFET relaxation oscillator were obtained through simulation. V S and output pulse.

[0037] Temperature dependence analysis: The temperature parameter was activated in the compact model, and a sweep simulation was performed in the range of 300K to 330K to observe the capacitor charging and discharging waveforms. V S The amplitude, frequency, and final output pulse changes.

[0038] like Figure 4 The figure shows the capacitor charging and discharging waveforms obtained from a scanning simulation of a spiking neuron circuit within a temperature range of 300K to 330K. V S And digital pulse sequences Spikes.

[0039] Depend on Figure 4It was found that temperature changes cause slight variations in the amplitude and frequency of the ferroelectric relaxation oscillator, but the oscillation behavior itself remains stable. In simulating an RS neuron, the spike neuron circuit of this invention, despite changes in ambient temperature, does not exhibit significant changes in the timing and morphology of its final output digital spike sequence, Spikes.

[0040] This invention relates to the transconductance of FeFETs and MOSFETs based on expressions for device parameters. g F , g M The system is refined, and empirical models of carrier mobility temperature and threshold voltage are introduced into the control model. Temperature-induced changes in the underlying circuit parameters are absorbed by the dynamic characteristics of the spiking neuron circuit, ensuring the functional stability of the entire spiking neuron circuit within a certain temperature range.

[0041] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0042] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for controlling a temperature-stable spiking neuron circuit, characterized in that, include: The circuit includes a ferroelectric transistor (FeFET) whose drain is connected to a power supply and whose source is connected to the drain of a MOSFET device; the source of the MOSFET device is grounded. One end of capacitor C is connected to the source of the ferroelectric transistor FeFET and the drain of the MOSFET device, respectively, and the other end is grounded; The construction process of the modulation model of the spiking neuron circuit includes: The current equation across capacitor C is the starting point of the control model, and its expression is: ； In the formula, The voltage across capacitor C is denoted by ; C is the film capacitance. and These are the drain currents of the ferroelectric transistor FeFET and the MOSFET, respectively. The drain current of FeFET and MOSFET is expressed as follows: ； ； In the formula, and , respectively, represent the transconductance of the FeFET and MOSFET; s is the switching state variable; and These are the gate voltages of the FeFET and MOSFET, respectively; and These are the threshold voltages of FeFET and MOSFET, respectively; The expressions for the transconductance of FeFET and MOSFET are: ； ； In the formula, The aspect ratio of the FeFET channel; The aspect ratio of the MOSFET channel; and The carrier mobility is denoted as FeFET and MOSFET, respectively. and These are the gate oxide capacitances per unit area for FeFET and MOSFET, respectively. Based on the expressions for the transconductance of FeFET and MOSFET, a constant is introduced. K M and K F The expression is: ； ； The expression for the current is obtained as follows: ； ； The empirical models of carrier mobility temperature and threshold voltage are introduced into the pre-constructed regulation model; By adjusting the gate voltage of the FeFET and the gate voltage of the MOSFET, the spiking neuron circuit and its firing frequency can be controlled individually, including: The charging time of the capacitor in the spiking neuron circuit is obtained based on the switching state of the FeFET. T on and discharge time T off ; Based on the charging and discharging times, the complete time-domain expression for the capacitor voltage and the frequency of the spiking neuron circuit are obtained. f , T = T on + T off ,frequency f =1 / T ; Charging phase: The FeFET is turned on, capacitor C is charged, and... I DM and I DF Substituting the expression into the current equation of capacitor C, we can obtain the charging start time. t I and charging deadline t H Then the charging time T on = t H - t I ; Discharge phase: FeFET is off, only the drain current of the MOSFET is present. I DM Discharging capacitor C will I DM Substituting the expression into the current equation of capacitor C, the discharge time can be obtained. T off .

2. The method for controlling a temperature-stable spiking neuron circuit according to claim 1, characterized in that, include: The ferroelectric layer in the FeFET ferroelectric transistor is either Zr-doped HfO2 or Si-doped HfO2.

3. The method for controlling a temperature-stable spiking neuron circuit according to claim 2, characterized in that, The thickness of HfO2 doped with Zr is 10 nm; the thickness of HfO2 doped with Si is 15 nm.

4. The method for controlling a temperature-stable spiking neuron circuit according to claim 1, characterized in that, Empirical models of carrier mobility temperature include: Carrier mobility, expressed as: ； In the formula, The carrier mobility; This is the current operating temperature; For reference temperature; The mobility temperature index reflects the dominant role of phonon scattering in carrier mobility. As temperature increases, lattice vibrations intensify, scattering is enhanced, and mobility decreases.

5. The method for controlling a temperature-stable spiking neuron circuit according to claim 1, characterized in that, Threshold voltage empirical models include: Threshold voltage, expressed as: ； In the formula, Threshold voltage; This is the current operating temperature; For reference temperature; This is the temperature coefficient of the threshold voltage. For MOSFETs, as temperature increases, the absolute value of the threshold voltage decreases.

6. The method for controlling a temperature-stable spiking neuron circuit according to claim 1, characterized in that, The charging time T on and discharge time T off ,include: Charging start time t I and charging deadline t H The expression is: ； ； ； In the formula, α is the current drive capability ratio; V X1 High threshold voltage; V X2 Low threshold voltage; Discharge time T off : 。

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