Driving method of display device and display device

Abstract

The application discloses a display device driving method and a display device. The display device comprises a controller and a level shift chip, and the controller and the level shift chip are electrically connected. The controller comprises a receiving port, and the level shift chip comprises a fast discharge mode and a shutdown state bit. When the receiving port of the controller receives a first rising edge of a port signal of the receiving port, the controller sends a first signal to the level shift chip, so that the level shift chip forcibly clears the shutdown state bit. When the receiving port of the controller receives a first falling edge of the port signal, the controller sends a second signal to the level shift chip, so that the level shift chip forcibly enters the fast discharge mode. The application improves the problem of power-down residual image of the display.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a driving method for a display device and a display device. Background Technology

[0002] Currently, in the display panel industry, charging the liquid crystal of the display panel causes it to flip, allowing light to pass through and display images. In discharge mode, when the voltage of the display panel's level shift chip decreases to a certain level, all the thin-film field-effect transistors (TFTs) of the display panel are activated, rapidly discharging the charge in their liquid crystal capacitors, allowing the liquid crystal to recover quickly. In existing technology, voltage fluctuations or rebounds can cause abnormal discharge of all TFTs, resulting in power-down ghosting in the display. Summary of the Invention

[0003] The purpose of this invention is to provide a driving method and display device for a display device, which improves the problem of power-off ghosting in displays.

[0004] To achieve the objectives of this invention, the following technical solution is provided: In a first aspect, the present invention provides a driving method for a display device, the display device including a controller and a level shifting chip, the controller and the level shifting chip being electrically connected, the controller including a receiving port, and the level shifting chip including a fast discharge mode and a power-off state bit; When the controller's receiving port receives the first rising edge of the port signal of the receiving port, the controller sends a first signal to the level shift chip to force the level shift chip to clear the power-off state bit; When the controller's receiving port receives the first falling edge of the port signal, the controller sends a second signal to the level shift chip to force the level shift chip into the fast discharge mode.

[0005] It is understandable that when the controller's receiving port captures the first rising edge of the port signal, it sends a first signal to forcibly clear the power-off state bit of the level shifter chip. When the controller's receiving port captures the first falling edge, it sends a second signal to force the level shifter chip to enter a fast discharge mode. The first rising edge corresponds to a critical signal node in the initial stage of the display device's startup. Clearing the power-off state bit at this time can completely eliminate residual power-off state interference in the chip, ensuring that the chip responds to subsequent drive commands in its initial normal state and avoiding startup failures. The first falling edge corresponds to the initial stage of signal switching. Forced fast discharge can accelerate the release of excess charge inside the chip, reduce the impact of charge accumulation on signal transmission, improve the accuracy of controlling the level shifter chip, improve the stability of the circuit, reduce circuit noise, speed up the discharge speed during signal switching, and improve the problem of power-off ghosting on the display. In one embodiment, the display device further includes a signal processing circuit, which receives a first voltage and a second voltage, wherein the first voltage is the power supply voltage of the power management chip and the second voltage is a preset voltage; the port signal includes a high-level signal and a low-level signal; when the first voltage is higher than or equal to the second voltage, the port signal output by the signal processing circuit is the high-level signal; when the first voltage is lower than the second voltage, the port signal output by the signal processing circuit is the low-level signal.

[0006] It is understandable that the signal processing circuit compares the first voltage with the second voltage. When the first voltage is higher than or equal to the second voltage, the port signal output by the signal processing circuit is a high-level signal; when the first voltage is lower than the second voltage, the port signal output by the signal processing circuit is a low-level signal. This improves the adaptability and anti-interference capability of the port signal to changes in the power supply voltage, ensures that the signal received by the controller can accurately match the actual state of the power management chip, thereby ensuring the correctness of sending instructions to the level shifting chip, reducing abnormal operation of the display device caused by power supply voltage fluctuations, and enhancing the stability of the driving method. Secondly, this application also provides a display device, including a display panel and a driving circuit, wherein the display panel and the driving circuit are electrically connected, the driving circuit includes the driving method described in the first aspect, the driving circuit further includes the controller, the level shifting chip and / or the signal processing circuit, the controller is electrically connected to the level shifting chip, and / or the controller is electrically connected to the signal processing circuit, the controller includes a receiving port, the level shifting chip includes a fast discharge mode and a power-off state bit, wherein: when the receiving port of the controller receives the first rising edge of the port signal of the receiving port, the controller is configured to send a first signal to the level shifting chip to force the level shifting chip to clear the power-off state bit; when the receiving port of the controller receives the first falling edge of the port signal, the controller is further configured to send a second signal to the level shifting chip to force the level shifting chip to enter the fast discharge mode.

[0007] It is understandable that the above driving method achieves precise control of the level shifter chip, clears the power-off state bit to ensure the chip is in normal condition during startup, and provides a stable initial drive signal for the display panel; the fast discharge mode reduces charge accumulation on the chip, avoids drive signal distortion, and ensures that the signal received by the panel accurately corresponds to the display requirements. At the same time, it improves the overall working stability and display quality of the display device, avoiding problems such as panel startup failure and image ghosting caused by inaccurate control of the drive circuit.

[0008] In one embodiment, the signal processing circuit includes a first comparison module, a first gating module, and a second gating module. The first input terminal of the first comparison module is used to input a first voltage, the second input terminal is used to input a second voltage, the third input terminal is used to input a positive power supply voltage, and the fourth input terminal is used to input a negative power supply voltage. The first output terminal of the first comparison module is connected to the gate of both the first and second gating modules. The drain of the first gating module is used to input a third voltage, and the source of the first gating module is connected to the drain of the second gating module and the receiving port of the controller. The first gating module is turned on when receiving a positive voltage, and the source of the second gating module is used to input a fourth voltage, which is less than the third voltage. The second gating module is turned on when receiving a negative voltage. The first comparison module compares the first voltage and the second voltage. When the first voltage is higher than the second voltage, the first comparison module outputs the positive power supply voltage to the gate of the first gating module; when the first voltage is lower than the second voltage, the first comparison module outputs the negative power supply voltage to the gate of the second gating module.

[0009] It is understandable that the first comparison module compares the first voltage with the second voltage. When the first voltage is higher than the second voltage, it outputs the corresponding positive power supply voltage to activate the first gating module to output the third voltage; when the first voltage is lower than the second voltage, it outputs the negative power supply voltage to activate the second gating module to output the fourth voltage. This simplified comparison and gating structure reduces interference nodes. Moreover, the clear difference between the third and fourth voltages ensures a clear distinction between high and low levels of the port signal, avoiding intermediate ambiguity. This setting improves the accuracy of voltage judgment and the clarity of gating logic, ensuring stable and clearly distinguishable port signals, providing a reliable triggering basis for the controller, reducing drive failures caused by signal processing errors, and enhancing the operational stability of the display device.

[0010] In one embodiment, the first comparison module includes a first comparator, the first gating module includes an N-channel field-effect transistor, the second gating module includes a P-channel field-effect transistor, and the first output terminal of the first comparator is connected to the gate of the N-channel field-effect transistor and the gate of the P-channel field-effect transistor. When the first voltage is higher than the second voltage, the first comparator outputs the positive power supply voltage to the gate of the N-channel field-effect transistor, and the N-channel field-effect transistor is turned on when receiving the positive power supply voltage to output the third voltage to the controller; When the first voltage is lower than the second voltage, the first comparator outputs the negative power supply voltage to the gate of the P-channel field-effect transistor, and the P-channel field-effect transistor is turned on when receiving the negative power supply voltage to output the fourth voltage to the controller.

[0011] It can be understood that when the first voltage is higher than the second voltage, the first comparator outputs a positive power supply voltage to the gate of the N-channel field-effect transistor. The N-channel field-effect transistor is turned on when receiving the positive power supply voltage to output a third voltage to the controller. When the first voltage is lower than the second voltage, the first comparator outputs a negative power supply voltage to the gate of the P-channel field-effect transistor. The P-channel field-effect transistor is turned on when receiving the negative power supply voltage to output a fourth voltage to the controller. This improves the response speed and gating accuracy of the signal processing circuit, avoids threshold drift, and further ensures the stable operation of the display device.

[0012] In one embodiment, the display device further includes a first voltage divider unit and a second voltage divider unit. The first voltage divider unit is connected in series between the first output terminal and the gate of the N-channel field-effect transistor. One end of the second voltage divider unit is connected to both the first output terminal and one end of the first voltage divider unit. The other end of the second voltage divider unit is connected to the gate of the P-channel field-effect transistor.

[0013] It is understandable that the first and second voltage divider units precisely adjust the comparator output voltage to within the safe and effective range of the gate voltage of the N-channel MOSFET or P-channel MOSFET. When the positive power supply voltage is too high, the first voltage divider unit reduces the gate voltage to prevent breakdown; when the absolute value of the negative power supply voltage is too large, the second voltage divider unit adjusts the gate voltage to ensure that the conduction threshold is reached, further stabilizing the gate voltage and effectively protecting the N-channel and P-channel MOSFETs from overvoltage damage, reducing signal transmission loss, and improving the stability of port signals. Simultaneously, the first and second voltage divider units can also filter out some voltage fluctuations, enhance the circuit's anti-interference capability, reduce gating failures caused by voltage anomalies, and further ensure the reliability of the signal processing circuit.

[0014] In one embodiment, the first voltage divider unit includes at least one first resistor; and / or, the second voltage divider unit includes at least one second resistor.

[0015] It is understood that the first voltage divider unit includes at least one first resistor; and / or, the second voltage divider unit includes at least one second resistor, which takes into account both the requirements of circuit simplification and voltage division accuracy. The single resistor scheme can reduce the hardware cost and integration difficulty of the display device, reduce the circuit space occupied, and adapt to the miniaturized display device scenario; the multiple resistor scheme can accurately adjust the voltage division ratio, avoid the abnormal operation of subsequent driving circuits (such as level shifting chips) due to voltage fluctuations, ensure the stability of the voltage signal input to the display panel, and improve the stability of display image quality. In one embodiment, the level shifting chip includes a signal conditioning module and a logic board, the signal conditioning module being electrically connected to the logic board, the level shifting chip including a constant current output mode and a constant voltage output mode, and the logic board being used to output a clock signal; When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is lower than the first preset voltage, the level shifting chip is used to enter the constant current output mode. When the signal conditioning module receives the second rising edge of the clock signal, and the voltage of the clock signal is higher than or equal to the first preset voltage, the level shifting chip is used to enter the constant voltage output mode. When the signal conditioning module receives the second falling edge of the clock signal, and the voltage of the clock signal is higher than or equal to the second preset voltage, the level shifting chip is used to enter the constant current output mode. When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is lower than the second preset voltage, the level shifting chip is used to enter the constant voltage output mode.

[0016] Understandably, this design achieves automatic output mode switching through dual judgment of clock signal edge and voltage threshold. The constant current output mode ensures stable current to the display panel's light-emitting elements, avoiding uneven brightness due to current fluctuations and improving screen brightness consistency. The constant voltage output mode ensures stable voltage in the drive circuit, preventing circuit damage or signal distortion due to abnormal voltage. Simultaneously, the real-time triggering mechanism based on the clock signal enables rapid response to mode switching, adapting to high-frequency refresh rates in display devices, reducing screen ghosting caused by mode switching delays, and improving display smoothness.

[0017] In one embodiment, the signal conditioning module further includes a first conditioning module, a second conditioning module, and a signal output terminal. The gates of the first conditioning module and the second conditioning module are both connected to the logic board. The source of the first conditioning module and the drain of the second conditioning module are both connected to a first port of the level shifting chip. The first port is used to receive the clock signal. The output terminal of the first conditioning module is connected to the output terminal of the second conditioning module and the signal output terminal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is lower than the first preset voltage, the first conditioning module is used to output a constant first conditioning current to the signal output terminal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is higher than or equal to the first preset voltage, the first conditioning module is used to output a constant first conditioning voltage to the signal output terminal. When the signal conditioning module receives the second falling edge of the clock signal, and the voltage of the clock signal is higher than or equal to the second preset voltage, the second conditioning module is used to output a constant second conditioning current; When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is lower than the second preset voltage, the second conditioning module outputs a constant second conditioning voltage.

[0018] Understandably, this design achieves differentiated and precise processing of the rising and falling edges of the clock signal through modular conditioning, improving signal conditioning accuracy and stability. The first conditioning module focuses on the rising edge signal, while the second conditioning module focuses on the falling edge signal. This avoids the conditioning delay or insufficient accuracy problems caused by a single module processing both edges, resulting in smaller errors in the output constant current or voltage. This effectively reduces display panel drive anomalies caused by signal fluctuations and ensures the continuity of the conditioned signal, preventing signal interruptions during module switching and improving the smoothness and clarity of the displayed image. Furthermore, precise constant current or voltage output reduces component losses caused by signal instability, improving the overall reliability of the display device.

[0019] In one embodiment, the first conditioning module includes a first transistor, a second transistor, a third transistor, a first NOT gate, a second comparator, and a third comparator; the second conditioning module includes a fourth transistor, a fifth transistor, a sixth transistor, a second NOT gate, a third NOT gate, a fourth comparator, and a fifth comparator. The logic board is connected to one end of the level shifting chip. The gate of the first transistor and one end of the second NOT gate are connected to the logic board. The other end of the second NOT gate is connected to the gate of the fourth transistor. The source of the first transistor and the drain of the fourth transistor are both connected to the other end of the level shifting chip. The drain of the first transistor is connected to the first sub-input of the second comparator. The source of the fourth transistor is connected to the fifth sub-input of the fourth comparator. The second sub-input of the second comparator is connected to the third sub-input of the third comparator. The output of the second comparator is connected to one end of the first NOT gate and the second transistor. The gate of the transistor is connected, the source of the second transistor is connected to the drain of the third transistor and the display panel, the other end of the first NOT gate is connected to the gate of the third transistor, the source of the third transistor is connected to the output terminal of the third comparator and the fourth sub-input terminal of the third comparator, the sixth sub-input terminal of the fourth comparator is connected to the seventh sub-input terminal of the fifth comparator, the output terminal of the fourth comparator is connected to one end of the third NOT gate and the gate of the fifth transistor, the other end of the third NOT gate is connected to the gate of the sixth transistor, the source of the fifth transistor is connected to the drain of the sixth transistor, the source of the second transistor, the drain of the third transistor and the display panel, the eighth sub-input terminal of the fifth comparator is connected to the output terminal of the fifth comparator and the source of the sixth transistor, the drain of the second transistor is used to input the first operating voltage, and the drain of the fifth transistor is used to input the second operating voltage.

[0020] This design, through a refined combination of components and a feedback calibration mechanism, achieves ultra-high precision conditioning of the clock signal edge. Transistors control the current or voltage output, NOT gates invert logic signals to precisely switch transistor states, and comparators determine voltage thresholds and calibrate the output signal. These three components work together to reduce current or voltage errors after conditioning, effectively avoiding issues such as color deviation and image ghosting on the display panel caused by signal distortion, thus greatly improving the consistency of display quality. Furthermore, the feedback calibration mechanism of the third and fifth comparators can correct output signal deviations in real time, ensuring signal stability and enhancing the display device's anti-interference capabilities. In addition, the independent supply of the first and second operating voltages avoids power supply interference between modules, ensuring the conditioning module's response speed under high-frequency clock signals and adapting to high frame rate display scenarios.

[0021] Implementing the embodiments of this application will have the following beneficial effects: By configuring the controller's receiving port to send a first signal to forcibly clear the power-off state bit of the level shifter chip upon capturing the first rising edge of the port signal, and a second signal to force the level shifter chip to enter a fast discharge mode upon capturing the first falling edge, the controller's receiving port can effectively eliminate residual power-off state interference, preventing the chip from failing to enter other power-off states and avoiding power-down ghosting caused by insufficient fast discharge. The first falling edge forces the level shifter chip into a fast discharge mode, rapidly releasing the charge in the liquid crystal capacitors and quickly restoring the liquid crystal, thus preventing power-down ghosting. This configuration prevents the level shifter chip from remembering the current power-off state bit if it hasn't discharged below a certain voltage, thus preventing power-down ghosting when re-entering the power-off state due to the previous power-off state bit not being cleared. It also avoids the rebound of the power supply voltage, which fails to drop to the potential that can trigger the fast discharge mode, thus improving the power-down ghosting problem of the display device. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is an application scenario diagram of a display device according to one embodiment; Figure 2 This is a schematic diagram of the structure of a display device according to one embodiment; Figure 3 This is a schematic diagram of the partial structural voltage of a display device according to one embodiment; Figure 4 This is a flowchart illustrating a control method for a display device according to one embodiment; Figure 5 This is a schematic diagram of the structure of a display device according to one embodiment; Figure 6 This is a schematic diagram of the structure of a signal conditioning module according to one embodiment; Figure 7 This is a flowchart illustrating a signal conditioning module processing method according to one embodiment; Figure 8This is a schematic diagram of the output current of a signal conditioning module in one embodiment; Figure 9 This is a schematic diagram of the clock signal output voltage of one embodiment; Figure 10 This is a schematic diagram of the voltage commonly used in a display device to enter a fast discharge mode in one embodiment; Figure 11 This is a schematic diagram of the first voltage in the power-down afterimage state of a display device according to one embodiment; Figure 12 This is a schematic diagram of the second voltage in the power-down afterimage state of a display device according to one embodiment.

[0024] Explanation of reference numerals in the attached figures: 101-User, 102-Electronic device, 103-Server, 201-First comparator, 2011-First input, 2012-Second input, 2013-Third input, 2014-Fourth input, 2015-First output, 202-First resistor, 203-Second resistor, 204-N-channel field-effect transistor, 205-P-channel field-effect transistor, 206-Controller, 207-Level shifter chip, 208-Positive power supply voltage, 209-Negative power supply voltage, 301-Signal conditioning module 3011 - First transistor, 3012 - Second transistor, 3013 - Third transistor, 3014 - First NOT gate, 3015 - Second comparator, 3016 - Third comparator, 3017 - Fourth transistor, 3018 - Fifth transistor, 3019 - Sixth transistor, 3020 - Second NOT gate, 3021 - Third NOT gate, 3022 - Fourth comparator, 3023 - Fifth comparator, 303 - Logic board, 304 - Signal output terminal, 500 - Display device, 501 - Processor, 502 - Memory. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the examples described are only a part of the examples of the present application, and not all of them. Based on the examples in the present application, all other examples obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0026] The terms “1” and “2”, etc., in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one example of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] Please see Figure 1 , Figure 1 This is an application scenario diagram of a display device provided in this application. For example... Figure 1 As shown in the diagram, this application scenario includes user 101, electronic device 102, and server 103. It should be noted that electronic device 102 includes a display device, which can display video data or image data. Furthermore, Figure 1 The number of devices, the form of each device, and the number of users in the system shown are for illustrative purposes only and do not constitute a limitation of this application. A user 101 can use multiple electronic devices 102, and a server 103 can be connected to multiple electronic devices 102. The server 103 transmits data to the electronic devices 102, and the electronic devices 102 can display the data on the display.

[0029] User 101 is the user who actually operates electronic device 102 to control it to perform corresponding operations. Electronic device 102 can be... Figure 1 The laptop computer shown can also be a personal computer (PC), all-in-one computer, handheld computer, tablet computer, desktop computer, smartphone, smart TV playback terminal, and portable device, as long as it includes a display device. When the electronic device is a personal computer, it can be an all-in-one computer, etc., and its operating system can include, but is not limited to, Linux, Unix, and Windows series systems (such as Windows XP, Windows 7, etc.). Mobile electronic devices, such as smartphones, can have operating systems including, but not limited to, Android, iOS (Apple's operating system), and Windows.

[0030] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a display device provided in this application. Figure 2 As shown, the display device includes a display panel and a driving circuit, which are electrically connected. The driving circuit includes the driving method described above. The driving circuit also includes a controller 206, a level shifting chip 207 and / or a signal processing circuit, a positive power supply voltage 208, and a negative power supply voltage 209. The controller 206 is electrically connected to the level shifting chip 207, and / or the controller 206 is electrically connected to the signal processing circuit. The controller 206 includes a receiving port, and the level shifting chip 207 includes a fast discharge mode and a power-off state bit. When the controller's receiving port receives the first rising edge of the port signal, the controller sends a first signal to the level shift chip to force the level shift chip to clear the power-off state bit; when the controller's receiving port receives the first falling edge of the port signal, the controller also sends a second signal to the level shift chip to force the level shift chip to enter the fast discharge mode.

[0031] It should be noted that the fast discharge mode is a function of the level shifter chip, which enables rapid discharge of the liquid crystal. Please refer to [link / reference needed]. Figure 10 The specific process is as follows: The operating voltage of the level shifter chip is typically 3.3V (VDD3.3). When VDD3.3 drops to a set voltage (usually 2.7V), the level shifter chip enters a fast discharge mode. In this mode, the level shifter chip pulls all output voltages to a first high voltage (VGH). This first high voltage causes all thin-film transistors to turn on, thus enabling rapid discharge. For example, display devices include power management integrated circuits (ICs). Currently, they often enter fast discharge mode by using a 12V supply voltage (Vin) to power the IC. The IC generates a 3.3V voltage to power the level shifter chip. When the display device is powered off, the 12V supply voltage is turned off. During the drop in the 12V supply voltage, the load capacity of the IC decreases, affecting the voltage generated by the IC. Therefore, the 3.3V voltage output to the level shifter chip will decrease. Figure 10 As shown, the clock signal (CK) stops outputting after Vin is powered off, and enters fast discharge mode when VDD3.3 drops to 2.7V.

[0032] Currently, the following situations can cause power-down ghosting on display devices: user manual power-on / off, automatic power-off or power-on, or repeated power outages and restorations in a short period causing the display to power on and off repeatedly within a short timeframe. The causes of power-down ghosting will be explained below. Please refer to the following sections for details. Figure 11 On the one hand, because the manual power-on and power-off speed is relatively fast, if the first high voltage is not discharged to a certain voltage when the power is off, the level shift chip will remember the power-off state bit at this moment. This will cause the level shift chip to be unable to reset the corresponding power-off state bit when the power is turned on again later. After powering on, when powering off again, the fast discharge mode will not be visible because the previous power-off state bit has not been cleared, and the display device will produce a power-off afterimage.

[0033] On the other hand, please refer to Figure 12 When the display device automatically shuts down or powers on, although the power-on and power-off times are relatively gradual, the supply voltage will rebound multiple times. Because the 12V supply voltage drops to 3.3V, the VDD3.3 voltage will also rebound. The rebounded VDD3.3 does not drop to the set voltage, thus failing to trigger the fast discharge mode. At this time, the clock signal continues to output, and the fast discharge mode is not entered, so the phenomenon of the fast discharge mode is not visible, and the display device produces a power-off afterimage. Specifically, when the display device automatically shuts down or powers on, it cannot directly cut off the power supply as it would with manual power-on or power-off. Instead, it gradually limits the current output until it shuts off. Due to changes in screen load, the screen's supply voltage cannot drop as quickly as it would with manual power-off; the supply voltage will rebound and fluctuate, causing VDD3.3 not to drop to the set voltage and failing to trigger the fast discharge mode.

[0034] For example, the controller only needs to detect when the first rising edge or falling edge of the received signal occurs, and then send a command to the level shifter chip via the integrated circuit bus. When the first rising edge occurs, the controller clears the shutdown state bit stored in the level shifter chip at that time to prevent it from failing to enter other shutdown state bits during power-off. When the first falling edge occurs, the controller forces the level shifter chip into discharge mode.

[0035] It is understandable that by controlling the level shifter chip, the display device can flexibly adapt to different voltage conditions. For example, in different operating modes, the display device may require different voltage levels, and the controller can adjust the state of the level shifter chip as needed to meet these changes. This flexible setting allows the display device to be used more widely in different scenarios and for different needs.

[0036] It is understandable that the controller's precise control of the level shifting chip helps improve the reliability of the display device. By ensuring that the level shifting chip operates under the correct voltage conditions and avoiding unnecessary voltage fluctuations or interference, the display device can operate more stably, which helps reduce the failure rate and improve the overall reliability of the display device.

[0037] It should be noted that when testing the monitor panel using a lamp-lighting fixture, the discharge mode is used to activate all the thin-film transistors on the panel after the 3.3V voltage of the detection level shift chip drops to a certain level, quickly discharging the charge in the liquid crystal capacitors. If the voltage rebounds, it will inevitably affect the 3.3V voltage of the level shift chip, leading to abnormal discharge of the thin-film transistors and causing the monitor to exhibit a power-down image retention problem. Typically, this power-down image retention problem appears on the panel.

[0038] In this embodiment, it can be understood that when the controller's receiving port captures the first rising edge of the port signal, it sends a first signal to forcibly clear the power-off state bit of the level shift chip. When the controller's receiving port captures the first falling edge, it sends a second signal to force the level shift chip to enter a fast discharge mode. The first rising edge corresponds to a critical signal node in the initial stage of the display device's startup. Clearing the power-off state bit stored in the level shift chip at this time can completely eliminate residual power-off state interference from the level shift chip, preventing the device from failing to enter other power-off state bits during shutdown and avoiding power-down ghosting caused by insufficient fast discharge. The first falling edge forces the level shift chip to enter a fast discharge mode, allowing the charge in the liquid crystal capacitor of the display device to be released quickly, enabling the liquid crystal to recover quickly and avoiding power-down ghosting. Through the above settings, it is prevented that if the level shift chip does not discharge to a certain voltage, it will store the power-off state bit at this moment, and when the device is powered on again, the level shift chip will not be able to reset the corresponding power-off state bit, thus preventing power-down ghosting when re-entering the power-off state bit because the previous power-off state bit was not cleared. It also avoids the rebound of the power supply voltage, which fails to drop to the potential that can trigger the fast discharge mode, thus improving the power-down ghosting problem of the display device.

[0039] In one embodiment of this application, the signal processing circuit includes a first comparison module, a first gating module, and a second gating module. The first input terminal of the first comparison module is used to input a first voltage, the second input terminal of the first comparison module is used to input a second voltage, the third input terminal of the first comparison module is used to input a positive power supply voltage, and the fourth input terminal of the first comparison module is used to input a negative power supply voltage. The first output terminal of the first comparison module is connected to the gate of both the first and second gating modules. The drain of the first gating module is used to input a third voltage, and the source of the first gating module is connected to the drain of the second gating module and the receiving port of the controller. The first gating module is turned on when receiving a positive voltage, and the source of the second gating module is used to input a fourth voltage, where the fourth voltage is less than the third voltage. The second gating module is turned on when receiving a negative voltage. The first comparison module compares the magnitudes of the first and second voltages. When the first voltage is higher than the second voltage, the first comparison module controls the first comparison module to output a positive power supply voltage to the gate of the first gating module; when the first voltage is lower than the second voltage, the first comparison module controls the first comparison module to output a negative power supply voltage to the gate of the second gating module.

[0040] Optionally, the positive power supply voltage is greater than zero, and the negative power supply voltage is less than zero. Optionally, the positive power supply voltage is around 5V. Optionally, the negative power supply voltage is ground voltage.

[0041] It is understandable that the first comparison module compares the first voltage with the second voltage. When the first voltage is higher than the second voltage, it outputs the corresponding positive power supply voltage to activate the first gating module to output the third voltage; when the first voltage is lower than the second voltage, it outputs the negative power supply voltage to activate the second gating module to output the fourth voltage. This simplified comparison and gating structure reduces interference nodes. Moreover, the clear difference between the third and fourth voltages ensures a clear distinction between high and low levels of the port signal, avoiding intermediate ambiguity. This setting improves the accuracy of voltage judgment and the clarity of gating logic, ensuring stable and clearly distinguishable port signals, providing a reliable triggering basis for the controller, reducing drive failures caused by signal processing errors, and enhancing the operational stability of the display device.

[0042] In one implementation, please refer to Figure 2The first comparison module includes a first comparator 201, the first gating module includes an N-channel field-effect transistor 204, and the second gating module includes a P-channel field-effect transistor 205. The first output terminal 2015 of the first comparator 201 is connected to the gate of both the N-channel field-effect transistor 204 and the gate of the P-channel field-effect transistor 205. When the first voltage is higher than the second voltage, the first comparator 201 outputs a positive power supply voltage to the gate of the N-channel field-effect transistor 204, and the N-channel field-effect transistor 204 is turned on when receiving the positive power supply voltage to output a third voltage to the controller 206. When the first voltage is lower than the second voltage, the first comparator 201 outputs a negative power supply voltage to the gate of the P-channel field-effect transistor 205, and the P-channel field-effect transistor 205 is turned on when receiving the negative power supply voltage to output a fourth voltage to the controller 206.

[0043] Optionally, the first input terminal 2011 of comparator 201 is used to input a first voltage, the second input terminal 2012 of comparator 201 is used to input a second voltage, the third input terminal 2013 of comparator 201 is used to input a positive power supply voltage, the fourth input terminal 2014 of comparator 201 is used to input a negative power supply voltage, the drain of N-channel field-effect transistor 204 is used to input a third voltage, the source of P-channel field-effect transistor 205 is used to input a fourth voltage, the input terminal of controller 206 is connected to both the source of N-channel field-effect transistor 204 and the drain of P-channel field-effect transistor 205, and the output terminal of controller 206 is connected to the output terminal of level shifting chip 207.

[0044] For example, please refer to Figure 3 , Figure 3 This is a partial voltage diagram of a display device. When the first voltage is 12V and the second voltage is 8V, the first voltage is greater than the second voltage. At this time, the first comparator outputs a positive power supply voltage to the gate of the N-channel field-effect transistor, i.e., a high-level output. When the first voltage drops and becomes lower than 8V, the first comparator will immediately output a negative power supply voltage, i.e., a low-level output.

[0045] For example, the third voltage is 3.3V. When the display is working normally, the first comparator will output a high level, the N-channel MOSFET will be turned on, the P-channel MOSFET will be turned off, and the controller will be continuously input with 3.3V. When the display panel is powered off, the first voltage drops, the N-channel MOSFET is turned off, the P-channel MOSFET is turned on, and the voltage received by the controller will be pulled down instantly.

[0046] It is understandable that the first comparator can quickly compare the magnitudes of the first voltage and the second voltage, and immediately output the corresponding positive or negative power supply voltage, with a fast response speed.

[0047] It is understandable that the first comparator can accurately compare the magnitudes of the first voltage and the second voltage. The first comparator can ensure that the positive or negative power supply voltage is output under the correct conditions, thereby improving the accuracy of the control level shifting chip.

[0048] It is understandable that the first comparator replaces the more complex circuit logic to implement voltage comparison and circuit control, thereby simplifying the overall circuit design.

[0049] It can be understood that when the first voltage is higher than the second voltage, the first comparator outputs a positive power supply voltage to the gate of the N-channel field-effect transistor. The N-channel field-effect transistor is turned on when receiving the positive power supply voltage to output a third voltage to the controller. When the first voltage is lower than the second voltage, the first comparator outputs a negative power supply voltage to the gate of the P-channel field-effect transistor. The P-channel field-effect transistor is turned on when receiving the negative power supply voltage to output a fourth voltage to the controller. This improves the response speed and gating accuracy of the signal processing circuit, avoids threshold drift, and further ensures the stable operation of the display device.

[0050] In one embodiment, the display device further includes a first voltage divider unit and a second voltage divider unit. The first voltage divider unit is connected in series between the first output terminal and the gate of the N-channel field-effect transistor. One end of the second voltage divider unit is connected to both the first output terminal and one end of the first voltage divider unit. The other end of the second voltage divider unit is connected to the gate of the P-channel field-effect transistor.

[0051] It is understandable that setting a first voltage divider unit can limit the amount of current flowing to the gate of the N-channel MOSFET. The current between the source and drain of the N-channel MOSFET can be controlled by adjusting the gate voltage of the N-channel MOSFET. Excessive gate current of the N-channel MOSFET can cause it to break down. Therefore, connecting a first voltage divider unit of appropriate size in series between the first output terminal and the gate of the N-channel MOSFET can effectively limit the current flowing to the gate of the N-channel MOSFET and prevent damage to the N-channel MOSFET.

[0052] It is understandable that setting up a first voltage divider unit can isolate noise, reduce the sensitivity of the N-channel field-effect transistor to noise, and improve the signal-to-noise ratio of the circuit.

[0053] It is understandable that setting up a first voltage divider unit can limit the voltage variation of the gate of the N-channel field-effect transistor, thereby effectively improving the stability of the circuit. This helps to maintain the normal operating state of the circuit and avoid changes in circuit performance caused by voltage fluctuations at the gate of the N-channel field-effect transistor.

[0054] It should be noted that the resistance value of the first voltage divider unit should be appropriate, neither too large nor too small. An excessively large resistance value may increase the power consumption of the circuit and reduce the response speed of the circuit, while an excessively small resistance value may not achieve the above effects.

[0055] It is understandable that setting a second voltage divider unit can limit the amount of current flowing to the gate of the P-channel field-effect transistor. The current between the source of the P-channel field-effect transistor and the drain of the N-channel field-effect transistor can be controlled by adjusting the gate voltage of the P-channel field-effect transistor. Excessive gate current of the P-channel field-effect transistor can cause it to break down. Therefore, the setting of this second voltage divider unit can effectively limit the current flowing to the gate of the P-channel field-effect transistor and prevent damage to the P-channel field-effect transistor.

[0056] It is understandable that a second voltage divider unit is set up. The second voltage divider unit can isolate noise, reduce the sensitivity of the P-channel field-effect transistor to noise, and improve the signal-to-noise ratio of the circuit.

[0057] It is understandable that setting a second voltage divider unit can limit the voltage variation of the gate of the P-channel field-effect transistor, thereby effectively improving the stability of the circuit. This helps to maintain the normal operating state of the circuit and avoid changes in circuit performance caused by voltage fluctuations of the gate of the P-channel field-effect transistor.

[0058] It should be noted that the resistance value of the second voltage divider unit should be appropriate, neither too large nor too small. An excessively large resistance value may increase the power consumption of the circuit and reduce the response speed of the circuit, while an excessively small resistance value may not achieve the above effects.

[0059] Optionally, the source of the P-channel MOSFET is grounded. This means that by grounding the source of the P-channel MOSFET, when it is turned on, it transmits a low-level signal to the controller.

[0060] It is understandable that the first and second voltage divider units precisely adjust the comparator output voltage to within the safe and effective range of the gate voltage of the N-channel MOSFET or P-channel MOSFET. When the positive power supply voltage is too high, the first voltage divider unit reduces the gate voltage to prevent breakdown; when the absolute value of the negative power supply voltage is too large, the second voltage divider unit adjusts the gate voltage to ensure that the conduction threshold is reached, further stabilizing the gate voltage and effectively protecting the N-channel and P-channel MOSFETs from overvoltage damage, reducing signal transmission loss, and improving the stability of port signals. Simultaneously, the first and second voltage divider units can also filter out some voltage fluctuations, enhance the circuit's anti-interference capability, reduce gating failures caused by voltage anomalies, and further ensure the reliability of the signal processing circuit.

[0061] In one embodiment, the first voltage divider unit includes at least one first resistor 202; and / or, the second voltage divider unit includes at least one second resistor 203.

[0062] It is understood that the first voltage divider unit includes at least one first resistor; and / or, the second voltage divider unit includes at least one second resistor, which takes into account both the requirements of circuit simplification and voltage division accuracy. The single resistor scheme can reduce the hardware cost and integration difficulty of the display device, reduce the circuit space occupied, and adapt to the miniaturized display device scenario; the multiple resistor scheme can accurately adjust the voltage division ratio, avoid the abnormal operation of subsequent driving circuits (such as level shifting chips) due to voltage fluctuations, ensure the stability of the voltage signal input to the display panel, and improve the stability of display image quality.

[0063] In one embodiment, the level shifting chip includes a signal conditioning module and a logic board. The signal conditioning module is electrically connected to the logic board. The level shifting chip includes a constant current output mode and a constant voltage output mode. The logic board is used to output a clock signal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is lower than a first preset voltage, the level shifting chip is used to enter the constant current output mode. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is higher than or equal to the first preset voltage, the level shifting chip is used to enter the constant voltage output mode. When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is higher than or equal to the second preset voltage, the level shifting chip is used to enter the constant current output mode. When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is lower than the second preset voltage, the level shifting chip is used to enter the constant voltage output mode.

[0064] Understandably, this design achieves automatic output mode switching through dual judgment of clock signal edge and voltage threshold. The constant current output mode ensures stable current to the display panel's light-emitting elements, avoiding uneven brightness due to current fluctuations and improving screen brightness consistency. The constant voltage output mode ensures stable voltage in the drive circuit, preventing circuit damage or signal distortion due to abnormal voltage. Simultaneously, the real-time triggering mechanism based on the clock signal enables rapid response to mode switching, adapting to high-frequency refresh rates in display devices, reducing screen ghosting caused by mode switching delays, and improving display smoothness.

[0065] In one implementation method, please refer to Figure 7 , Figure 8 and Figure 9The signal conditioning module also includes a first conditioning module, a second conditioning module, and a signal output terminal. The gates of both the first and second conditioning modules are connected to the logic board. The source of the first conditioning module and the drain of the second conditioning module are both connected to the first port of the level shifter chip. The first port is used to receive a clock signal. The output terminal of the first conditioning module is connected to the output terminal of the second conditioning module and the signal output terminal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is lower than the first preset voltage, the first conditioning module outputs a constant first conditioning current to the signal output terminal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is higher than or equal to the first preset voltage, the first conditioning module outputs a constant first conditioning voltage to the signal output terminal. When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is higher than or equal to the second preset voltage, the second conditioning module outputs a constant second conditioning current. When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is lower than the second preset voltage, the second conditioning module outputs a constant second conditioning voltage.

[0066] Understandably, this design achieves differentiated and precise processing of the rising and falling edges of the clock signal through modular conditioning, improving signal conditioning accuracy and stability. The first conditioning module focuses on the rising edge signal, while the second conditioning module focuses on the falling edge signal. This avoids the conditioning delay or insufficient accuracy problems caused by a single module processing both edges, resulting in smaller errors in the output constant current or voltage. This effectively reduces display panel drive anomalies caused by signal fluctuations and ensures the continuity of the conditioned signal, preventing signal interruptions during module switching and improving the smoothness and clarity of the displayed image. Furthermore, precise constant current or voltage output reduces component losses caused by signal instability, improving the overall reliability of the display device.

[0067] Please see Figure 6 , Figure 6 This is a schematic diagram of a signal conditioning module provided in this application. Figure 6As shown, the first conditioning module includes a first transistor 3011, a second transistor 3012, a third transistor 3013, a first NOT gate 3014, a second comparator 3015, and a third comparator 3016. The second conditioning module includes a fourth transistor 3017, a fifth transistor 3018, a sixth transistor 3019, a second NOT gate 3020, a third NOT gate 3021, a fourth comparator 3022, and a fifth comparator 3023. The logic board 303 is connected to one end of the level shifter chip 207. The gate of the first transistor 3011 and one end of the second NOT gate 3020 are connected to the logic board 207. The circuit board 303 is connected, and the other end of the second NOT gate 3020 is connected to the gate of the fourth transistor 3017. The source of the first transistor 3011 and the drain of the fourth transistor 3017 are both connected to the other end of the level shift chip 207. The drain of the first transistor 3011 is connected to the first sub-input terminal of the second comparator 3015. The source of the fourth transistor 3017 is connected to the fifth sub-input terminal of the fourth comparator 3022. The second sub-input terminal of the second comparator 3015 is connected to the third sub-input terminal of the third comparator 3016. The output terminal of the second comparator 3015 is connected to the first... One end of NOT gate 3014 is connected to the gate of the second transistor 3012. The source of the second transistor 3012 is connected to the drain of the third transistor 3013 and the display panel. The other end of the first NOT gate 3014 is connected to the gate of the third transistor 3013. The source of the third transistor 3013 is connected to the output and fourth sub-input of the third comparator 3016. The sixth sub-input of the fourth comparator 3022 is connected to the seventh sub-input of the fifth comparator 3023. The output of the fourth comparator 3022 is connected to one end of the third NOT gate 3021. The gate of the fifth transistor 3018 is connected to the gate of the sixth transistor 3019. The source of the fifth transistor 3018 is connected to the drain of the sixth transistor 3019, the source of the second transistor 3012, the drain of the third transistor 3013, and the display panel. The eighth sub-input terminal of the fifth comparator 3023 is connected to the output terminal of the fifth comparator 3023 and the source of the sixth transistor 3019. The drain of the second transistor 3012 is used to input the first operating voltage, and the drain of the fifth transistor 3018 is used to input the second operating voltage.

[0068] Optionally, the voltage value of the first operating voltage is the same as the voltage value of the second operating voltage. Optionally, the current value corresponding to the first operating voltage (first operating current) is the same as the current value corresponding to the second operating voltage (second operating current).

[0069] Optionally, when the signal conditioning module receives the second rising edge of the clock signal, the logic board 303 outputs a signal "1", turning on the first transistor 3011. When the waveform of the clock signal transitions from low to high level and the voltage of the clock signal is lower than the first preset voltage, the second transistor 3012 turns on the level shift chip 207 to enter the constant current output mode, driving the voltage to rise with a constant current. When the voltage value is greater than the first preset voltage, the third transistor 3013 turns on, and the level shift chip 207 switches to the constant voltage output mode, maintaining a constant positive level.

[0070] Optional, please see Figure 9 , Figure 9 The bold lines in the text represent the ideal state of the clock signal. Figure 9 The regular lines in the diagram represent the actual state of the clock signal. When the signal conditioning module receives the second falling edge of the clock signal, logic board 303 outputs a signal "0", the fourth transistor 3017 turns on, and when the clock signal voltage is higher than or equal to the second preset voltage, the fifth transistor 3018 turns on. The level shift chip 207 operates in constant current output mode, driving the voltage rise with a constant current. When the waveform voltage value is lower than the second preset voltage, the level shift chip 207 switches to constant voltage output mode, and the sixth transistor 3019 turns on, maintaining a constant negative level. The two constant currents are of the same magnitude but opposite in direction, primarily to delay voltage spikes at the rising and falling edges of the clock signal waveform, thus avoiding the generation of current spikes.

[0071] This design, through a refined combination of components and a feedback calibration mechanism, achieves ultra-high precision conditioning of the clock signal edge. Transistors control the current or voltage output, NOT gates invert logic signals to precisely switch transistor states, and comparators determine voltage thresholds and calibrate the output signal. These three components work together to reduce current or voltage errors after conditioning, effectively avoiding issues such as color deviation and image ghosting on the display panel caused by signal distortion, thus greatly improving the consistency of display quality. Furthermore, the feedback calibration mechanism of the third comparator 3016 and the fifth comparator 3023 can correct output signal deviations in real time, ensuring signal stability and enhancing the display device's anti-interference capabilities. In addition, the independent supply of the first and second operating voltages avoids power supply interference between modules, ensuring the conditioning module's response speed under high-frequency clock signals and adapting to high frame rate display scenarios.

[0072] Please see Figure 4 , Figure 4 This application provides a schematic flowchart of a driving method for a display device. The display device includes a controller and a level shifter chip, which are electrically connected. The controller includes a receiving port, and the level shifter chip includes a fast discharge mode and a power-off state bit, such as... Figure 4As shown, the control method for the display device includes steps S401 to S402, as detailed below. S401: When the controller's receiving port receives the first rising edge of the port signal, the controller sends a first signal to the level shift chip to force the level shift chip to clear the power-off state bit.

[0073] S402: When the controller's receiving port receives the first falling edge of the port signal, the controller sends a second signal to the level shift chip to force the level shift chip into fast discharge mode.

[0074] In one embodiment, the display device further includes a signal processing circuit, which receives a first voltage and a second voltage, wherein the first voltage is the power supply voltage of the power management chip and the second voltage is a preset voltage; the port signal includes a high-level signal and a low-level signal; when the first voltage is higher than or equal to the second voltage, the port signal output by the signal processing circuit is a high-level signal; when the first voltage is lower than the second voltage, the port signal output by the signal processing circuit is a low-level signal.

[0075] It is understandable that the signal processing circuit compares the first voltage with the second voltage. When the first voltage is higher than or equal to the second voltage, the port signal output by the signal processing circuit is a high-level signal; when the first voltage is lower than the second voltage, the port signal output by the signal processing circuit is a low-level signal. This improves the adaptability and anti-interference capability of the port signal to changes in the power supply voltage, ensures that the signal received by the controller can accurately match the actual state of the power management chip, thereby ensuring the correctness of sending instructions to the level shifting chip, reducing abnormal operation of the display device caused by power supply voltage fluctuations, and enhancing the stability of the driving method.

[0076] It is understandable that when the controller's receiving port captures the first rising edge of the port signal, it sends a first signal to forcibly clear the power-off state bit of the level shifter chip. When the controller's receiving port captures the first falling edge, it sends a second signal to force the level shifter chip to enter a fast discharge mode. The first rising edge corresponds to a critical signal node in the initial stage of the display device's startup. Clearing the power-off state bit at this time can completely eliminate residual power-off state interference in the chip, ensuring that the chip responds to subsequent drive commands in its initial normal state and avoiding startup failures. The first falling edge corresponds to the initial stage of signal switching. Forced fast discharge can accelerate the release of excess charge inside the chip, reduce the impact of charge accumulation on signal transmission, improve the accuracy of controlling the level shifter chip, improve the stability of the circuit, reduce circuit noise, speed up the discharge speed during signal switching, and improve the problem of power-off ghosting on the display.

[0077] Please see Figure 5 , Figure 5This is a schematic diagram of the structure of a display device provided in this application. Figure 5 As shown, the display device 500 includes a processor 501 and a memory 502, wherein the memory 502 is used to store computer instructions, and the processor 501 is used to invoke the computer instructions to execute the method as described above, wherein: When the controller's receiving port receives the first rising edge of the port signal, the processor 501 controls the controller to send a first signal to the level shift chip so that the level shift chip forcibly clears the power-off state bit. When the controller's receiving port receives the first falling edge of the port signal, the processor 501 controls the controller to send a second signal to the level shift chip, so that the level shift chip is forced to enter the fast discharge mode.

[0078] In one embodiment of this application, the display device further includes a signal processing circuit. The signal processing circuit is used to receive a first voltage and a second voltage. The first voltage is the power supply voltage of the power management chip, and the second voltage is a preset voltage. The port signal includes a high-level signal and a low-level signal. When the first voltage is higher than or equal to the second voltage, the processor 501 is used to control the port signal output by the signal processing circuit to be a high-level signal; when the first voltage is lower than the second voltage, the processor 501 is used to control the port signal output by the signal processing circuit to be a low-level signal.

[0079] In this embodiment, when the first voltage is greater than the second voltage, the controller controls the level shift chip to clear the off state bit; when the first voltage is less than the second voltage, the controller controls the level shift chip to enter the discharge mode. This allows the controller to control the operation of the level shift chip according to the magnitude of the first and second voltages, improving the accuracy of the level shift chip's operation and mitigating the power-down ghosting problem of the display.

[0080] In one embodiment of this application, when the first voltage is greater than the second voltage, the processor 501 controls the source of the N-channel field-effect transistor to output a third voltage to the sixth input terminal, and controls the level shift chip to clear the off state bit through the controller.

[0081] In one embodiment of this application, when the first voltage is less than the second voltage, the processor 501 controls the drain of the P-channel field-effect transistor to output a fourth voltage to the sixth input terminal, and controls the level shift chip to enter the discharge mode through the controller.

[0082] Those skilled in the art will understand that, for ease of explanation, Figure 5Only one memory 502 and processor 501 are shown in the illustration. In a real terminal or server, multiple processors 501 and memory 502 may exist. The memory 502 may also be referred to as a storage medium or storage device, etc., and this embodiment does not impose any limitations on this.

[0083] It should be understood that in this application, the processor 501 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 501 may also employ a general-purpose microprocessor, graphics processing unit (GPU), or one or more integrated circuits to execute relevant programs to achieve the functions required by the embodiments of this application.

[0084] Processor 501 can also be an integrated circuit chip with signal processing capabilities. In implementation, each step of this application can be completed by the integrated logic circuitry in the hardware of processor 501 or by instructions in software form. The processor 501 described above can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 502. Processor 501 reads the information in memory 502 and, in conjunction with its hardware, completes the functions required by the units included in the methods, apparatus, and storage media of the embodiments of this application.

[0085] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). The memory 502 can also be a Compact Disc Read-Only Memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. The memory 502 can exist independently and be connected to the processor 501 via a bus. Alternatively, the memory 502 can be integrated with the processor 501. The memory 502 can store programs, and when the program stored in the memory 502 is executed by the processor 501, the processor 501 performs the various steps of the determination method in the above embodiments of this application.

[0086] It should be noted that when the processor 501 is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory 502 (memory module) is integrated into the processor 501. It should be noted that the memory 502 described herein is intended to include, but is not limited to, these and any other suitable types of memory 502.

[0087] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0088] In implementation, each step of the above method can be completed by the integrated logic circuitry of the hardware in the processor 501 or by instructions in software form. The steps of the method disclosed in the embodiments of this application can be directly manifested as execution by the hardware processor, or by a combination of hardware and software modules in the processor 501. The software modules can be located in mature storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 502. The processor 501 reads the information in memory 502 and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, these will not be described in detail here.

[0089] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0090] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer-programmed program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a processor, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic) or wireless (e.g., infrared, wireless, microwave, etc.) means, or from one website, computer, server, or data center to a mobile phone processor via a wired means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0091] In the description of the embodiments of the present invention, it should be noted that if the orientation or positional relationship of the terms "center", "upper", "lower", "left", "right", "horizontal", "inner", "outer" and other indicators are based on the orientation or positional relationship of the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0092] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A driving method for a display device, characterized in that, The display device includes a controller and a level shifting chip, the controller and the level shifting chip are electrically connected, the controller includes a receiving port, and the level shifting chip includes a fast discharge mode and a power-off state bit; When the controller's receiving port receives the first rising edge of the port signal of the receiving port, the controller sends a first signal to the level shift chip to force the level shift chip to clear the power-off state bit; When the controller's receiving port receives the first falling edge of the port signal, the controller sends a second signal to the level shift chip to force the level shift chip into the fast discharge mode.

2. The driving method according to claim 1, characterized in that, The display device further includes a signal processing circuit, which is used to receive a first voltage and a second voltage, wherein the first voltage is the power supply voltage of the power management chip and the second voltage is a preset voltage; The port signals include high-level signals and low-level signals; When the first voltage is higher than or equal to the second voltage, the port signal output by the signal processing circuit is the high-level signal; When the first voltage is lower than the second voltage, the port signal output by the signal processing circuit is the low-level signal.

3. A display device, characterized in that, The system includes a display panel and a driving circuit, the display panel and the driving circuit being electrically connected. The driving circuit includes the driving method as described in claim 1 or 2. The driving circuit further includes the controller, the level shifting chip, and / or the signal processing circuit. The controller is electrically connected to the level shifting chip, and / or the controller is electrically connected to the signal processing circuit. The controller includes a receiving port. The level shifting chip includes a fast discharge mode and a power-off state bit, wherein: When the controller receives the first rising edge of the port signal of the receiving port, the controller sends a first signal to the level shift chip to force the level shift chip to clear the power-off state bit. When the controller's receiving port receives the first falling edge of the port signal, the controller is also used to send a second signal to the level shift chip to force the level shift chip into the fast discharge mode.

4. The display device according to claim 3, characterized in that, The signal processing circuit includes a first comparison module, a first gating module, and a second gating module. The first input terminal of the first comparison module is used to input a first voltage, the second input terminal of the first comparison module is used to input a second voltage, the third input terminal of the first comparison module is used to input a positive power supply voltage, and the fourth input terminal of the first comparison module is used to input a negative power supply voltage. The first output terminal of the first comparison module is connected to the gate of the first gating module and the gate of the second gating module. The drain of the first gating module is used to input a third voltage, and the source of the first gating module is connected to the drain of the second gating module and the receiving port of the controller. The first gating module is turned on when receiving a positive voltage, and the source of the second gating module is used to input a fourth voltage, which is less than the third voltage. The second gating module is turned on when receiving a negative voltage. The first comparison module compares the magnitudes of the first voltage and the second voltage. When the first voltage is higher than the second voltage, the first comparison module controls the first selection module to output the positive power supply voltage to the gate of the first selection module. When the first voltage is lower than the second voltage, the first comparison module is controlled to output the negative power supply voltage to the gate of the second selection module.

5. The display device according to claim 4, characterized in that, The first comparison module includes a first comparator, the first gating module includes an N-channel field-effect transistor, the second gating module includes a P-channel field-effect transistor, and the first output terminal of the first comparator is connected to the gate of the N-channel field-effect transistor and the gate of the P-channel field-effect transistor. When the first voltage is higher than the second voltage, the first comparator outputs the positive power supply voltage to the gate of the N-channel field-effect transistor, and the N-channel field-effect transistor is turned on when receiving the positive power supply voltage to output the third voltage to the controller; When the first voltage is lower than the second voltage, the first comparator outputs the negative power supply voltage to the gate of the P-channel field-effect transistor, and the P-channel field-effect transistor is turned on when receiving the negative power supply voltage to output the fourth voltage to the controller.

6. The display device according to claim 5, characterized in that, The display device further includes a first voltage divider unit and a second voltage divider unit. The first voltage divider unit is connected in series between the first output terminal and the gate of the N-channel field-effect transistor. One end of the second voltage divider unit is connected to both the first output terminal and one end of the first voltage divider unit. The other end of the second voltage divider unit is connected to the gate of the P-channel field-effect transistor.

7. The display device according to claim 6, characterized in that, The first voltage divider unit includes at least one first resistor; and / or, the second voltage divider unit includes at least one second resistor.

8. The display device according to claim 3, characterized in that, The level shifting chip includes a signal conditioning module and a logic board. The signal conditioning module is electrically connected to the logic board. The level shifting chip includes a constant current output mode and a constant voltage output mode. The logic board is used to output a clock signal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is lower than the first preset voltage, the level shifting chip is used to enter the constant current output mode. When the signal conditioning module receives the second rising edge of the clock signal, and the voltage of the clock signal is higher than or equal to the first preset voltage, the level shifting chip is used to enter the constant voltage output mode. When the signal conditioning module receives the second falling edge of the clock signal, and the voltage of the clock signal is higher than or equal to the second preset voltage, the level shifting chip is used to enter the constant current output mode. When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is lower than the second preset voltage, the level shifting chip is used to enter the constant voltage output mode.

9. The display device according to claim 8, characterized in that, The signal conditioning module further includes a first conditioning module, a second conditioning module, and a signal output terminal. The gates of the first conditioning module and the second conditioning module are both connected to the logic board. The source of the first conditioning module and the drain of the second conditioning module are both connected to the first port of the level shifting chip. The first port is used to receive the clock signal. The output terminal of the first conditioning module is connected to the output terminal of the second conditioning module and the signal output terminal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is lower than the first preset voltage, the first conditioning module is used to output a constant first conditioning current to the signal output terminal. When the signal conditioning module receives the second rising edge of the clock signal and the voltage of the clock signal is higher than or equal to the first preset voltage, the first conditioning module is used to output a constant first conditioning voltage to the signal output terminal. When the signal conditioning module receives the second falling edge of the clock signal, and the voltage of the clock signal is higher than or equal to the second preset voltage, the second conditioning module is used to output a constant second conditioning current; When the signal conditioning module receives the second falling edge of the clock signal and the voltage of the clock signal is lower than the second preset voltage, the second conditioning module outputs a constant second conditioning voltage.

10. The display device according to claim 9, characterized in that, The first conditioning module includes a first transistor, a second transistor, a third transistor, a first NOT gate, a second comparator, and a third comparator. The second conditioning module includes a fourth transistor, a fifth transistor, a sixth transistor, a second NOT gate, a third NOT gate, a fourth comparator, and a fifth comparator. The logic board is connected to one end of the level shifting chip. The gate of the first transistor and one end of the second NOT gate are connected to the logic board. The other end of the second NOT gate is connected to the gate of the fourth transistor. The source of the first transistor and the drain of the fourth transistor are both connected to the other end of the level shifting chip. The drain of the first transistor is connected to the first sub-input of the second comparator. The source of the fourth transistor is connected to the fifth sub-input of the fourth comparator. The second sub-input of the second comparator is connected to the third sub-input of the third comparator. The output of the second comparator is connected to one end of the first NOT gate and the gate of the second transistor. The second transistor is connected to the source of the third transistor and the drain of the third transistor, as well as to the display panel. The other end of the first NOT gate is connected to the gate of the third transistor. The source of the third transistor is connected to the output of the third comparator and the fourth sub-input of the third comparator. The sixth sub-input of the fourth comparator is connected to the seventh sub-input of the fifth comparator. The output of the fourth comparator is connected to one end of the third NOT gate and the gate of the fifth transistor. The other end of the third NOT gate is connected to the gate of the sixth transistor. The source of the fifth transistor is connected to the drain of the sixth transistor, the source of the second transistor, the drain of the third transistor, and the display panel. The eighth sub-input of the fifth comparator is connected to the output of the fifth comparator and the source of the sixth transistor. The drain of the second transistor is used to input a first operating voltage, and the drain of the fifth transistor is used to input a second operating voltage.

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