Compensation circuit, gate drive module, gate drive circuit and display panel

Abstract

The application discloses a compensation circuit, a gate driving module, a gate driving circuit and a display panel. The compensation circuit is connected with a target power signal and a target control signal, and is connected with a control end of a target transistor. A first end of the target transistor is connected with a reference voltage signal, and a second end of the target transistor is connected with a back-end circuit. When the back-end circuit of the target transistor needs to work, the compensation circuit is configured by the target control signal to output a compensation voltage to the control end of the target transistor. The compensation voltage is the sum of a power voltage of the target power signal and a threshold voltage of the target transistor, so that the target transistor is turned on, and a reference voltage of the reference voltage signal is transmitted to the back-end circuit through the target transistor. Through the compensation circuit, the influence of threshold voltage drift of the target transistor on the back-end circuit can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a compensation circuit, a gate driving module, a gate driving circuit, and a display panel. Background Technology

[0002] During long-term operation, the threshold voltage of a transistor is prone to drift, which can affect the normal operation of the connected downstream circuits and lead to overall circuit malfunctions.

[0003] Therefore, how to reduce the impact of transistor threshold voltage drift on its back-end circuits has become an urgent technical problem to be solved. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide a compensation circuit, a gate driving module, a gate driving circuit, and a display panel that can reduce the impact of threshold voltage drift of the target transistor on its back-end circuit.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a compensation circuit, wherein the compensation circuit is connected to a target power supply signal and a target control signal, and the compensation circuit is connected to the control terminal of the target transistor, the first terminal of the target transistor is connected to a reference voltage signal, and the second terminal of the target transistor is connected to a back-end circuit; wherein, when the back-end circuit of the target transistor needs to work, the compensation circuit is configured by the target control signal to output a compensation voltage to the control terminal of the target transistor, the compensation voltage being the sum of the power supply voltage of the target power supply signal and the threshold voltage of the target transistor, thereby turning on the target transistor, and the reference voltage of the reference voltage signal is transmitted to the back-end circuit through the target transistor.

[0006] In one embodiment, the compensation circuit includes a first switching unit, a storage unit, and a second switching unit. The first switching unit is connected to a target power signal, the storage unit is connected to the control terminal of the target transistor, the first switching unit, and the second switching unit, and the second switching unit is also connected to the second terminal of the target transistor. The circuit configures the on / off state of the first and second switching units through a target control signal and the on / off state of the target transistor through a reference voltage signal. The threshold voltage of the target transistor is stored in the storage unit. When the back-end circuit of the target transistor needs to operate, the power supply voltage of the target power signal and the threshold voltage stored in the storage unit are output to the control terminal of the target transistor.

[0007] In one embodiment, the target control signal includes a first configuration signal and a second configuration signal. The control terminal of the first switching unit is connected to the first configuration signal, and the control terminal of the second switching unit is connected to the second configuration signal. Specifically, in a first stage: the first switching unit is configured to be turned on by the first configuration signal, the second switching unit is configured to be turned on by the second configuration signal, and the target transistor is turned off under the action of a reference voltage signal. In a second stage following the first stage: the first switching unit is configured to be turned off by the first configuration signal, the second switching unit is configured to be turned off by the second configuration signal, and the target transistor is first turned on and then turned off under the action of the reference voltage signal, so that the threshold voltage of the target transistor is stored in a memory cell. When the back-end circuit of the target transistor needs to operate, the first switching unit is configured to be turned on by the first configuration signal, the second switching unit is configured to be turned off by the second configuration signal, and the voltage at the control terminal of the target transistor is raised to a compensation voltage.

[0008] In one embodiment, the first switching unit includes a first transistor, a first terminal of which is connected to a target power signal, a second terminal of which is connected to a storage unit, and a control terminal of which is connected to a first configuration signal; and / or, the second switching unit includes a second transistor, a first terminal of which is connected to a storage unit, a second terminal of which is connected to a second terminal of a target transistor, and a control terminal of which is connected to a second configuration signal; and / or, the storage unit includes a first capacitor, a first terminal of which is connected to the first switching unit, and a second terminal of which is connected to the control terminal of the target transistor and the second switching unit.

[0009] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a gate driving module, the gate driving module comprising: a first input circuit connected to a first node, configured to precharge the first node under the control of a first input signal; an output circuit connected to the first node, configured to raise the potential of the first node under the action of a clock signal, and output the clock signal as a driving signal; a second input circuit connected to the first node, configured to pull down the potential of the first node under the control of a second input signal; a control circuit connected to the first node and the second node, configured to pull down the potential of the second node when the potential of the first node is not pulled down, and to pull up the potential of the second node when the potential of the first node is pulled down; a first reset circuit connected to the first node, the second node and the output terminal of the output circuit, configured to pull down the potential of the first node and the potential of the output terminal of the output circuit when the potential of the second node is pulled up; and at least one of the aforementioned compensation circuits for outputting a compensation voltage to the control terminal of at least one transistor in the first input circuit and the control circuit, wherein one compensation circuit corresponds to one transistor.

[0010] In one embodiment, at least one compensation circuit includes a first compensation circuit, and the first input circuit includes a first input transistor and a second input transistor. The first compensation circuit is connected to a first power supply signal and a first control signal, and the first compensation circuit is connected to the control terminal of the first input transistor. The first terminal of the first input transistor is connected to a first reference voltage signal, the second terminal of the first input transistor is connected to the first terminal of the second input transistor, the second terminal of the second input transistor is connected to a first node, and the control terminal of the second input transistor is connected to a first input signal.

[0011] In one embodiment, the control circuit includes a first control sub-circuit and a second control sub-circuit, the first control sub-circuit including a first control transistor and a second control transistor; at least one compensation circuit includes a second compensation circuit, the second compensation circuit being connected to a second power supply signal and a second control signal, and the second compensation circuit being connected to the control terminal of the first control transistor, the first terminal of the first control transistor being connected to a second reference voltage signal, and the second terminal of the first control transistor being connected to the control terminal of the second control transistor and the second control sub-circuit respectively, the first terminal of the second control transistor being connected to the control terminal of the first control transistor, and the second terminal of the second control transistor being connected to a second node; or, at least one compensation circuit includes a third compensation circuit, the third compensation circuit being connected to a third power supply signal and a third control signal, and the third compensation circuit being connected to the control terminal of the second control transistor, the first terminal of the second control transistor being connected to the third reference voltage signal, the second terminal of the second control transistor being connected to a second node, the first terminal and the control terminal of the first control transistor being connected to a power supply signal, and the second terminal of the first control transistor being connected to the second control sub-circuit.

[0012] In one embodiment, the gate drive module further includes a second reset circuit connected to the output terminal of the first node and the output circuit. The second reset circuit is configured to pull down the potential of the first node and the output terminal of the output circuit when an inter-frame reset signal is received.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a gate driving circuit, which includes multiple cascaded gate driving modules, and each gate driving module is any of the gate driving modules described above.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a display panel, which includes the aforementioned gate driving circuit.

[0015] In the above scheme, when the back-end circuit of the target transistor needs to operate, the compensation circuit is configured by the target control signal to output a compensation voltage to the control terminal of the target transistor, causing the target transistor to conduct. The reference voltage signal is then transmitted to the back-end circuit through the target transistor. Since the compensation voltage is the sum of the power supply voltage of the target power signal and the threshold voltage of the target transistor (i.e., incorporating the threshold voltage of the target transistor into the compensation voltage), the compensation voltage adjusts synchronously with changes in the threshold voltage of the target transistor. This compensates for changes in the threshold voltage of the target transistor, preventing abnormal conduction or failure to conduct due to threshold voltage drift. In other words, the target transistor can conduct normally when the back-end circuit needs to operate, correctly transmitting the reference voltage signal to the back-end circuit. Therefore, using this compensation circuit can reduce the impact of threshold voltage drift of the target transistor on its back-end circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of the compensation circuit provided in this application; Figure 2 This is a schematic diagram of another embodiment of the compensation circuit provided in this application; Figure 3 This is a schematic diagram of the structure of an embodiment of the gate driving module provided in this application; Figure 4 This is a schematic diagram of another embodiment of the gate drive module provided in this application; Figure 5 This is a timing diagram of the gate drive module provided in this application; Figure 6 This is a schematic diagram of another embodiment of the gate driving module provided in this application; Figure 7 This is another timing diagram of the gate drive module provided in this application; Figure 8 This is a schematic diagram of another embodiment of the gate driving module provided in this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] It should be noted that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. The term "multiple" in this application means at least two, such as two, three, etc. The term "several" in this application means at least two. The term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships may exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0019] Please see Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the compensation circuit provided in this application. Figure 1 As shown, the compensation circuit 10 is connected to the target power signal and the target control signal, and the compensation circuit 10 is connected to the control terminal of the target transistor 20. The first terminal of the target transistor 20 is connected to the reference voltage signal, and the second terminal of the target transistor 20 is connected to the back-end circuit 30.

[0020] When the back-end circuit 30 of the target transistor 20 needs to work, the compensation circuit 10 is configured by the target control signal to output a compensation voltage to the control terminal of the target transistor 20. The compensation voltage is the sum of the power supply voltage of the target power signal and the threshold voltage of the target transistor 20, so that the target transistor 20 is turned on and the reference voltage of the reference voltage signal is transmitted to the back-end circuit 30 through the target transistor 20.

[0021] In one embodiment, the target transistor 20 is an n-type TFT (Thin-Film Transistor).

[0022] In one embodiment, when the reference voltage signal connected to the target transistor 20 is high, the reference voltage it provides is equal to the power supply voltage provided by the target power supply signal; when the reference voltage signal connected to the target transistor 20 is low, the reference voltage it provides is equal to the Vcom voltage, such as 0V.

[0023] In this embodiment, when the back-end circuit of the target transistor needs to operate, the compensation circuit is configured by the target control signal to output a compensation voltage to the control terminal of the target transistor, causing the target transistor to conduct. The reference voltage of the reference voltage signal is then transmitted to the back-end circuit through the target transistor. Since the compensation voltage is the sum of the power supply voltage of the target power signal and the threshold voltage of the target transistor (i.e., incorporating the threshold voltage of the target transistor into the compensation voltage), the compensation voltage is adjusted synchronously with the change in the threshold voltage of the target transistor. This can offset the change in the threshold voltage of the target transistor, preventing the target transistor from abnormally conducting or failing to conduct due to threshold voltage drift. In other words, the target transistor can conduct normally when the back-end circuit needs to operate, correctly transmitting the reference voltage signal to the back-end circuit. Therefore, using this compensation circuit can reduce the impact of the threshold voltage drift of the target transistor on its back-end circuit.

[0024] Please see Figure 2 , Figure 2 This is a schematic diagram of another embodiment of the compensation circuit provided in this application. Figure 2 As shown, the compensation circuit 10 includes a first switching unit 11, a storage unit 12, and a second switching unit 13. The first switching unit 11 is connected to the target power signal. The storage unit 12 is connected to the control terminal of the target transistor 20, the first switching unit 11, and the second switching unit 13. The second switching unit 13 is also connected to the second terminal of the target transistor 20. Specifically, the target control signal includes a first configuration signal and a second configuration signal. The first terminal of the first switching unit 11 is connected to the target power signal. The second terminal of the first switching unit 11 is connected to the first terminal of the storage unit 12, and the control terminal of the first switching unit 11 is connected to the first configuration signal. The second terminal of the storage unit 12 is connected to the control terminal of the target transistor 20 and the first terminal of the second switching unit 13, and the second terminal of the second switching unit 13 is connected to the second terminal of the target transistor 20. The control terminal of the second switching unit 13 is connected to the second configuration signal.

[0025] In one embodiment, the first switching unit 11 includes a first transistor To1, wherein the first terminal, the second terminal, and the control terminal of the first transistor To1 are sequentially the first terminal, the second terminal, and the control terminal of the first switching unit 11. Specifically, the first terminal of the first transistor To1 is connected to a target power signal, the second terminal of the first transistor To1 is connected to a storage unit, and the control terminal of the first transistor To1 is connected to a first configuration signal. It should be noted that in this embodiment, the first switching unit 11 is only illustrated by example, which includes one first transistor To1. In other embodiments, the first switching unit 11 can also be implemented in other ways. For example, the first switching unit 11 may include multiple transistors connected in series.

[0026] In one embodiment, the second switching unit 13 includes a second transistor To2, wherein the first terminal, the second terminal, and the control terminal of the second transistor To2 are sequentially the first terminal, the second terminal, and the control terminal of the second switching unit 13. Specifically, the first terminal of the second transistor To2 is connected to the memory cell, the second terminal of the second transistor To2 is connected to the second terminal of the target transistor 20, and the control terminal of the second transistor To2 is connected to a second configuration signal. It should be noted that in this embodiment, the second switching unit 13 is only illustrated by example, which includes one second transistor To2. In other embodiments, the second switching unit 13 can also be implemented in other ways. For example, the second switching unit 13 can also include multiple transistors connected in series.

[0027] In one embodiment, the storage unit 12 includes a first capacitor C1, with its first and second terminals being the first and second terminals of the storage unit 12, respectively. Specifically, the first terminal of the first capacitor C1 is connected to the first switching unit 11, and the second terminal of the first capacitor C1 is connected to the control terminal of the target transistor 20 and the second switching unit 13. It should be noted that in this embodiment, the storage unit 12 is only illustrated by example, with one first capacitor C1. In other embodiments, the storage unit 12 can also be implemented in other ways. For example, the storage unit 12 can be obtained by connecting multiple capacitors in series, in parallel, or in a combination of series and parallel connections.

[0028] Figure 2 In the compensation circuit shown, the first switching unit 11 and the second switching unit 13 are switched on and off via a target control signal, and the target transistor 20 is switched on and off via a reference voltage signal. First, the threshold voltage of the target transistor 20 is stored in the storage unit 12. Then, when the back-end circuit 30 of the target transistor 20 needs to operate, the power supply voltage of the target power signal and the threshold voltage stored in the storage unit 12 are output to the control terminal of the target transistor 20. That is, the voltage output to the control terminal of the target transistor 20 is the sum of the power supply voltage of the target power signal and the threshold voltage of the target transistor 20, which is the compensation voltage.

[0029] In one embodiment, the transistors in the first switching unit 11, the second switching unit 13, and the target transistor 20 are all n-type TFTs. Furthermore, the target transistor 20 employs a symmetrical structure, meaning its source and drain are interchangeable. For example, if the target transistor 20 is an n-type TFT, when its drain voltage is less than its source voltage, the current direction reverses, and the source and drain are swapped. In this embodiment, the process of storing the threshold voltage of the target transistor 20 in the storage unit 12 includes two stages: a first stage and a second stage. The second stage follows the first stage, and the start time of the second stage is the end time of the first stage.

[0030] In the first stage: the first switching unit 11 is configured to be turned on by the first configuration signal, the second switching unit 13 is configured to be turned on by the second configuration signal, and the target transistor 20 is turned off under the action of the reference voltage signal. Specifically, in the first stage, the first configuration signal, the second configuration signal, and the reference voltage signal are all at high level. At this time, both the first switching unit 11 and the second switching unit 13 are turned on, the target power signal charges the storage unit 12 through the turned-on first switching unit 11, and the control terminal, the first terminal, and the second terminal of the target transistor 20 are all at high level, so the target transistor 20 is turned off.

[0031] In the second stage: the first switching unit 11 is configured to be off by the first configuration signal, the second switching unit 13 is configured to be off by the second configuration signal, and the target transistor 20 is first turned on and then turned off under the action of the reference voltage signal, so that the threshold voltage of the target transistor 20 is stored in the storage unit 12. Specifically, in the second stage, the first configuration signal, the second configuration signal, and the reference voltage signal are all at low level. At this time, the first switching unit 11 and the second switching unit 13 are both turned off, the storage unit 12 discharges to the control terminal of the target transistor 20, and the control terminal, the first terminal (at this time the source of the target transistor 20), and the second terminal (at this time the drain of the target transistor 20) of the target transistor 20 are at high level, low level, and high level respectively. The target transistor 20 is turned on, so that the second terminal of the target transistor 20 begins to discharge to the first terminal of the target transistor 20 until the target transistor 20 is turned off (or turned off). When the target transistor 20 is turned off, the voltage difference Vgs between its control terminal (i.e., gate) and source is equal to the threshold voltage Vth of the target transistor 20. Assuming the voltage at the control terminal of the target transistor 20 is VA, and the reference voltage at the first terminal of the target transistor 20 is Vcom (i.e., 0V), then Vgs = VA - Vcom = Vth, that is, VA = Vcom + Vth = Vth. At this time, since there is no discharge path in the storage cell 12, the voltage at the control terminal of the target transistor 20 remains at the threshold voltage of the target transistor 20 and is stored in the storage cell 12.

[0032] When the back-end circuit 30 of the target transistor 20 needs to operate, the first switching unit 11 is configured to be turned on by the first configuration signal, and the second switching unit 13 is configured to be turned off by the second configuration signal. The voltage at the control terminal of the target transistor 20 is raised to the compensation voltage. Specifically, at the end of the second stage, the back-end circuit 30 of the target transistor 20 needs to operate. The first configuration signal is high, the second configuration signal is low, and the reference voltage signal is high. At this time, the first switching unit 11 is turned on, and the second switching unit 13 is turned off. Since the voltage difference across the storage cell 12 cannot change abruptly, the voltage at the control terminal of the target transistor 20 is raised to the sum of the power supply voltage of the target power signal and the threshold voltage of the target transistor 20, that is, raised to the compensation voltage. Since the first terminal (which is the drain of the target transistor 20) is at a high level and the second terminal (which is the source of the target transistor 20) is at a low level, the target transistor 20 is turned on. The first terminal of the target transistor 20 charges the second terminal of the target transistor 20, so that the voltage at the second terminal of the target transistor 20 becomes the reference voltage of the reference voltage signal at this time.

[0033] In this embodiment, considering that transistors with threshold voltage drift in each gate driving module of the display panel can cause display abnormalities such as image retention and uneven brightness, the aforementioned compensation circuit 10 can be applied to each gate driving module of the display panel to compensate for the voltage at the control terminal of at least one target transistor 20 in each gate driving module. It should be noted that the aforementioned compensation circuit 10 can also be applied to other circuit modules that require compensation.

[0034] Please see Figure 3 , Figure 3 This is a schematic diagram of an embodiment of the gate driving module provided in this application. Figure 3 The gate driving module shown adopts an 11T1C architecture, which includes 11 TFTs and 1 capacitor. It should be noted that in other embodiments, the gate driving module may also employ other combinations of TFTs and capacitors; this embodiment does not specifically limit this. Exemplarily, each TFT in the gate driving module is an n-type TFT.

[0035] like Figure 3 As shown, the gate drive module includes a first input circuit, an output circuit, a second input circuit, a control circuit, and a first reset circuit. Figure 3In the gate drive module shown and described below, the first node corresponds to the Q point, and the second node corresponds to the QB point; VGH and GCH are both constant power supply signals, for example, the power supply voltage provided by VGH and GCH is 17V; VGL is a constant low-level signal; Gn-k is the first input signal of this stage gate drive module, Gn+k is the second input signal of this stage gate drive module, and k can be an integer greater than or equal to 1, for example, k is 4; CLKn is the clock signal of this stage gate drive module; Gn is the drive signal output by this stage gate drive circuit.

[0036] Figure 3 In the gate drive module shown, the first input circuit is connected to the first node and is configured to pre-charge the first node under the control of the first input signal (i.e., Gn-k). The first input signal comes from the preceding gate drive module.

[0037] In one embodiment, the first input circuit includes a first input transistor T1, a first terminal of the first input transistor T1 is connected to a constant power supply signal VGH, a second terminal of the first input transistor T1 is connected to a first node, and a control terminal of the first input transistor T1 is connected to a first input signal.

[0038] Figure 3 In the gate drive module shown, the output circuit is connected to the first node and is configured to raise the potential of the first node under the action of the clock signal (i.e., CLKn) and output the clock signal as the drive signal (i.e., Gn).

[0039] In one embodiment, the output circuit may further include an output transistor T5 and a second capacitor C2. A clock signal is connected to a first terminal of the output transistor T5, the second terminal of the output transistor T5 is the output terminal, and the control terminal of the output transistor T5 is connected to the first node. The first terminal of the second capacitor C2 is connected to the first node, and the second terminal of the second capacitor C2 is connected to the output terminal of the output transistor T5.

[0040] Figure 3 In the gate drive module shown, the second input circuit is connected to the first node and is configured to pull down the potential of the first node under the control of the second input signal (i.e., Gn+k). The second input signal comes from the subsequent gate drive module.

[0041] In one embodiment, the second input circuit includes a second input transistor T1A, the first terminal of the second input transistor T1A is connected to the first node, the second terminal of the second input transistor T1A is connected to a constant low-level signal VGL, and the control terminal of the second input transistor T1A is connected to a second input signal.

[0042] Figure 3In the gate drive module shown, the control circuit is connected to the first node and the second node and is configured to pull down the potential of the second node when the potential of the first node is not pulled down, and to pull up the potential of the second node when the potential of the first node is pulled down.

[0043] In one embodiment, the control circuit includes a first control sub-circuit and a second control sub-circuit. The first control sub-circuit is connected to the second control sub-circuit, a first node, and a second node, respectively, and the second control sub-circuit is also connected to the second node. The second control sub-circuit is configured to pull down the potential of the second node when the potential of the first node is not pulled down, and the first control sub-circuit is configured to pull up the potential of the second node when the potential of the first node is pulled down.

[0044] Specifically, the first control sub-circuit includes a first control transistor T7 and a second control transistor T10, and the second control sub-circuit includes a third control transistor T11 and a fourth control transistor T4. The channel width-to-length ratio of the third control transistor T11 is greater than that of the first control transistor T7, and the channel width-to-length ratio of the fourth control transistor T4 is greater than that of the second control transistor T10. The first terminal of the first control transistor T7 is connected to a constant power supply signal GCH and is also connected to the control terminal of the first control transistor T7. The second terminal of the first control transistor T7 is connected to the first terminal of the third control transistor T11. The first terminal of the second control transistor T10 is connected to the constant power supply signal GCH, and the second terminal of the second control transistor T10 is connected to the first terminal of the fourth control transistor T4. The control terminal of the second control transistor T10 is also connected to the second terminal of the first control transistor T7. The second terminals of both the third control transistor T11 and the fourth control transistor T4 are connected to a constant low-level signal, and both the control terminals of the third control transistor T11 and the fourth control transistor T4 are connected to the first node.

[0045] Figure 3 In the gate drive module shown, the first reset circuit is connected to the first node, the second node, and the output terminal of the output circuit, respectively, and is configured to pull down the potential of the first node and the potential of the output terminal of the output circuit when the potential of the second node is pulled up.

[0046] In one embodiment, the first reset circuit includes a first reset transistor T2 and a second reset transistor T6. A first terminal of the first reset transistor T2 is connected to a first node, a second terminal of the first reset transistor T2 is connected to a constant low-level signal VGL, and a control terminal of the first reset transistor T2 is connected to a second node. A first terminal of the second reset transistor T6 is connected to the output terminal of the output circuit, a second terminal of the second reset transistor T6 is connected to a constant low-level signal VGL, and a control terminal of the second reset transistor T6 is connected to the second node.

[0047] Figure 3The gate driving module shown may further include a second reset circuit. The second reset circuit is connected to the output terminals of the first node and the output circuit, and is configured to pull down the potential of the first node and the output terminal of the output circuit when an inter-frame reset signal is received. Specifically, the inter-frame reset signal is generated before the current frame display ends and the next frame display begins.

[0048] In one embodiment, the second reset circuit includes a third reset transistor T2A and a fourth reset transistor TP. The inter-frame reset signals include a first reset signal ResetQ and a second reset signal TPE. The first terminal of the third reset transistor T2A is connected to the first node, the second terminal of the third reset transistor T2A is connected to a constant low-level signal VGL, and the control terminal of the third reset transistor T2A is connected to the first reset signal. The first terminal of the fourth reset transistor TP is connected to the output terminal of the output circuit, the second terminal of the fourth reset transistor TP is connected to the constant low-level signal VGL, and the control terminal of the fourth reset transistor TP is connected to the second reset signal. By resetting between adjacent frames of display using the second reset circuit, residual voltage at the output terminals of the first node and the output circuit can be avoided.

[0049] Figure 3 In the gate drive module shown, when the first input transistor T1 operates under a constant power supply signal VGH for a long time, its threshold voltage is prone to drift. For example, after the threshold voltage of the first input transistor T1 shifts to a smaller value, the first input transistor T1 is easier to turn on. After the first input transistor T1 is abnormally turned on, the constant power supply signal VGH reaches the first node through the abnormally turned-on first input transistor T1 (i.e., leakage occurs), abnormally pre-charging the first node, making the first node high level. The high level of the first node causes the output transistor T5 in the back-end circuit to turn on abnormally, resulting in incorrect charging and ultimately causing the display screen of the display panel to be abnormal.

[0050] Figure 3 In the gate drive module shown, the first control transistor T7 and the second control transistor T10 operate under a constant power supply signal GCH for a long time, and their threshold voltages are prone to drift. For example, if the threshold voltages of the first control transistor T7 and the second control transistor T10 shift to a larger value, it will be more difficult for the first control transistor T7 and the second control transistor T10 to conduct. When the first reset transistor T2 and the second reset transistor T6 used for reset in the back-end circuit need to work, the first control transistor T7 and the second control transistor T10 cannot conduct normally, which leads to the first reset transistor T2 and the second reset transistor T6 not being able to conduct normally, thus causing abnormality in the reset stage.

[0051] Therefore, in this embodiment, at least one compensation circuit can be added to the gate driving module. The at least one compensation circuit is used to output a compensation voltage to the control terminal of at least one of the first input transistor T1, the first control transistor T7, and the second control transistor T10, and one compensation circuit corresponds to one transistor.

[0052] Please see Figure 4 , Figure 4 This is a schematic diagram of another embodiment of the gate drive module provided in this application. Figure 3 The difference between the gate drive modules shown is that... Figure 4 The gate drive module shown includes a first compensation circuit, which outputs a compensation voltage to the control terminal of the first input transistor T1. Furthermore, the first input circuit includes the first input transistor T1 and a third input transistor T14. Figure 4 As shown, the first compensation circuit is connected to a first power supply signal and a first control signal, the first control signal ( Figure 4 (Not directly illustrated) It includes a first configuration signal and a second configuration signal, and the first compensation circuit is connected to the control terminal of the first input transistor T1. The specific structure of the first compensation circuit is the same as that of the aforementioned compensation circuit. For example, the first compensation circuit also includes a first transistor To1, a second transistor To2, and a first capacitor C1. The specific circuit connection method will not be described in detail here. The first terminal of the first input transistor T1 is connected to the first reference voltage signal, the second terminal of the first input transistor T1 is connected to the first terminal of the third input transistor T14, the second terminal of the third input transistor T14 is connected to the first node, and the control terminal of the third input transistor T14 is connected to the first input signal. For example, the first power supply signal is a constant power supply signal VGH, the reference voltage provided when the first reference voltage signal is high is the power supply voltage provided by the first power supply signal, and the reference voltage provided when the first reference voltage signal is low is Vcom.

[0053] It should be noted that since the voltage at the second terminal of the first input transistor T1 is not constantly at a high level, the probability of the third input transistor T14 experiencing threshold voltage drift or severe threshold voltage drift is relatively small.

[0054] Please see Figure 5 , Figure 5 This is a timing diagram of the gate drive module provided in this application. (See diagram below.) Figure 5As shown, at time t1 (i.e., the start time of the first stage), the first configuration signal, the second configuration signal, and the first reference voltage signal are all at high level. At this time, the first transistor To1 and the second transistor To2 are both turned on. The first power supply signal charges the first capacitor C1 through the turned-on first transistor To1. The control terminal, the first terminal, and the second terminal of the first input transistor T1 are all at high level, and the first input transistor T1 is turned off.

[0055] At time t2 (t1 to t2 is the first stage, and time t2 is the start of the second stage), the first configuration signal, the second configuration signal, and the first reference voltage signal are all at low level. At this time, the first transistor To1 and the second transistor To2 are both turned off. The first capacitor C1 discharges to the control terminal of the first input transistor T1. The control terminal of the first input transistor T1, the first terminal of the first input transistor T1 (which is the source of the first input transistor T1 at this time), and the second terminal of the first input transistor T1 (which is the drain of the first input transistor T1 at this time) are at high level, low level, and high level SET is at low level, respectively. The first input transistor T1 is turned on, so that the second terminal of the first input transistor T1 begins to discharge to the first terminal of the first input transistor T1 until the first input transistor T1 is turned off (or turned off). When the first input transistor T1 is turned off, the voltage of the control terminal of the first input transistor T1 is maintained at the threshold voltage of the first input transistor T1 and is stored in the first capacitor C1.

[0056] At time t3 (t2 to t3 is the second stage, and time t3 is the end of the second stage, or the time when output transistor T5 needs to work), the first configuration signal is high, the second configuration signal is low, and the first reference voltage signal is high. Since the voltage difference across the first capacitor C1 cannot change abruptly, the voltage at the control terminal of the first input transistor T1 is raised to the compensation voltage (i.e., the sum of the power supply voltage of the first power supply signal and the threshold voltage of the first input transistor T1). Since the first terminal of the first input transistor T1 (which is the drain of the first input transistor T1 at this time) is high and the second terminal of the first input transistor T1 (which is the source of the first input transistor T1 at this time) is low, the first input transistor T1 is turned on. The first terminal of the first input transistor T1 charges the second terminal of the first input transistor T1, making the voltage at the second terminal of the first input transistor T1 the reference voltage of the first reference voltage signal at this time.

[0057] At time t3 and thereafter, the pre-charging phase, charging phase, reset phase, and holding phase are performed sequentially.

[0058] During the pre-charge phase: at time t3, the first input signal Gn-k is high, the third input transistor T14 is turned on, and the first reference voltage signal is transmitted to the first node through the turned-on first input transistor T1 and third input transistor T14 to pre-charge the first node. During the pre-charge phase, the clock signal (i.e., CLKn) is low, and even if the output transistor T5 is turned on, Gn has no output. Furthermore, during the pre-charging phase, both the first control transistor T7 and the second control transistor T10 are turned on. Since the first node is at a high level, both the third control transistor T11 and the fourth control transistor T4 are turned on. Because the channel width-to-length ratio of the third control transistor T11 is greater than that of the first control transistor T7, meaning the driving capability of the third control transistor T11 is greater than that of the first control transistor T7, and the channel width-to-length ratio of the fourth control transistor T4 is greater than that of the second control transistor T10, meaning the driving capability of the fourth control transistor T4 is greater than that of the second control transistor T10, the third control transistor T11 can pull down the potential of the control terminal of the second control transistor T10, and the fourth control transistor T4 can pull down the potential of the second node, meaning the second node is at a low level.

[0059] During the charging phase: The clock signal (CLKn) goes high because the first node has been pre-charged to the reference voltage of the first reference voltage signal. The control terminal of the output transistor T5 (i.e., the first node) is high, so the output transistor T5 is turned on. The clock signal is output to Gn through the output transistor T5, causing Gn to go high and drive the corresponding row pixel. At the same time, when Gn goes high, the potential of the first node is further raised through the coupling effect of the second capacitor C2, enhancing the driving capability of the output transistor T5 and ensuring that Gn can output a sufficiently high level.

[0060] During the reset phase: the second input signal Gn+4 goes high, the second input transistor T1A turns on, causing the first node to be pulled down to a low level, the third control transistor T11 and the fourth control transistor T4 turn off, the second node is pulled up to a high level by the first control transistor T7 and the second control transistor T10, causing the first reset transistor T2 and the second reset transistor T6 to both turn on, the first reset transistor T2 pulls down the first node to a low level, and the second reset transistor T6 pulls down the second terminal of the output transistor T5 to a low level.

[0061] During the holding phase: the first reset transistor T2 and the second reset transistor T6 remain on, and the second terminal of the first node and the output transistor T5 are pulled down to a low level.

[0062] In this embodiment, when the output transistor T5 needs to operate (or at the start of the pre-charge phase), a compensation voltage is output to the control terminal of the first input transistor T1 through the first compensation circuit. This compensates for the threshold voltage drift of the first input transistor T1, preventing it from abnormally conducting due to the threshold voltage drift and resolving the leakage phenomenon caused by the threshold voltage drift. Furthermore, this embodiment only adds two pulse durations (the first stage and the second stage) before the start of the pre-charge phase, without affecting the subsequent pre-charge phase, charging phase, reset phase, and holding phase.

[0063] Please see Figure 6 , Figure 6 This is a schematic diagram of another embodiment of the gate driving module provided in this application. Figure 3 The difference between the gate drive modules shown is that... Figure 6 The gate drive module shown includes a second compensation circuit, which outputs a compensation voltage to the control terminal of the first control transistor T7. For example... Figure 6 As shown, the second compensation circuit is connected to a second power supply signal and a second control signal, the second control signal ( Figure 6 (Not directly illustrated) This includes a first configuration signal and a second configuration signal. The second compensation circuit is connected to the control terminal of the first control transistor T7. The first terminal of the first control transistor T7 is connected to the second reference voltage signal, and the second terminal of the first control transistor T7 is connected to the control terminal of the second control transistor T10 and the second control sub-circuit (specifically, connected to the first terminal of the third control transistor T11 in the second sub-control circuit). The first terminal of the second control transistor T10 is connected to the control terminal of the first control transistor T7, and the second terminal of the second control transistor T10 is connected to the second node. For example, the second power supply signal is a constant power supply signal GCH. When the second reference voltage signal is high, the reference voltage provided is the power supply voltage provided by the second power supply signal; when the second reference voltage signal is low, the reference voltage provided is Vcom.

[0064] In one embodiment, the channel width-to-length ratio of the second transistor To2 in the second compensation circuit is greater than the channel width-to-length ratio of the third control transistor T11.

[0065] Please see Figure 7 , Figure 7 This is another timing diagram of the gate drive module provided in this application. (See diagram below.) Figure 7As shown, at time t3 (i.e., the start time of the first stage, specifically the start time of the pre-charging stage in this embodiment), the first configuration signal, the second configuration signal, and the second reference voltage signal are all at high level. At this time, the first transistor To1 and the second transistor To2 are both turned on. The second power supply signal charges the first capacitor C1 through the turned-on first transistor To1. The control terminal, the first terminal, and the second terminal of the first control transistor T7 are all at high level, and the first control transistor T7 is turned off. Furthermore, the entire gate drive module is in the pre-charge stage. Since the channel width-to-length ratio of the second transistor To2 in the second compensation circuit is greater than that of the third control transistor T11, for example, the channel width-to-length ratio of the second transistor To2 in the second compensation circuit is slightly greater than that of the third control transistor T11, that is, the driving capability of the second transistor To2 in the second compensation circuit is slightly higher than that of the third control transistor T11. The voltage at the second terminal of the first control transistor T7 can be slightly pulled down by the third control transistor T11, so that the second terminal of the first control transistor T7 is maintained at a high level less than VGH, thus preventing the voltage at the second terminal of the first control transistor T7 from being pulled down to a constant low level VGL.

[0066] At time t4 (t3 to t4 is the first stage, and time t4 is the start time of the second stage, specifically the start time of the charging stage in this embodiment), the first configuration signal, the second configuration signal, and the second reference voltage signal are all at low level. At this time, the first transistor To1 and the second transistor To2 are both turned off. The first capacitor C1 discharges to the control terminal of the first control transistor T7. The control terminal of the first control transistor T7, the first terminal of the first control transistor T7 (which is the source of the first control transistor T7 at this time), and the second terminal of the first control transistor T7 (which is the drain of the first control transistor T7 at this time) are at high level, low level, and high level SET is at low level, respectively. The first control transistor T7 is turned on, so that the second terminal of the first control transistor T7 begins to discharge to the first terminal of the first control transistor T7 until the first control transistor T7 is turned off (or turned off). When the first control transistor T7 is turned off, the voltage of the control terminal of the first control transistor T7 is maintained at the threshold voltage of the first control transistor T7 and is stored in the first capacitor C1.

[0067] At time t5 (t4 to t5 is the second stage, and time t5 is the end of the second stage; in this embodiment, it is the time when the first reset transistor T2 and the second reset transistor T6 need to start working, i.e., the start of the reset stage in this embodiment), the first configuration signal is high, the second configuration signal is low, and the second reference voltage signal is high. Since the voltage difference across the first capacitor C1 cannot change abruptly, the voltage at the control terminal of the first control transistor T7 is raised to the compensation voltage (i.e., the sum of the power supply voltage of the second power supply signal and the threshold voltage of the first control transistor T7). Since the first terminal of the first control transistor T7 (which is the drain of the first control transistor T7 at this time) is high and the second terminal of the first control transistor T7 (which is the source of the first control transistor T7 at this time) is low, the first control transistor T7 is turned on, and the first terminal of the first control transistor T7 charges the second terminal of the first control transistor T7, making the voltage at the second terminal of the first control transistor T7 the reference voltage of the second reference voltage signal at this time.

[0068] At time t5 and thereafter, both the first configuration signal and the second reference voltage signal are at high level, turning on the first control transistor T7 and the second control transistor T10, maintaining the high voltage of the second node, so that the first reset transistor T2 and the second reset transistor T6 remain on, pulling down the second terminal of the first node and the output transistor T5 to a low level.

[0069] In this embodiment, when the reset transistor needs to work (or at the beginning of the reset phase), the second compensation circuit outputs a compensation voltage to the control terminal of the first control transistor T7 to offset the threshold voltage drift of the first control transistor T7, so that the first control transistor T7 will not fail to conduct the reset transistor normally due to the threshold voltage drift, thus ensuring the reset effect.

[0070] Please see Figure 8 , Figure 8 This is a schematic diagram of another embodiment of the gate driving module provided in this application. Figure 3 The difference between the gate drive modules shown is that... Figure 8 The gate drive module shown includes a third compensation circuit, which outputs a compensation voltage to the control terminal of the second control transistor T10. Figure 8 As shown, the third compensation circuit is connected to the third power supply signal and the third control signal. The third control signal ( Figure 6(Not directly illustrated) This includes a first configuration signal and a second configuration signal. The third compensation circuit is connected to the control terminal of the second control transistor T10. The first terminal of the second control transistor T10 is connected to the third reference voltage signal, and the second terminal of the second control transistor T10 is connected to the second node. The first terminal and control terminal of the first control transistor T7 are connected to the constant power supply signal GCH, and the second terminal of the first control transistor T7 is connected to the second control sub-circuit (specifically, to the first terminal of the third control transistor T11 in the second sub-control circuit). For example, the third power supply signal is the constant power supply signal GCH, the reference voltage provided when the third reference voltage signal is high is the power supply voltage provided by the third power supply signal, and the reference voltage provided when the third reference voltage signal is low is Vcom. The principle of the third compensation circuit can be referred to the second compensation circuit, and will not be explained in detail here.

[0071] The third compensation voltage outputs a compensation voltage (i.e., the sum of the power supply voltage of the third power supply signal and the threshold voltage of the second control transistor T10) to the control terminal of the second control transistor T10 when the reset transistor needs to work (or at the beginning of the reset phase). This compensates for the threshold voltage drift of the second control transistor T10, ensuring that the second control transistor T10 will not fail to conduct the reset transistor normally due to the threshold voltage drift, thus guaranteeing the reset effect.

[0072] It should be noted that this embodiment only illustrates the case where the gate driving module includes a single first compensation circuit, a single second compensation circuit, and a single third compensation circuit. In other embodiments, two or all of the first, second, and third compensation circuits may coexist. For example, the gate driving module may include both a first compensation circuit and a second compensation circuit, where the first compensation circuit compensates for the first input transistor T1, and the second compensation circuit compensates for the first control transistor T7.

[0073] This embodiment also provides a gate driving circuit, which includes multiple cascaded gate driving modules.

[0074] In one embodiment, each stage of the gate drive module can be Figure 4 , Figure 6 and Figure 8 The gate drive module shown in any embodiment.

[0075] In one embodiment, the drive signal output terminal of the (nk)th gate drive module is connected to the first input signal terminal of the nth gate drive module, and the drive signal output terminal of the (n+k)th gate drive module is connected to the second input signal terminal of the nth gate drive module.

[0076] In a specific application, if k is 4, then the first input terminal of the nth gate driver module is connected to the output Gn-4 of the (n-4)th gate driver module, and the second input terminal of the nth gate driver module is connected to the output Gn+4 of the (n+4)th gate driver module.

[0077] Combination Figure 5 The timing diagram shows that the start time of the precharge phase (t3) corresponds to Gn-4, and the end time of the precharge phase (CLKn is high, outputting Gn). Therefore, t2 corresponds to Gn-8, and t1 corresponds to Gn-12. Thus, the second configuration signal of the first compensation circuit in the nth gate drive module can be provided by the drive signal output of the (n-12)th gate drive module, which is consistent with the timing of Gn-12. Furthermore, since the first configuration signal is high at the start of the precharge phase (t3) while CLKn is low, and low at the end of the precharge phase while CLKn is high, meaning the timing of the first configuration signal and CLKn is reversed, the first configuration signal terminal of the first compensation circuit in the nth gate drive module is connected to the clock signal terminal of the (n-4)th gate drive module, which is consistent with the timing of CLKn-4. The first reference voltage signal of the first compensation circuit in the nth gate drive module is provided separately and can be represented as Vrefn.

[0078] Combination Figure 7 In the timing diagram, the start time of the reset phase, i.e., time t5, corresponds to Gn+4, and the end time of the precharge phase, i.e., time t4, outputs Gn. Therefore, time t3 should correspond to Gn-4. Thus, the second configuration signal of the second compensation circuit in the nth gate drive module can be provided by the drive signal output of the (n-4)th gate drive module, i.e., its timing is consistent with Gn-4. Furthermore, the first configuration signal of the second compensation circuit in the nth gate drive module is provided separately, and can be represented as CLKn'. The first reference voltage signal of the second compensation circuit in the nth gate drive module is provided separately, and can be represented as Vrefn'.

[0079] This embodiment also provides a display panel, which includes the aforementioned gate driving circuit. The display panel includes a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive signal output terminal of one gate driving module in the gate driving circuit is electrically connected to at least one scan line.

[0080] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A compensation circuit, characterized in that, The compensation circuit is connected to the target power signal and the target control signal, and is connected to the control terminal of the target transistor. The first terminal of the target transistor is connected to a reference voltage signal, and the second terminal of the target transistor is connected to the back-end circuit. The compensation circuit includes a first switching unit, a storage unit, and a second switching unit. The first switching unit is connected to the target power signal, and the storage unit is connected to the control terminal of the target transistor, the first switching unit, and the second switching unit. The second switching unit is also connected to the second terminal of the target transistor. The target control signal includes a first configuration signal and a second configuration signal. The control terminal of the first switching unit is connected to the first configuration signal, and the control terminal of the second switching unit is connected to the second configuration signal. When the back-end circuit of the target transistor needs to operate, the compensation circuit is configured by the target control signal to output a compensation voltage to the control terminal of the target transistor. The compensation voltage is the sum of the power supply voltage of the target power signal and the threshold voltage of the target transistor, so that the target transistor is turned on, and the reference voltage of the reference voltage signal is transmitted to the back-end circuit through the target transistor. In the first stage: the first switching unit is configured to be turned on by the first configuration signal, the second switching unit is configured to be turned on by the second configuration signal, and the target transistor is turned off under the action of the reference voltage signal; In the second stage following the first stage: the first switching unit is configured to be turned off by the first configuration signal, the second switching unit is configured to be turned off by the second configuration signal, and the target transistor is first turned on and then turned off under the action of the reference voltage signal, so that the threshold voltage of the target transistor is stored in the memory cell; When the back-end circuit of the target transistor needs to operate, the first switching unit is configured to be turned on by the first configuration signal, the second switching unit is configured to be turned off by the second configuration signal, and the voltage at the control terminal of the target transistor is raised to the compensation voltage.

2. The compensation circuit according to claim 1, characterized in that, The first switching unit includes a first transistor, a first terminal of the first transistor is connected to the target power signal, a second terminal of the first transistor is connected to the storage unit, and a control terminal of the first transistor is connected to the first configuration signal. And / or, the second switching unit includes a second transistor, a first terminal of the second transistor is connected to the memory cell, a second terminal of the second transistor is connected to the second terminal of the target transistor, and the control terminal of the second transistor is connected to the second configuration signal; And / or, the storage unit includes a first capacitor, a first terminal of which is connected to the first switching unit, and a second terminal of which is connected to the control terminal of the target transistor and the second switching unit.

3. A gate driving module, characterized in that, The gate driving module includes: A first input circuit, connected to a first node, is configured to precharge the first node under the control of a first input signal. An output circuit, connected to the first node, is configured to raise the potential of the first node under the action of a clock signal and output the clock signal as a drive signal; The second input circuit, connected to the first node, is configured to pull down the potential of the first node under the control of the second input signal; A control circuit, connected to the first node and the second node, is configured to pull down the potential of the second node when the potential of the first node is not pulled down, and to pull up the potential of the second node when the potential of the first node is pulled down. A first reset circuit, connected to the first node, the second node, and the output terminal of the output circuit, is configured to pull down the potential of the first node and the potential of the output terminal of the output circuit when the potential of the second node is pulled up. At least one compensation circuit as described in any one of claims 1-2 is used to output the compensation voltage to the control terminal of at least one transistor in the first input circuit and the control circuit, and one compensation circuit corresponds to one transistor.

4. The gate driving module according to claim 3, characterized in that, At least one of the compensation circuits includes a first compensation circuit, and the first input circuit includes a first input transistor and a second input transistor; The first compensation circuit is connected to a first power supply signal and a first control signal, and the first compensation circuit is connected to the control terminal of the first input transistor. The first terminal of the first input transistor is connected to a first reference voltage signal, the second terminal of the first input transistor is connected to the first terminal of the second input transistor, the second terminal of the second input transistor is connected to the first node, and the control terminal of the second input transistor is connected to the first input signal.

5. The gate driving module according to claim 3, characterized in that, The control circuit includes a first control sub-circuit and a second control sub-circuit, wherein the first control sub-circuit includes a first control transistor and a second control transistor. At least one of the compensation circuits includes a second compensation circuit, the second compensation circuit is connected to a second power supply signal and a second control signal, and the second compensation circuit is connected to the control terminal of the first control transistor. The first terminal of the first control transistor is connected to a second reference voltage signal, and the second terminal of the first control transistor is connected to the control terminal of the second control transistor and the second control sub-circuit, respectively. The first terminal of the second control transistor is connected to the control terminal of the first control transistor, and the second terminal of the second control transistor is connected to the second node. or, At least one of the compensation circuits includes a third compensation circuit, which is connected to a third power supply signal and a third control signal, and is connected to the control terminal of the second control transistor. The first terminal of the second control transistor is connected to a third reference voltage signal, and the second terminal of the second control transistor is connected to the second node. The first terminal and the control terminal of the first control transistor are connected to a power supply signal, and the second terminal of the first control transistor is connected to the second control sub-circuit.

6. The gate driving module according to claim 3, characterized in that, The gate driving module further includes a second reset circuit, which is connected to the output terminal of the first node and the output circuit. The second reset circuit is configured to pull down the potential of the first node and the potential of the output terminal of the output circuit when an inter-frame reset signal is received.

7. A gate driving circuit, comprising a plurality of cascaded gate driving modules, characterized in that, The gate driving modules at each level are the gate driving modules as described in any one of claims 3 to 6.

8. A display panel, characterized in that, The display panel includes the gate driving circuit as described in claim 7.

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