Method and apparatus for traffic scheduling of wireless communication data paths

Abstract

The application provides a traffic scheduling method and device of a wireless communication data path, and relates to the technical field of communication. The method comprises the following steps: acquiring a current occupation amount of a downstream hardware buffer in a data path and a target access category of a target data queue currently transmitted; adopting a hierarchical sending strategy to control a data sending behavior of an upstream host driver according to a relationship between the current occupation amount and at least two levels of water lines corresponding to the target access category; monitoring a real-time occupation amount of a sending queue of the host driver; and controlling the host driver to feed back a flow control instruction to an upper-layer operating system according to the real-time occupation amount. In this way, the data path is regarded as an integral pipeline. By introducing the multi-level water lines and the hierarchical sending strategy and combining the feedback based on the real-time occupation amount, smooth flow control and dynamic balance of the entire pipeline are realized. Meanwhile, manual configuration and tuning dependence on parameters such as queue depths at all levels are eliminated, and zero-configuration self-adaptation is realized.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and apparatus for traffic scheduling of wireless communication data paths. Background Technology

[0002] In high-speed data transmission systems such as Wi-Fi 6, data packets flow through a typical multi-stage processing pipeline from the host application layer to final transmission via the antenna: Level 1 (Host Software Layer): The operating system's network stack delivers data packets to the device driver, which temporarily stores them in its own send queue (txq). The depth of this queue is limited by the host's memory.

[0003] Level 2 (Host-Hardware Interface Layer): The driver transfers data from host memory to on-chip memory via a DMA (Direct Memory Access) channel. The driver writes a descriptor describing the data transfer task into the ring buffer of this DMA channel. The depth of this buffer is determined by the hardware design and is typically small.

[0004] Level 3 (Chip Firmware Layer): The firmware (FW) retrieves data packets from the DMA circular buffer and places them into its internal processing buffer for MAC (Media Access Control) layer protocol processing. The depth of this buffer is also determined by the size of the chip's memory.

[0005] Ideally, a pipeline should be continuously "fed" by all three stations, with data packets flowing smoothly like on a factory assembly line. However, the processing power and buffer depth of each station vary, and the firmware's processing power can dynamically change due to the wireless environment, making it easy for the pipeline to become unbalanced.

[0006] Specifically, to support QoS (Quality of Service), modern Wi-Fi systems are inherently distributed, providing multiple parallel hardware and software queues for different Access Categories (ACs), such as voice (AC_VO), video (AC_VI), and best-effort (AC_BE). This means there are multiple parallel processing pipelines, each requiring efficient management. AC_BE is the most common traffic type, suitable for data transmission without specific QoS requirements, such as web browsing and file downloads.

[0007] Existing solutions typically employ a global, homogeneous flow control strategy for all these parallel pipelines, mainly including the following two types of solutions: Option 1: Timer-based rate control. The host driver sends fixed batches of data packets at fixed time intervals (Timer). This is an open-loop, static control method that cannot perceive the real-time status of downstream pipeline stations. The system applies uniform rate control or backpressure thresholds to all queues. When a high-traffic queue (such as AC_BE) triggers global backpressure, it unfairly blocks all other queues, even low-load voice queues.

[0008] Option 2: Control based on single-point binary backpressure. When the DMA circular buffer is full, the driver completely stops sending; when space is available, the driver resumes sending at maximum capacity. This is an improvement over Option 1, introducing feedback, but the feedback signal is too coarse (only "full / not full" states). Mechanisms such as netif_stop_queue in the Linux network subsystem also belong to this type of binary backpressure idea. This option solves the priority of packet dequeueing, but it does not solve the problem of traffic smoothing and efficiency within each pipeline, and cannot provide differentiated, optimal traffic injection strategies for different types of pipelines.

[0009] However, existing flow control strategies have the following drawbacks: 1. Inability to achieve pipeline optimization: Both existing solutions only focus on the traffic of a single interface (driver to DMA) without optimizing the entire multi-stage pipeline as a whole. Neither single-queue nor multi-queue systems can solve the deeper problems of "pipeline bubble" (downstream sites waiting idly) and "pipeline stagnation" (upstream sites forced to wait due to downstream congestion).

[0010] 2. The control granularity is too coarse, lacking flow isolation and differentiation: The timer scheme has absolutely no dynamism.

[0011] While binary backpressure schemes are dynamic, their "stop-and-go" control leads to severe jitter in the data stream. The system oscillates between two extremes: "sending at full speed, causing downstream congestion" and "completely stopping, causing downstream starvation," failing to achieve a smooth and efficient pipeline state.

[0012] A "one-size-fits-all" flow control strategy cannot meet the diverse needs of different data flows, resulting in the inability to effectively guarantee the service quality of high-priority traffic.

[0013] 3. Reliance on manual tuning: To achieve better performance in specific scenarios, both solutions implicitly require engineers to manually adjust parameters. For example, the depth of the TXQ driver, timer timeout values, and DMA queue depth. These parameters are interconnected, making the tuning process complex, time-consuming, and lacking cross-platform and cross-scenario applicability. Furthermore, a set of compromise parameters needs to be manually set for the entire system, making it impossible to "tailor-make" an optimal strategy for each queue or adapt to dynamically changing network loads. Summary of the Invention

[0014] The purpose of this invention is to provide a traffic scheduling method and apparatus for wireless communication data paths, so as to at least solve one of the above-mentioned problems.

[0015] In a first aspect, the present invention provides a traffic scheduling method for a wireless communication data path, comprising: Obtain the current occupancy of downstream hardware buffers in the data path and the target access category of the target data queue currently being transmitted; Based on the relationship between the current occupancy and at least two water level levels corresponding to the target access category, a hierarchical sending strategy is adopted to control the data sending behavior of the upstream host driver. Monitor the real-time occupancy of the send queue of the host driver; Based on real-time occupancy, the host driver controls the flow control commands to be fed back to the upper-level operating system.

[0016] In an optional implementation, at least two water level levels are included, comprising a low water level and a high water level, and the hardware buffer includes a DMA buffer; based on the relationship between the current occupancy and the at least two water level levels corresponding to the target access category, a hierarchical transmission strategy is adopted to control the data transmission behavior of the upstream host driver, including: When the current occupancy is less than the low watermark, the host driver controls the maximum capacity to retrieve data from the corresponding data queue of its send queue and submits the DMA task to the DMA buffer. When the current occupancy is greater than or equal to the low watermark and less than the high watermark, the host driver controls the DMA task to be submitted at a smooth and sustainable rate. When the current occupancy is greater than or equal to the high watermark and less than the maximum capacity of the DMA buffer, the host driver is controlled to reduce the sending rate. When the current occupancy equals the maximum capacity of the DMA buffer, the host driver stops submitting DMA tasks.

[0017] In an optional implementation, the target data queue includes multiple parallel data queues, and the target access category includes one or more of voice, video, best-effort, and background. Each of the multiple parallel data queues independently executes the step of controlling the data transmission behavior driven by the upstream host using a hierarchical transmission strategy based on the relationship between the current occupancy and at least two water level levels corresponding to the target access category.

[0018] In an optional implementation, at least two water level levels are configured based on the service objectives of the corresponding access categories; the water level corresponding to the access category of low-latency flows is shallower than the water level corresponding to the access category of high-throughput flows.

[0019] In an optional implementation, based on real-time occupancy, the host driver is controlled to send flow control commands to the upper-level operating system, including: Based on the relationship between real-time occupancy and preset high and low thresholds, the host driver controls the system to send instructions to pause or resume transmission.

[0020] In an optional implementation, based on the relationship between real-time occupancy and preset high and low thresholds, the host driver is controlled to send a pause or resume transmission command to the operating system, including: When the real-time usage exceeds the high threshold, the host driver calls the corresponding interface of the operating system to suspend the upper-layer network protocol stack from delivering data packets to the host driver. When the real-time usage drops below a low threshold, the host driver calls the corresponding interface of the operating system to notify the operating system to resume sending data packets.

[0021] In a second aspect, the present invention provides a traffic scheduling device for a wireless communication data path, comprising: The transmission control module is used to obtain the current occupancy of the downstream hardware buffer in the data path and the target access category of the target data queue being transmitted. Based on the relationship between the current occupancy and the target access category and at least two water level lines, it adopts a hierarchical transmission strategy to control the data transmission behavior of the upstream host driver. The feedback control module is used to monitor the real-time occupancy of the host driver's send queue and, based on the real-time occupancy, control the host driver to send flow control commands to the upper-layer operating system.

[0022] In an optional implementation, the target data queue includes multiple parallel data queues; the transmission control module includes multiple independent rate control units, each rate control unit corresponding to one of the multiple parallel data queues.

[0023] Thirdly, the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the traffic scheduling method for wireless communication data paths of any of the foregoing embodiments.

[0024] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, performs a traffic scheduling method for a wireless communication data path according to any of the foregoing embodiments.

[0025] The present invention provides a method and apparatus for traffic scheduling of wireless communication data paths. The method includes: acquiring the current occupancy of the downstream hardware buffer in the data path and the target access category of the target data queue being transmitted; controlling the data transmission behavior of the upstream host driver using a hierarchical transmission strategy based on the relationship between the current occupancy and at least two water level levels corresponding to the target access category; monitoring the real-time occupancy of the host driver's transmission queue; and controlling the host driver to feed back flow control instructions to the upper-layer operating system based on the real-time occupancy. This treats the data path as a whole pipeline. By introducing multi-level water level levels and a hierarchical transmission strategy, combined with feedback based on real-time occupancy, smooth flow control and dynamic balance of the entire pipeline are achieved. Simultaneously, it eliminates the dependence on manual configuration and tuning of parameters such as queue depth at each level, achieving zero-configuration adaptive control. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 A flowchart illustrating a traffic scheduling method for a wireless communication data path provided in an embodiment of the present invention; Figure 2 A schematic diagram illustrating the dynamic balancing principle of a distributed multi-stage pipeline provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a traffic scheduling device for a wireless communication data path provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] This invention aims to address the inefficiency of a single multi-stage processing pipeline (Host Driver → DMA Channel → Firmware) in the data path of high-speed wireless communication (such as Wi-Fi 6), from the host to the firmware. Specifically, this invention aims to solve the following technical problems: How to dynamically schedule traffic for the three pipeline stations at different depths—the host driver send queue (Driver txq), the DMA descriptor queue (DMA DescriptorQueue), and the firmware processing buffer (FW Buffer)—as a whole in order to maximize the throughput of the entire pipeline.

[0030] How to avoid "pipeline bubbles" or "pipeline blockage" caused by mismatch in the processing capacity of each level of the pipeline, both of which will seriously reduce system performance.

[0031] How can we establish an adaptive mechanism that can automatically adjust and maintain the total amount of "in-flight packets" in the entire pipeline within an optimal dynamic range, thereby achieving seamless connection between stations without requiring manual configuration and tuning of the depth of queues at different levels for different platforms or scenarios?

[0032] In a system supporting Quality of Service (QoS) with multiple parallel, heterogeneous data streams, how can the aforementioned pipeline balancing mechanism be applied independently and differentiated to achieve the following: 1. Traffic isolation and differentiated service guarantee: Avoid low-priority high-traffic traffic (such as file download) affecting the performance of high-priority real-time traffic (such as voice calls).

[0033] 2. Maximize system aggregation performance: Apply the optimal pipeline management strategy for each traffic type (such as low latency and high throughput) to improve the overall performance of the entire system.

[0034] Based on this, the traffic scheduling method and apparatus for wireless communication data paths provided in this embodiment of the invention adopts a two-layer solution: 1. Core Mechanism: This method provides a dynamic balancing approach based on multi-level watermarks and graded responses for efficient management of single data pipelines. It treats the data path as a unified pipeline and achieves this by introducing multi-level watermarks and a graded response mechanism. Smooth Flow Control: Upgrades the coarse "go / stop" control to a refined four-level speed control of "acceleration / constant speed / deceleration / stop".

[0035] Automatic balancing: The system automatically finds and maintains an optimal total amount of "in-transit data packets", so that the entire pipeline is continuously and efficiently utilized, thereby maximizing end-to-end throughput.

[0036] Zero configuration: Eliminates the dependence on manual configuration and tuning of parameters such as queue depth at each level, achieving true self-adaptation.

[0037] 2. Distributed architecture: The core mechanism described above is used as the "engine". An engine is instantiated independently for each parallel pipeline in the system, and each engine can be configured with a set of heterogeneous control parameters that match its service goals.

[0038] To facilitate understanding of this embodiment, a traffic scheduling method for wireless communication data paths disclosed in this embodiment of the invention will first be described in detail.

[0039] This invention provides a traffic scheduling method for wireless communication data paths. This method can be executed by an electronic device at the host driver layer and can be applied to network interface cards (NICs) using PCIe (PCI Express). See also... Figure 1 The flowchart shown illustrates a traffic scheduling method for a wireless communication data path, which may include the following steps S110 to S140: Step S110: Obtain the current occupancy of the downstream hardware buffer in the data path and the target access category of the target data queue being transmitted.

[0040] The downstream hardware buffer mentioned above can be, but is not limited to, a DMA buffer. There can be one or more target data queues, and these queues can operate in parallel. Different data queues can have different access categories, or there can be two or more data queues with the same access category. The access category corresponds to the traffic type and can include various types such as voice (AC_VO), video (AC_VI), best-effort (AC_BE), and background (AC_BK). Background is used for background tasks, such as data backup and synchronization operations, which can tolerate higher latency and lower priority. Based on this, in some possible embodiments, the target data queue includes multiple parallel data queues, and the target access category includes one or more of voice, video, best-effort, and background.

[0041] Step S120: Based on the relationship between the current occupancy and the target access category corresponding to at least two water level levels, a hierarchical transmission strategy is adopted to control the data transmission behavior of the upstream host driver.

[0042] Two or more watermark levels are pre-configured for each access category. The watermark levels for different access categories can be the same or different. At least two watermark levels are configured based on the service objectives of the corresponding access category. The watermark level for the access category of low-latency flow is shallower than the watermark level for the access category of high-throughput flow. That is, for data queues aimed at achieving low latency, a shallower watermark level is configured; for data queues aimed at achieving high throughput, a deeper watermark level is configured.

[0043] In some possible embodiments, at least two water level levels may include a low water level and a high water level. The hardware buffer includes a DMA buffer. Based on the relationship between the DMA buffer occupancy in the data path and the preset low and high water levels, a selection from multiple transmission rates (at least including acceleration, constant speed, and deceleration) can be made to control the data transmission behavior of the upstream host driver. Therefore, step S120 may include: when the current occupancy is less than the low water level, controlling the host driver to acquire data from the corresponding data queue of its transmission queue at maximum capacity and submitting a DMA task to the DMA buffer; when the current occupancy is greater than or equal to the low water level and less than the high water level, controlling the host driver to submit a DMA task at a smooth and sustainable rate; when the current occupancy is greater than or equal to the high water level and less than the maximum capacity of the DMA buffer, controlling the host driver to reduce the transmission rate; and when the current occupancy is equal to the maximum capacity of the DMA buffer, controlling the host driver to stop submitting DMA tasks.

[0044] The specific values ​​of the low and high water levels can be set according to actual needs and are not limited here. For example, the low water level is 25% of the buffer capacity. If the buffer occupancy is below this level, it indicates that the downstream FW processing speed is very fast, and the pipeline is at risk of "flow interruption". The high water level is 75% of the buffer capacity. When the buffer occupancy is above this level, it indicates that downstream FW processing is starting to back up, and the pipeline is at risk of "blockage".

[0045] When the target data queue comprises multiple parallel data queues, this embodiment also provides distributed and differentiated management: each data queue in the multiple parallel data queues independently executes step S120. Specifically, a rate control unit can be independently instantiated for each data queue, so that the data flow of each data queue is managed by an independent rate control unit. Different multi-level watermarks can be configured for at least two of the multiple data queues.

[0046] Step S130: Monitor the real-time occupancy of the host driver's send queue.

[0047] Step S140: Based on the real-time occupancy, control the host driver to send flow control instructions to the upper-level operating system.

[0048] Considering the persistently slow FW (Server Controller), which causes data packets to accumulate in the txq (Transfer Queue) and consume a large amount of host memory, this embodiment also provides a second feedback loop: monitoring the host driver's own state to provide feedback upstream (i.e., the Operating System, OS). Specifically, the occupancy of the sending queue within the host driver can be monitored, and when it exceeds a preset threshold, pressure is applied to the upper-layer operating system. This monitoring and pressure mechanism is also executed independently for each parallel data queue.

[0049] In some possible embodiments, step S140 above may include: controlling the host driver to send a pause or resume sending command to the operating system based on the relationship between the real-time occupancy and preset high and low thresholds.

[0050] In one possible implementation, when the real-time usage exceeds a high threshold, the host driver calls the corresponding interface of the operating system to suspend the delivery of data packets from the upper-layer network protocol stack to the host driver; when the real-time usage falls back below the low threshold, the host driver calls the corresponding interface of the operating system to notify the operating system to resume sending data packets.

[0051] It should be noted that there is no specific order of execution between steps S110 to S120 and steps S130 to S140; they can be executed simultaneously.

[0052] The wireless communication data path traffic scheduling method provided in this embodiment of the invention treats the data path as a whole pipeline. By introducing multi-level water level lines and hierarchical transmission strategies, combined with feedback based on real-time occupancy, it achieves smooth flow control and dynamic balance of the entire pipeline. At the same time, it eliminates the dependence on manual configuration and optimization of parameters such as queue depth at each level, and achieves zero-configuration adaptiveness.

[0053] For ease of understanding, please refer to the following: Figure 2 The above methods will be described in detail.

[0054] The distributed multi-stage pipeline dynamic balancing system applied in this embodiment of the invention may include: Multiple parallel hardware data channels (such as DMA channels).

[0055] Multiple independent rate control modules, each associated with a hardware data channel, are configured for the aforementioned traffic scheduling method for wireless communication data paths.

[0056] A strategy configuration module is used to set different multi-level water level lines for at least two of a plurality of rate control modules.

[0057] like Figure 2 As shown, the distributed multi-stage pipeline dynamic balancing system applied in this embodiment of the invention involves an operating system protocol stack (OS Net Stack), a driver transmit queue (driver txq), a dynamic rate control module, and a Wi-Fi SOC chip. The dynamic rate control module communicates with the Wi-Fi SOC chip via a bus (PCIe). The Wi-Fi SOC chip includes a DMA controller / channel, a firmware buffer (FW buffer), and a firmware data processing module. The DMA controller / channel includes a DMA ring buffer. Data flows from the operating system protocol stack, through the driver transmit queue and the dynamic rate control module, and then through the bus to the Wi-Fi SOC chip. Within the Wi-Fi SOC chip, it passes through the DMA controller / channel and the firmware buffer, finally reaching the firmware data processing module. The operating system protocol stack can be paused and resumed, and the driver transmit queue is configured with different H / L levels for different txqs. The dynamic rate control module consists of multiple independently instantiated dynamic rate control modules, which operate in parallel, independently, and without interference.

[0058] The solution of this invention is divided into two levels: core mechanism and distributed application, which will be described in detail below.

[0059] I. Core Mechanism: Dynamic Balance of a Single Pipeline.

[0060] The core idea of ​​this invention is to set up multiple water level lines at key pipeline stations (depth of DMA queue) and allow the upstream station (Driver) to adopt different, graded transmission strategies according to the downstream water level status, while monitoring its own status to provide feedback to the upstream (OS), thereby achieving dynamic balance of the entire pipeline.

[0061] The workflow is described in detail below: 1. Set up multiple watermarks: Logically define at least two watermarks within the critical, shallower second-stage pipeline station – the DMA circular buffer: Low Watermark (L_WM): For example, 25% of the buffer capacity. When the buffer occupancy is below this level, it indicates that the downstream FW processing speed is very fast, and there is a risk of "flow interruption" in the pipeline.

[0062] High Watermark (H_WM): for example, 75% of the buffer capacity. When the buffer occupancy is above this watermark, it indicates that processing at the downstream FW starts to pile up, and the pipeline is at risk of "blocking".

[0063] 2. Graded transmission strategy of the driver (Feedback Loop 1): The transmission control module of the driver no longer simply checks "full / not full", but checks which interval the current occupancy DMA_level of the DMA circular buffer falls into, and adopts a corresponding transmission strategy: 2.1 Aggressive Zone - DMA_level < L_WM: Status: The downstream is extremely "starved", and bubbles are about to appear in the pipeline.

[0064] Strategy: The driver fetches packets from the txq for transmission and submits DMA tasks at its maximum capacity, with the purpose of quickly filling the downstream and preventing the FW from being idle.

[0065] 2.2 Steady Zone - L_WM ≤ DMA_level < H_WM: Status: The pipeline is in a healthy, balanced and ideal state.

[0066] Strategy: The driver submits DMA tasks at a stable and sustainable rate, for example, processing one standard-sized batch each time. This is the optimal working interval.

[0067] 2.3 Throttling Zone - H_WM ≤ DMA_level < FULL (i.e. the maximum capacity of the aforementioned DMA buffer): Status: The downstream begins to "indigestion" and shows signs of congestion.

[0068] Strategy: The driver actively reduces the transmission rate. This can be achieved by reducing the size of transmission batches, or introducing a tiny delay between transmission batches. The purpose is to "gently" reduce the pressure on the downstream and avoid blocking caused by impact.

[0069] 2.4 Stop Zone - DMA_level == FULL: Status: The downstream is completely blocked.

[0070] Strategy: The driver completely stops submitting tasks to the DMA and waits for interrupt wakeup. This serves as the final safeguard measure.

[0071] 3. Upstream Backpressure Propagation (Feedback Loop 2): The above strategy solves the pipeline balancing from txq to FW. However, if the FW remains slow, packets will accumulate in txq, consuming a large amount of host memory. Therefore, a second feedback loop is needed: The driver also monitors the depth of its own TXQ; When the depth of txq exceeds a preset high watermark (i.e., the aforementioned high threshold) due to continuous deceleration or cessation of downstream (DMA) processes, the driver invokes an operating system interface (such as netif_stop_queue in Linux) to suspend the delivery of data packets from the upper-layer network protocol stack to the driver. This achieves a step-by-step propagation of backpressure signals from hardware (DMA) → driver (txq) → operating system (Net Stack), fundamentally controlling the total amount of data entering the entire pipeline and preventing unnecessary consumption of host memory.

[0072] When the txq depth falls below the low watermark, the driver calls the corresponding interface (netif_wake_queue) to notify the operating system to resume packet delivery.

[0073] Through these two layers of feedback loops and hierarchical control, the system can automatically maintain the total amount of "in-transit data packets" (txq + DMARing + FW Buffer) at a dynamically optimal level, thereby achieving self-balancing and efficient operation of the entire pipeline.

[0074] II. Distributed Architecture: Differentiated Management of Multiple Pipelines

[0075] This invention applies the core mechanism described above to a system with multiple parallel queues to achieve distributed and differentiated management.

[0076] 1. Independent instantiation: Each AC's data stream is managed by a separate rate control module instance. For example: The Dynamic Rate Control Module (AC_VO) only monitors the status of the DMA Channel (AC_VO) and only uses the shallow waterline threshold configured for AC_VO to execute the graded transmission strategy of "acceleration / constant speed / deceleration".

[0077] The Dynamic Rate Control Module (AC_BE) only monitors the status of the DMA Channel (AC_BE) and only uses the deep water threshold configured for AC_BE to execute its hierarchical strategy.

[0078] Two (or more) dynamic rate control modules operate in parallel, independently, and without interference.

[0079] 2. Heterogeneous parameter configuration: Allows configuring a different set of water level thresholds for each instance that match its service objectives.

[0080] Example 1: Low-latency stream (AC_VO).

[0081] Configure a set of shallow water level thresholds, such as L_WM_VO=10% and H_WM_VO=40%.

[0082] Effect: By forcing the number of data packets in the DMA queue to remain at a very low level, hardware queuing latency is greatly reduced, ensuring the quality of voice calls.

[0083] Example 2: High throughput stream (AC_BE).

[0084] Configure a set of deeper water level thresholds, such as L_WM_BE=40% and H_WM_BE=85%.

[0085] Effects: Allows the driver to accumulate more data packets in the software for aggregation and batch processing, and continuously injects large amounts of data into the hardware, maximizing link utilization and file download speed.

[0086] In summary, the key points of the embodiments of the present invention include: 1. Core balancing mechanism: A dynamic balancing method for a single flowline based on multi-level water level lines and graded responses.

[0087] 1.1 Pipeline overall optimization concept: Treat the data path as a multi-level pipeline as a whole, rather than an isolated interface. The optimization goal is the balance and throughput of the entire pipeline.

[0088] 1.2 Multi-level water level and graded response: The core mechanism is to achieve fine and smooth regulation of flow by setting multiple thresholds in the buffer zone, rather than the crude "go / stop" control.

[0089] 1.3 Dual feedback loop: There is not only feedback from hardware to driver, but also feedback from driver to operating system, realizing end-to-end traffic adaptation.

[0090] 2. Distributed application architecture: The core balancing mechanism is applied independently to multiple parallel data queues.

[0091] 3. Heterogeneous strategy configuration: Configure different control parameters (especially water level thresholds) for different data queues to achieve differentiated services.

[0092] Compared with existing "timer schemes" and "single-point binary reverse pressure schemes", the embodiments of the present invention have the following advantages: 1. From “interface flow control” to “pipeline optimization”: Existing technologies only solve the point-to-point congestion problem, while the solution of this invention optimizes the flow efficiency of the entire data path, which can significantly reduce pipeline idleness and congestion, thereby achieving higher average throughput and more stable low latency.

[0093] 2. From “coarse-grained control” to “fine-grained adjustment”: The embodiments of the present invention use a smooth “gearbox” instead of a rough “switch” to avoid data stream jitter, so that the firmware can receive a more stable and predictable data stream, which is conducive to the execution of its internal scheduling algorithm and further improves wireless performance.

[0094] 3. From "Reactive Response" to "Proactive Prediction": The high-water mark mechanism enables the drive to "anticipate" impending congestion and slow down in advance, rather than passively stopping only after complete blockage. This is a more proactive and intelligent form of congestion management, improving the system's responsiveness and robustness.

[0095] 4. Achieves true "zero-configuration adaptive" performance: Through a dynamic balancing mechanism, it automatically finds the optimal operating point, completely eliminating the need for manual tuning of queue depths, timer parameters, etc. This allows the driver to approach its optimal performance under different hardware platforms and network loads, greatly reducing adaptation and maintenance costs.

[0096] 5. Achieved true QoS guarantee: By providing tailored and isolated pipeline management for different ACs, the problem of interference between traffic is fundamentally solved, ensuring the performance of high-priority applications.

[0097] 6. Maximize overall system performance: By ensuring that each pipeline operates in its optimal mode, the system's aggregate throughput and overall user experience are maximized, rather than making mediocre compromises among all traffic types.

[0098] 7. Clear architecture and strong scalability: The "core mechanism + distributed architecture" design makes the solution logically clear, easy to implement and extend. When adding new queue types in the future, only a new set of parameters needs to be configured for them, without modifying the core algorithm.

[0099] Corresponding to the traffic scheduling method for wireless communication data paths described above, this embodiment of the invention also provides a traffic scheduling device for wireless communication data paths. See also... Figure 3 The diagram shows a traffic scheduling device for a wireless communication data path. The device includes: The transmission control module 301 is used to obtain the current occupancy of the downstream hardware buffer in the data path and the target access category of the target data queue being transmitted, and to control the data transmission behavior of the upstream host driver according to the relationship between the current occupancy and the target access category corresponding to at least two water level lines. The feedback control module 302 is used to monitor the real-time occupancy of the host driver's send queue and, based on the real-time occupancy, control the host driver to send flow control commands to the upper-layer operating system.

[0100] The wireless communication data path flow scheduling device provided in this embodiment of the invention treats the data path as a whole pipeline. By introducing multi-level water level lines and hierarchical transmission strategies, combined with feedback based on real-time occupancy, it achieves smooth flow control and dynamic balance of the entire pipeline. At the same time, it eliminates the dependence on manual configuration and optimization of parameters such as queue depth at each level, and achieves zero-configuration adaptiveness.

[0101] Furthermore, the aforementioned at least two water level levels include a low water level and a high water level, and the hardware buffer includes a DMA buffer; the aforementioned transmission control module 301 is specifically used to: when the current occupancy is less than the low water level, control the host driver to acquire data from the corresponding data queue of its transmission queue at maximum capacity, and submit a DMA task to the DMA buffer; when the current occupancy is greater than or equal to the low water level and less than the high water level, control the host driver to submit a DMA task at a smooth and sustainable rate; when the current occupancy is greater than or equal to the high water level and less than the maximum capacity of the DMA buffer, control the host driver to reduce the transmission rate; when the current occupancy is equal to the maximum capacity of the DMA buffer, control the host driver to stop submitting DMA tasks.

[0102] Furthermore, the aforementioned target data queue includes multiple parallel data queues, and the target access category includes one or more of voice, video, best-effort, and background; the aforementioned transmission control module 301 includes multiple independent rate control units, each rate control unit corresponding to one of the multiple parallel data queues.

[0103] Furthermore, the aforementioned at least two water level levels are configured based on the service objectives of the corresponding access categories; the water level corresponding to the access category of low-latency flows is shallower than the water level corresponding to the access category of high-throughput flows.

[0104] Furthermore, the aforementioned feedback control module 302 is specifically used to: control the host driver to send a pause or resume sending command to the operating system based on the relationship between the real-time occupancy and the preset high and low thresholds.

[0105] Furthermore, the aforementioned feedback control module 302 is also used to: when the real-time occupancy exceeds a high threshold, control the host driver to call the corresponding interface of the operating system to suspend the upper-layer network protocol stack from delivering data packets to the host driver; when the real-time occupancy falls below a low threshold, control the host driver to call the corresponding interface of the operating system to notify the operating system to resume sending data packets.

[0106] The traffic scheduling device for wireless communication data paths provided in this embodiment has the same implementation principle and technical effects as the aforementioned traffic scheduling method embodiment for wireless communication data paths. For the sake of brevity, any parts not mentioned in the traffic scheduling device embodiment for wireless communication data paths can be referred to the corresponding content in the aforementioned traffic scheduling method embodiment for wireless communication data paths.

[0107] like Figure 4 As shown, an electronic device 400 provided in this embodiment of the invention includes: a processor 401, a memory 402 and a bus. The memory 402 stores a computer program that can run on the processor 401. When the electronic device 400 is running, the processor 401 and the memory 402 communicate through the bus. The processor 401 executes the computer program to implement the above-mentioned traffic scheduling method for wireless communication data paths.

[0108] Specifically, the memory 402 and processor 401 mentioned above can be general-purpose memory and processor, without any specific limitations here.

[0109] This invention also provides a computer-readable storage medium storing a computer program. When a processor executes the computer program, it performs the traffic scheduling method for wireless communication data paths described in the preceding method embodiments. The computer-readable storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), RAM, a magnetic disk, or an optical disk.

[0110] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0111] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0112] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interface; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0114] The modules described as separate components may or may not be physically separate. Similarly, the components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0115] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A traffic scheduling method for a wireless communication data path, characterized in that, The traffic scheduling method for the wireless communication data path is executed by an electronic device in the host driver layer, including: Obtain the current occupancy of downstream hardware buffers in the data path and the target access category of the target data queue currently being transmitted; Based on the relationship between the current occupancy and at least two water level lines corresponding to the target access category, a hierarchical transmission strategy is adopted to control the data transmission behavior of the upstream host driver. Monitor the real-time occupancy of the host driver's send queue; Based on the real-time occupancy, the host driver is controlled to send flow control instructions to the upper-layer operating system; The at least two water level levels include a low water level and a high water level, and the hardware buffer includes a DMA buffer. The step of controlling the data transmission behavior of the upstream host driver using a tiered transmission strategy based on the relationship between the current occupancy and the at least two water level levels corresponding to the target access category includes: when the current occupancy is less than the low water level, controlling the host driver to acquire data from the corresponding data queue of its transmission queue at maximum capacity and submitting a DMA task to the DMA buffer; when the current occupancy is greater than or equal to the low water level and less than the high water level, controlling the host driver to submit a DMA task at a stable and sustainable rate; when the current occupancy is greater than or equal to the high water level and less than the maximum capacity of the DMA buffer, controlling the host driver to reduce the transmission rate; and when the current occupancy is equal to the maximum capacity of the DMA buffer, controlling the host driver to stop submitting DMA tasks.

2. The traffic scheduling method for wireless communication data paths according to claim 1, characterized in that, The target data queue includes multiple parallel data queues, and the target access category includes one or more of voice, video, best-effort, and background. Each of the multiple parallel data queues independently executes the step of controlling the data transmission behavior driven by the upstream host using a hierarchical transmission strategy based on the relationship between the current occupancy and at least two water level levels corresponding to the target access category.

3. The traffic scheduling method for wireless communication data paths according to claim 1, characterized in that, The at least two water level levels are configured based on the service target of the corresponding access category; the water level corresponding to the access category of low-latency flow is shallower than the water level corresponding to the access category of high-throughput flow.

4. The traffic scheduling method for wireless communication data paths according to claim 1, characterized in that, The step of controlling the host driver to feed back flow control instructions to the upper-layer operating system based on the real-time occupancy includes: Based on the relationship between the real-time occupancy and preset high and low thresholds, the host driver is controlled to send a pause or resume transmission command to the operating system.

5. The traffic scheduling method for wireless communication data paths according to claim 4, characterized in that, The step of controlling the host driver to send a pause or resume transmission command to the operating system based on the relationship between the real-time occupancy and preset high and low thresholds includes: When the real-time occupancy exceeds the high threshold, the host driver is controlled to call the corresponding interface of the operating system to suspend the upper-layer network protocol stack from delivering data packets to the host driver. When the real-time usage drops below the low threshold, the host driver is controlled to call the corresponding interface of the operating system to notify the operating system to resume sending data packets.

6. A traffic scheduling device for a wireless communication data path, characterized in that, The traffic scheduling device for the wireless communication data path is implemented by an electronic device in the host driver layer, including: The transmission control module is used to obtain the current occupancy of the downstream hardware buffer in the data path and the target access category of the target data queue being transmitted, and to control the data transmission behavior of the upstream host driver according to the relationship between the current occupancy and the target access category corresponding to at least two water level lines, using a hierarchical transmission strategy. The feedback control module is used to monitor the real-time occupancy of the host driver's sending queue, and control the host driver to send flow control instructions to the upper-layer operating system based on the real-time occupancy. The at least two water level levels include a low water level and a high water level, and the hardware buffer includes a DMA buffer. The transmission control module is specifically configured to: when the current occupancy is less than the low water level, control the host driver to acquire data from the corresponding data queue of its transmission queue at maximum capacity and submit a DMA task to the DMA buffer; when the current occupancy is greater than or equal to the low water level and less than the high water level, control the host driver to submit DMA tasks at a smooth and sustainable rate; when the current occupancy is greater than or equal to the high water level and less than the maximum capacity of the DMA buffer, control the host driver to reduce the transmission rate; and when the current occupancy is equal to the maximum capacity of the DMA buffer, control the host driver to stop submitting DMA tasks.

7. The traffic scheduling device for wireless communication data paths according to claim 6, characterized in that, The target data queue includes multiple parallel data queues; the transmission control module includes multiple independent rate control units, each of which corresponds to one of the multiple parallel data queues.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor executes the computer program, it implements the traffic scheduling method for the wireless communication data path according to any one of claims 1-5.

9. A computer-readable storage medium storing a computer program thereon, characterized in that, When the computer program is run by the processor, it executes the traffic scheduling method for the wireless communication data path according to any one of claims 1-5.

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