A depletion-mode gallium nitride chip, its fabrication method, and cascaded packaging device.

Abstract

This invention belongs to the field of semiconductor technology, specifically disclosing a depletion-mode gallium nitride (GaN) chip, its fabrication method, and a cascaded packaging device. The GaN chip includes a gate electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a first field plate unit comprising at least two field plates. The first field plate unit is at least partially located between the second and third dielectric layers. The gate electrode is located at the end of the first field plate unit near the source electrode and between the third dielectric layer and the stacked structure. Along a horizontal direction parallel to the substrate length, the first dielectric layer, the second dielectric layer, the gate electrode, and the first field plate unit are all located between the source electrode ohmic metal and the drain electrode ohmic metal. The source electrode ohmic metal, the gate electrode, and the first field plate unit are disposed on the same layer. The GaN chip of this invention simplifies the process while allowing multiple field plates to be formed on a single dielectric layer, resulting in better chip flatness and enabling the packaged device to be better applied in circuits.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a depletion-type gallium nitride chip and a cascaded package device including the depletion-type gallium nitride chip. Background Technology

[0002] In existing technologies, lateral devices, such as GaN HEMTs (High Electron Mobility Transistors), often employ a multi-field plate structure to weaken excessively strong electric field peaks. Typically, there are 1-4 field plates, all connected to the gate, all connected to the source, or partially connected to the gate while the remaining portion connects to the source. The field plates are stepped, with the height of the lower surface gradually increasing from the gate to the drain.

[0003] The above-mentioned methods for forming field plates mainly include the following three approaches: 1) etching multiple steps into the dielectric layer and filling with metal in one step to form the field plate; 2) alternating deposition of the dielectric layer and deposited metal to form a multilayer metal field plate; 3) etching large slopes into the dielectric layer and filling with metal in one step to form the field plate. The main problem with the first approach is that if the etching depth is determined by time, it is difficult to control the depth precisely, leading to large differences in electric field distribution and affecting reliability. If the etching depth is controlled by using different materials in the dielectric layer and utilizing the difference in etching selectivity, the etching selectivity will not be very large for dielectrics with similar materials such as SiN and SiO2, resulting in a certain risk in step control. For dielectrics with very different materials, such as SiN and Al2O3, AlN, multiple equipment is often required, resulting in high production costs. The main problem with the second approach is that it requires multiple metal processing steps, and the multi-layer metal field board needs vias for interconnection. The interconnection size is relatively limited, affecting the channel length and thus the chip's resistance. If interconnection is only done at the ends of the cells, although the area affected will be reduced, it will lead to a higher metal resistance of the field board and slower charging and discharging. The main problem with the third approach is that the large-scale beveled field board process is inherently difficult to control precisely and stably, making it difficult to guarantee process consistency and thus affecting reliability.

[0004] With the increasing market demand for power devices such as GaN HEMT, the industry urgently needs to develop stable, reliable, and cost-effective field board solutions. Summary of the Invention

[0005] In view of this, in order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a depletion-type gallium nitride chip and its fabrication method, as well as a cascaded packaging device, which can simplify the process while forming a multilayer field plate on a single dielectric layer and obtaining a chip with better flatness, so that the packaged device can be better applied in circuits.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention provides a depletion-mode gallium nitride (GaN) chip, comprising a source electrode, a drain electrode, a gate electrode, and a substrate and a stacked structure arranged sequentially from bottom to top. The GaN chip further includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a first field plate unit. The first dielectric layer is located on the side of the stacked structure away from the substrate. The source electrode and drain electrode are both located on the side of the third dielectric layer away from the substrate. The first field plate unit comprises at least two field plates, with at least a portion of the first field plate unit located between the second and third dielectric layers. The gate electrode is located at the end of the first field plate unit near the source electrode and is located between the third dielectric layer and the stacked structure, extending parallel to the substrate length. In the horizontal direction of the degree direction, the first dielectric layer, the second dielectric layer, the gate electrode, and the first field plate unit are all located between the source electrode ohmic metal and the drain electrode ohmic metal. Part of the bottom surface of the second dielectric layer and part of the bottom surface of the third dielectric layer are flush with the bottom surface of the first dielectric layer. This arrangement makes the gate trench corresponding to the gate electrode of the present invention different from the traditional complete gate trench. The present invention eliminates the part of the gate trench located between the source electrode ohmic metal and the gate electrode (the remaining part of the gate trench is the single-sided gate trench in the present invention), which is beneficial to improve resistance and makes the source electrode ohmic metal and the gate electrode flatter. It also greatly improves the filling gap of the top dielectric layer (reducing or eliminating it).

[0008] The stacked structure also has a source electrode ohmic metal and a drain electrode ohmic metal on the side away from the substrate. The source electrode is located above the source electrode ohmic metal, and the drain electrode is located above the drain electrode ohmic metal. The source electrode ohmic metal, the drain electrode ohmic metal, the gate electrode and the first field plate unit are disposed on the same layer.

[0009] By placing the source electrode ohmic metal, drain electrode ohmic metal, gate electrode, and first field plate unit in the same layer, and simultaneously forming the first field plate unit with at least two field plates on the second dielectric layer, the process flow is greatly simplified and production efficiency is improved. In addition, along the horizontal direction parallel to the substrate length direction, the first dielectric layer, the second dielectric layer, the gate electrode, and the first field plate unit are all located between the source electrode ohmic metal and the drain electrode ohmic metal. That is, there is no high step formed by dielectric layer between the gate electrode of the present invention and its adjacent source electrode ohmic metal, which makes the chip flatter and the area required to form the same resistance value smaller. The bottom surface of the upper end of the source electrode ohmic metal of the present invention is in direct contact with the capping layer of the stacked structure, without the presence of an additional dielectric layer. This reduces the vertical distance between the bottom of the source electrode ohmic metal and the two-dimensional electron gas below it. When the device is under extreme short-circuit conditions, the device is conductive, and there is a large and uniformly distributed potential difference between the drain electrode and the source electrode. This allows the bottom surface of the upper end of the source electrode ohmic metal and the two-dimensional electron gas below it to be in a semi-off state under relatively small voltage, making it less prone to short circuits.

[0010] According to some preferred embodiments of the present invention, the stacked structure includes a nucleation layer, a buffer layer, a channel layer, a barrier layer and a capping layer arranged sequentially from bottom to top, wherein the tops of the source electrode ohmic metal and the drain electrode ohmic metal are both located on the capping layer, and the bottoms of the source electrode ohmic metal and the drain electrode ohmic metal are both located in the barrier layer, and the bottom surface of the first dielectric layer is in contact with a portion of the top surface of the capping layer.

[0011] According to some preferred embodiments of the present invention, the first field plate unit includes a first field plate, a second field plate, and a third field plate, with one end of the first field plate connected to one end of the gate electrode; along a horizontal direction parallel to the substrate length direction, the second field plate is located between the first field plate and the third field plate; along a vertical direction, both the first field plate and the third field plate are located between a second dielectric layer and a third dielectric layer, with the second field plate located between the first dielectric layer and the third dielectric layer. In some embodiments of the present invention, the first field plate unit also includes three field plates, which are, from bottom to top, a first field plate, a second field plate, and a third field plate. Since the three field plates are interconnected, their potentials are equal, that is, the potential of the first field plate at high voltage equilibrium is equal to the potential of the second field plate at high voltage equilibrium, and also equal to the potential of the third field plate at high voltage equilibrium.

[0012] According to some preferred embodiments of the present invention, the bottom of the second field plate is located within a first dielectric layer, and the thickness of the first dielectric layer is greater than the sum of the thickness of the second dielectric layer and the thickness of the portion of the second field plate located within the first dielectric layer, to ensure that the height from the bottom surface of the formed second field plate to the capping layer is greater than the height from the bottom surface of the first field plate to the capping layer; the distance from the bottom surface of the first field plate to the capping layer is less than the distance from the bottom surface of the second field plate to the capping layer, and the distance from the bottom surface of the second field plate to the capping layer is less than the distance from the bottom surface of the third field plate to the capping layer. This design satisfies the requirement that the potential of the two-dimensional electron gas directly below the first field plate at high voltage equilibrium is less than the potential of the two-dimensional electron gas directly below the second field plate at high voltage equilibrium, and the potential of the two-dimensional electron gas directly below the second field plate at high voltage equilibrium is less than the potential of the two-dimensional electron gas directly below the third field plate at high voltage equilibrium. In other embodiments of the present invention, the first field plate unit may also be configured to include only two field plates, namely, the first field plate unit includes a fourth field plate and a fifth field plate, one end of the fourth field plate is connected to one end of the gate electrode, and the top of the end of the fourth field plate away from the gate electrode is connected to the bottom of the end of the fifth field plate away from the drain electrode; in the vertical direction, both the fourth and fifth field plates are located between the second and third dielectric layers. Furthermore, the distance from the bottom surface of the fourth field plate to the capping layer is less than the distance from the bottom surface of the fifth field plate to the capping layer, wherein the potential of the fourth field plate at high voltage equilibrium is equal to the potential of the fifth field plate at high voltage equilibrium, and the potential of the two-dimensional electron gas directly below the fourth field plate at high voltage equilibrium is less than the potential of the two-dimensional electron gas directly below the fifth field plate at high voltage equilibrium. Preferably, the thickness of the portion of the second field plate located in the first dielectric layer accounts for 30%-40% of the thickness of the second dielectric layer. In addition, in some embodiments of the present invention, the thickness of the first dielectric layer is 100-400 nm, and the thickness of the second dielectric layer is 75-310 nm.

[0013] According to some preferred embodiments of the present invention, the first field plate unit includes a connecting portion located above the first field plate and the second field plate and at the same horizontal height as the third field plate. The two ends of the bottom of the connecting portion are respectively connected to the first field plate and the second field plate, and the top end of the second field plate near the drain electrode is connected to the third field plate.

[0014] According to some preferred embodiments of the present invention, the top surface of the gate electrode near the source electrode is flush with the top surface of the source electrode ohmic metal, and there is a gap between the end of the gate electrode near the source electrode and the end of the source electrode ohmic metal near the gate electrode; along a horizontal direction parallel to the length of the substrate, the second dielectric layer is located between the gate electrode and the drain electrode ohmic metal, and the bottom end of the gate electrode away from the source electrode is connected to one end of the second dielectric layer.

[0015] According to some preferred embodiments of the present invention, the source electrode ohmic metal, the drain electrode ohmic metal, the gate electrode, and the first field plate unit all include a bottom metal layer and a top metal layer disposed sequentially from bottom to top. The thickness of the bottom metal layer is less than the thickness of the top metal layer, and the thickness ratio of the bottom metal layer to the top metal layer is 1:30-50. The top metal layer mainly serves as a metal interconnect, and has characteristics such as low resistivity and good conductivity. The top metal layer includes, but is not limited to, Al, Cu, or aluminum-copper alloys. The bottom metal layer mainly serves as an isolation layer and an adhesion layer, used to isolate the metal layer from the dielectric layer to prevent diffusion between the metal layer and the dielectric layer, and to improve the adhesion between the metal and the underlying layer. The bottom metal layer includes, but is not limited to, Ti or TiN.

[0016] According to some preferred embodiments of the invention, a second field plate unit is further included, the top of which is located above the third dielectric layer, the bottom of which is located in the third dielectric layer, and the bottom of which is connected to the top of the first field plate unit near the drain electrode. In some embodiments of the invention, when the first field plate unit is configured to include a first field plate, a second field plate, and a third field plate, the bottom of the second field plate unit is connected to the top surface of the third field plate near the drain electrode. In other embodiments of the invention, when the first field plate unit is configured to include only a fourth and a fifth field plate, and the depletion-mode gallium nitride chip also includes a second field plate unit, the top of the second field plate unit is located above the third dielectric layer, the bottom of which is located in the third dielectric layer, and the bottom of which is connected to the top surface of the fifth field plate near the drain electrode.

[0017] This invention also provides a cascaded packaged device, comprising the depletion-mode gallium nitride (GaN) chip as described above. The cascaded packaging of the GaN chip and the enhancement-mode MOS chip of this invention achieves a smaller package footprint and a smaller package size. Due to the good flatness of the chip, metal electrodes of the same thickness can withstand thicker wire diameters, allowing for greater current. The cascaded packaged device is obtained by cascading the GaN chip and the enhancement-mode MOS chip. Devices based on the above-described GaN chip package have a smaller chip area, lower parasitic capacitance, and faster switching speed; when applied in circuits, the device can meet higher frequencies, higher efficiency, and smaller size requirements.

[0018] The present invention also provides a method for fabricating a depletion-mode gallium nitride chip, the method being used to fabricate a depletion-mode gallium nitride chip with a first field plate unit including a first field plate, a second field plate, and a third field plate, the method comprising the following steps:

[0019] After growing a stacked structure on the substrate, a first dielectric layer is first grown on the top surface of the stacked structure, and a first step is formed by wet etching.

[0020] A second dielectric layer is grown on the first step, and a second step and a one-sided gate trench are formed by wet etching. A third step is formed by dry etching, and the one-sided gate trench is located near the end of the second step and away from the third step.

[0021] Source electrode ohmic metal and drain electrode ohmic metal are formed on the stacked structure, and a gate electrode is formed in a single-sided gate trench and a first field plate unit is formed on the second dielectric layer. The gate electrode is close to the end of the second dielectric layer away from the drain electrode ohmic metal.

[0022] Finally, a third dielectric layer is grown, forming the source and drain electrodes. Specifically, after growing the third dielectric layer, source and drain electrode vias are etched, metal is grown, and then patterned to form the source and drain electrodes.

[0023] According to some preferred embodiments of the present invention, the method of forming source electrode ohmic metal and drain electrode ohmic metal on a stacked structure, while forming a gate electrode in a single-sided gate trench and forming a first field plate unit on a second dielectric layer is as follows:

[0024] Source electrode ohmic holes and drain electrode ohmic holes are formed by etching downwards from the top surface of the stacked structure. Metal is then grown and patterned to form source electrode ohmic metal, drain electrode ohmic metal, gate electrode, and first field plate unit. A high-temperature annealing furnace is then used to anneal the wafer so that the heat source is applied from the substrate surface (equivalent to the back side of the wafer), allowing the source electrode ohmic metal and drain electrode ohmic metal to form ohmic contacts with the two-dimensional electron gas below them. In some embodiments of the present invention, the gate electrode, the first field plate unit, the source electrode ohmic metal, and the drain electrode ohmic metal are on the same layer and undergo the same high-temperature annealing. During high-temperature annealing, diffusion at the interface between the gate electrode and the first field plate unit and the underlying dielectric layer can occur, causing anomalies. Therefore, in this invention, one solution is to use a high-temperature annealing furnace so that the heat source is mainly applied from the wafer substrate surface, and the temperature is gradually transferred upwards through the substrate side. Both the source electrode ohmic metal and the drain electrode ohmic metal are directly connected to the underlying semiconductor layer (barrier layer) through their respective ohmic holes, resulting in better thermal conductivity. Compared to the source electrode ohmic metal and drain electrode ohmic metal, the gate electrode and the first field plate unit have an additional first dielectric layer and a second dielectric layer underneath. The dielectric layer has poor thermal conductivity, which means that the gate electrode and the first field plate unit experience a lower temperature under the same annealing conditions, effectively solving the diffusion phenomenon between them and the dielectric below.

[0025] According to some preferred embodiments of the present invention, the method of forming source electrode ohmic metal and drain electrode ohmic metal on a stacked structure, while forming a gate electrode in a single-sided gate trench and forming a first field plate unit on a second dielectric layer is as follows:

[0026] The wafer is etched downwards from the top surface of the stacked structure to form source electrode ohmic vias and drain electrode ohmic vias. A first annealing is then performed on the wafer, followed by metal re-growth and patterning to form source electrode ohmic metal, drain electrode ohmic metal, gate electrode, and first field plate unit. A second annealing is then performed to allow the source electrode ohmic metal and drain electrode ohmic metal to form ohmic contacts with the two-dimensional electron gas below them. In some embodiments of the present invention, to address the diffusion problem between the gate electrode and the first field plate unit and the underlying dielectric layer caused by high-temperature annealing, another optional approach is to perform a first annealing on the wafer before metal growth to improve the quality of the dielectric layer below the gate electrode and the first field plate unit; and then perform conventional annealing for ohmic contacts again after metal growth, thereby improving the diffusion phenomenon between the gate electrode and the first field plate unit and the underlying dielectric layer. In this step, both the first and second annealing are conventional annealing processes, typically with the heat source applied from the front side of the wafer.

[0027] Specifically, during the metal growth process, the metal grown above the second step forms the first field plate, the metal grown on the third step forms the connection part, and when the second dielectric layer is patterned by dry etching, the second dielectric layer on the side near the third step away from the source electrode will be over-etched, that is, a part of the first dielectric layer below the second dielectric layer will be etched away. As a result, the second field plate formed by the metal grown on the second dielectric layer will be partially located in the first dielectric layer.

[0028] According to some preferred embodiments of the present invention, in the step of forming the source electrode ohmic metal, drain electrode ohmic metal, gate electrode and first field plate unit through patterning processing, the patterning processing method is metal lift-off. When patterning metal, if conventional dry etching process is used, it will cause severe material damage to the etched area. In conventional processes, sacrificial layers are grown in advance in areas where the etched area has high damage requirements to avoid damage to critical interfaces. However, the gate trench in the present invention is designed to be single-sided, that is, there is no high step formed by dielectric layer between the source electrode ohmic hole and the single-sided gate trench. This makes the metal etching position in this area an epitaxial capping layer. Damage in this area affects the performance and reliability of the device. Therefore, to solve this problem, the present invention provides an optional method of using metal lift-off process to avoid etching damage in this area.

[0029] This invention also provides another method for fabricating a depletion-mode gallium nitride (GaN) chip. The method is used to fabricate a GaN chip with a first field plate unit comprising a first field plate, a second field plate, and a third field plate. The fabrication method includes the following steps:

[0030] After growing a stacked structure on the substrate, a first dielectric layer is first grown on the top surface of the stacked structure, and a first step is formed by wet etching.

[0031] A second dielectric layer is grown on the first step, and a second step and a one-sided gate trench are formed by wet etching. A third step is formed by dry etching, and the one-sided gate trench is located near the end of the second step and away from the third step.

[0032] The source electrode ohmic vias and drain electrode ohmic vias are formed by etching from the top surface of the stacked structure downwards, and the wafer is subjected to a first annealing to grow bottom and top metals. The source electrode ohmic metal, drain electrode ohmic metal, gate electrode and first field plate unit are formed by dry etching. The wafer is then subjected to a second annealing to make the source electrode ohmic metal and drain electrode ohmic metal form ohmic contacts with the two-dimensional electron gas below them, respectively. That is, the source electrode ohmic metal, drain electrode ohmic metal, gate electrode and first field plate unit all include bottom metal layer and top metal layer, and the thickness of the bottom metal layer is 0.1-50nm, and the thickness of the top metal layer is 100-4000nm. In addition, the first annealing and the second annealing in this step are conventional annealing, usually with the heat source applied from the front side of the wafer.

[0033] Finally, a third dielectric layer is grown, forming the source and drain electrodes. Specifically, after growing the third dielectric layer, source and drain electrode vias are etched, metal is grown, and then patterned to form the source and drain electrodes.

[0034] According to some preferred embodiments of the present invention, the dry etching employs a two-stage process, the two-stage process comprising a first stage and a second stage, wherein in the first stage, the etching rate of the top metal layer is greater than the etching rate of the bottom metal layer, and the ratio of the etching rate of the top metal layer to the etching rate of the bottom metal layer is greater than or equal to 1.5.

[0035] In the second stage of the process, the ratio of the etching rate of the bottom metal layer to the etching rate of the capping layer in the stacked structure is greater than or equal to 0.7. To address the etching damage caused by the epitaxial capping layer in the region corresponding to the etching of the source electrode ohmic via, this invention provides another solution: the grown metal (the source electrode ohmic metal, drain electrode ohmic metal, gate electrode, and first field plate unit all include a bottom metal layer and a top metal layer arranged sequentially from bottom to top) has a structure of a bottom metal layer plus a top metal layer, rather than a single metal layer. A two-stage dry etching process is then performed, with the differentiation between the two stages achieved by adjusting key parameters such as power, the ratio of reactive gases, and pressure. Specifically, in the first stage, a high difference in etching rates between the top and bottom metal layers is maintained, with the ratio of the top metal layer etching rate to the bottom metal layer etching rate greater than or equal to 1.5. Preferably, the ratio is greater than or equal to 10. The second stage of the process ensures a selectivity ratio for the etching of the bottom metal layer and the capping layer below it. The ratio of the etching rate of the bottom metal layer to that of the capping layer is greater than or equal to 0.7, and preferably, the ratio of the etching rate of the bottom metal layer to that of the capping layer in the stacked structure is greater than or equal to 3. By optimizing the two-stage process, damage to the capping layer during dry etching is minimized, thereby ensuring that the etching depth of the capping layer is less than 50 nm, and preferably less than 5 nm.

[0036] Due to the adoption of the above technical solutions, the advantages of the present invention compared with the prior art are as follows: The depletion-mode gallium nitride chip and its fabrication method, as well as the cascaded packaging device of the present invention, by setting the source electrode ohmic metal, drain electrode ohmic metal, gate electrode and the first field plate unit in the same layer, and simultaneously forming the first field plate unit with at least two field plates on the second dielectric layer, can greatly simplify the process flow and improve production efficiency; In addition, the structure between the gate electrode and the adjacent source electrode ohmic metal of the present invention is different from that of the prior art, and there is no high step formed by the dielectric layer, which makes the chip flatter and the area required to form the same resistance value smaller. The packaged device obtained by cascading the depletion-mode gallium nitride chip and the enhancement-mode MOS chip of the present invention has a faster switching speed, and the device can meet the requirements of higher frequency, higher efficiency and smaller size when applied in circuits. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic cross-sectional view of the structure after the first dielectric layer is formed in step 2 of embodiments 1 to 7 of the present invention;

[0039] Figure 2 This is a schematic cross-sectional view of the structure after the first step is formed in step 2 of embodiments 1 to 7 of the present invention;

[0040] Figure 3 This is a schematic cross-sectional view of the structure after the second dielectric layer is formed in step 3 of embodiments 1 to 7 of the present invention;

[0041] Figure 4 This is a schematic cross-sectional view of the structure after the second and third steps are formed in step 3 of Embodiments 1 to 3 and Embodiment 7 of the present invention;

[0042] Figure 5 This is a schematic cross-sectional view of the structure after the second step is formed in step 3 of embodiments 4 to 6 of the present invention;

[0043] Figure 6 This is a schematic cross-sectional view of the depletion-type gallium nitride chip according to Embodiment 8 of the present invention;

[0044] Figure 7 This is a schematic cross-sectional view of the depletion-type gallium nitride chip according to Embodiment 9 of the present invention;

[0045] Figure 8 This is a schematic cross-sectional view of the depletion-type gallium nitride chip of Embodiment 10 of the present invention;

[0046] Figure 9 This is a schematic cross-sectional view of the depletion-type gallium nitride chip according to Embodiment 11 of the present invention;

[0047] Figure 10 This is a schematic cross-sectional view of the depletion-type gallium nitride chip according to Embodiment 12 of the present invention;

[0048] The attached figures are labeled as follows:

[0049] Substrate-1, nucleation layer-21, buffer layer-22, channel layer-23, barrier layer-24, capping layer-25, first dielectric layer-31, second dielectric layer-32, third dielectric layer-33, source electrode-41, gate electrode-42, drain electrode-43, source electrode ohmic metal-51, drain electrode ohmic metal-52, first field plate-61, second field plate-62, third field plate-63, fourth field plate-64, fifth field plate-65, connector-66, second field plate unit-7, first step-81, second step-82, third step-83, bottom metal layer-91, top metal layer-92. Detailed Implementation

[0050] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] Example 1: This example provides a method for fabricating a depletion-mode gallium nitride chip, specifically including the following steps:

[0052] Step 1: Nitride epitaxial growth is performed on substrate 1 to sequentially form a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a capping layer 25. The materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 21, buffer layer 22, channel layer 23, barrier layer 24, and capping layer 25 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure. A high concentration of two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 23 and the barrier layer 24, generating a conductive channel.

[0053] Step 2: As Figure 1 As shown, a first dielectric layer 31 is formed by depositing one or more combinations of SiN, SiO2, SiON, and Al2O3 above the capping layer 25, and then wet etching is performed on the first dielectric layer 31 to form a first step 81, as shown. Figure 2 As shown.

[0054] Step 3: As Figure 3 As shown, one or more combinations of SiN, SiO2, SiON, and Al2O3 are deposited on the first step 81 to form a second dielectric layer 32. The second dielectric layer 32 is then wet-etched to form a second step 82 (equivalent to retaining a portion of the second dielectric layer 32 near the drain electrode 43 of the gate electrode 42, so that when the gate electrode 42 is formed later, a step can be formed on the side of the gate electrode 42 near the drain electrode 43 to grow metal and form the first field plate 61) and a single-sided gate trench. The second dielectric layer 32 is then dry-etched to form a third step 83, with the single-sided gate trench located near the end of the second step 82 away from the third step 83, as shown. Figure 4 As shown.

[0055] Step 4: Etch the source electrode ohmic holes and drain electrode ohmic holes downwards from the top surface of the capping layer 25. Both the source electrode ohmic holes and drain electrode ohmic holes penetrate the barrier layer 24 and the capping layer 25. Regenerate metal and use a metal lift-off process to form the source electrode ohmic metal 51, drain electrode ohmic metal 52, gate electrode 42, first field plate 61, second field plate 62, and third field plate 63. Then, anneal in a high-temperature annealing furnace so that the heat source is applied from one side of the substrate 1 of the wafer, allowing the source electrode ohmic metal 51 and drain electrode ohmic metal 52 to form ohmic contacts with the two-dimensional electron gas below them. In this embodiment, the heat source is preferably an infrared heat source.

[0056] Step 5: Finally, deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 to form a third dielectric layer 33. Then, etch source electrode vias, drain electrode vias, and gate vias downwards from the top surface of the third dielectric layer 33. All three vias penetrate the third dielectric layer 33. Next, fill the source electrode vias, drain electrode vias, and gate vias with metal to form source electrode 41, drain electrode 43, and a second field plate unit 7 (equivalent to a gate field plate). The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu. Finally, the depletion-mode gallium nitride chip of this embodiment is obtained. Figure 6 As shown.

[0057] In this embodiment, a high-temperature annealing furnace is used so that the heat source is mainly applied from one side of the wafer substrate 1. The temperature is gradually transferred upward through the substrate 1 side. The source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are both directly connected to the barrier layer 24 below through their respective ohmic vias, resulting in better thermal conductivity. Compared with the source electrode ohmic metal 51 and the drain electrode ohmic metal 52, the gate electrode 42 and the first field plate unit have an additional first dielectric layer 31 and a second dielectric layer 32 below them. The dielectric layers have poor thermal conductivity, which means that the gate electrode 42 and the first field plate unit experience a lower temperature under the same annealing conditions, effectively solving the diffusion phenomenon with the dielectric below them.

[0058] In some other embodiments of the present invention, a depletion-mode gallium nitride chip excluding the second field plate unit 7 can be obtained by not etching the gate via in step 5 of the above embodiment 1.

[0059] Example 2: This example provides a method for fabricating a depletion-mode gallium nitride chip, specifically including the following steps:

[0060] Step 1: Nitride epitaxial growth is performed on substrate 1 to sequentially form a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a capping layer 25. The materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 21, buffer layer 22, channel layer 23, barrier layer 24, and capping layer 25 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure. A high concentration of two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 23 and the barrier layer 24, generating a conductive channel.

[0061] Step 2: As Figure 1 As shown, a first dielectric layer 31 is formed by depositing one or more combinations of SiN, SiO2, SiON, and Al2O3 above the capping layer 25, and then wet etching is performed on the first dielectric layer 31 to form a first step 81, as shown. Figure 2 As shown.

[0062] Step 3: As Figure 3 As shown, one or more combinations of SiN, SiO2, SiON, and Al2O3 are deposited on the first step 81 to form a second dielectric layer 32. The second dielectric layer 32 is then wet-etched to form a second step 82 (equivalent to retaining a portion of the second dielectric layer 32 near the drain electrode 43 of the gate electrode 42, so that when the gate electrode 42 is formed later, a step can be formed on the side of the gate electrode 42 near the drain electrode 43 to grow metal and form the first field plate 61) and a single-sided gate trench. The second dielectric layer 32 is then dry-etched to form a third step 83, with the single-sided gate trench located near the end of the second step 82 away from the third step 83, as shown. Figure 4 As shown.

[0063] Step 4: The source electrode ohmic vias and drain electrode ohmic vias are etched downwards from the top surface of the capping layer 25, and the wafer undergoes a first annealing. Both the source electrode ohmic vias and drain electrode ohmic vias penetrate the barrier layer 24 and the capping layer 25. Metal is then grown back, and a metal lift-off process is used to form the source electrode ohmic metal 51, drain electrode ohmic metal 52, gate electrode 42, first field plate 61, second field plate 62, and third field plate 63. A second annealing is then performed to ensure that the source electrode ohmic metal 51 and drain electrode ohmic metal 52 form ohmic contacts with the two-dimensional electron gas below them. Both the first and second annealing processes involve applying heat from the front side of the wafer.

[0064] Step 5: Finally, deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 to form a third dielectric layer 33. Then, etch source electrode vias, drain electrode vias, and gate vias downwards from the top surface of the third dielectric layer 33. All three vias penetrate the third dielectric layer 33. Next, fill the source electrode vias, drain electrode vias, and gate vias with metal to form source electrode 41, drain electrode 43, and a second field plate unit 7 (equivalent to a gate field plate). The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu. Finally, the depletion-mode gallium nitride chip of this embodiment is obtained. Figure 6 As shown.

[0065] In this embodiment, the quality of the gate electrode 42 and the dielectric layer below the first field plate unit is improved by performing a first annealing on the wafer before metal growth; and the diffusion phenomenon between the gate electrode 42, the first field plate unit and the dielectric layer below them is improved by performing conventional annealing for ohmic contacts again after metal growth.

[0066] In some other embodiments of the present invention, a depletion-mode gallium nitride chip excluding the second field plate unit 7 can be obtained by not etching the gate via in step 5 of the above embodiment 2.

[0067] Example 3: This example provides a method for fabricating a depletion-mode gallium nitride chip, specifically including the following steps:

[0068] Step 1: Nitride epitaxial growth is performed on substrate 1 to sequentially form a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a capping layer 25. The materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 21, buffer layer 22, channel layer 23, barrier layer 24, and capping layer 25 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure. A high concentration of two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 23 and the barrier layer 24, generating a conductive channel.

[0069] Step 2: As Figure 1 As shown, a first dielectric layer 31 is formed by depositing one or more combinations of SiN, SiO2, SiON, and Al2O3 above the capping layer 25, and then wet etching is performed on the first dielectric layer 31 to form a first step 81, as shown. Figure 2 As shown.

[0070] Step 3: As Figure 3As shown, one or more combinations of SiN, SiO2, SiON, and Al2O3 are deposited on the first step 81 to form a second dielectric layer 32. The second dielectric layer 32 is then wet-etched to form a second step 82 (equivalent to retaining a portion of the second dielectric layer 32 near the drain electrode 43 of the gate electrode 42, so that when the gate electrode 42 is formed later, a step can be formed on the side of the gate electrode 42 near the drain electrode 43 to grow metal and form the first field plate 61) and a single-sided gate trench. The second dielectric layer 32 is then dry-etched to form a third step 83, with the single-sided gate trench located near the end of the second step 82 away from the third step 83, as shown. Figure 4 As shown.

[0071] Step 4: Etch the source electrode ohmic vias and drain electrode ohmic vias downwards from the top surface of the capping layer 25, and perform a first annealing on the wafer. Both the source electrode ohmic vias and drain electrode ohmic vias penetrate the barrier layer 24 and the capping layer 25. Regenerate the bottom metal and top metal, and use a two-stage dry etching process to form the source electrode ohmic metal 51, drain electrode ohmic metal 52, gate electrode 42, first field plate 61, second field plate 62, and third field plate 63, each with a bottom metal layer 91 and a top metal layer 92 structure. Then, perform a second annealing on the wafer so that the source electrode ohmic metal 51 and drain electrode ohmic metal 52 form ohmic contacts with the two-dimensional electron gas below them. Both the first and second annealing processes involve applying heat from the front side of the wafer.

[0072] Specifically, the two-stage dry etching process includes a first stage and a second stage. The differentiation between the two stages is achieved by adjusting key parameters such as power, the ratio of reactant gases, and pressure. In the first stage, the ratio of the etching rate of the top metal layer 92 to the etching rate of the bottom metal layer 91 is greater than or equal to 1.5. Preferably, the ratio is greater than or equal to 10, ensuring a high difference in etching rates between the top and bottom metal layers 92 and 91. In the second stage, the ratio of the etching rate of the bottom metal layer 91 to the etching rate of the capping layer 25 is greater than or equal to 0.7. Preferably, the ratio is greater than or equal to 3, ensuring a high selectivity ratio between the etching of the bottom metal layer 91 and the capping layer 25 below it. This two-stage dry etching method can minimize damage to the capping layer 25, thereby ensuring that the etching amount of the capping layer 25 is less than 50nm, preferably less than 5nm.

[0073] Step 5: Finally, deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 to form a third dielectric layer 33. Then, etch source electrode vias, drain electrode vias, and gate vias downwards from the top surface of the third dielectric layer 33. All three vias penetrate the third dielectric layer 33. Next, fill the source electrode vias, drain electrode vias, and gate vias with metal to form source electrode 41, drain electrode 43, and a second field plate unit 7 (equivalent to a gate field plate). The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu. Finally, the depletion-mode gallium nitride chip of this embodiment is obtained. Figure 9 As shown.

[0074] Example 4: This example provides a method for fabricating a depletion-mode gallium nitride chip. The fabrication method in this example is basically the same as that in Example 1, except that in step 3 of this example, the second dielectric layer 32 is no longer dry-etched to form the third step 83. That is, the second dielectric layer 32 in this example does not include the third step 83. Figure 5 As shown, there is only the second step 82, which means that the first field plate unit formed in step 4 of this embodiment only includes the fourth field plate 64 and the fifth field plate 65.

[0075] Example 5: This example provides a method for fabricating a depletion-mode gallium nitride chip. The fabrication method in this example is basically the same as that in Example 2, except that in step 3 of this example, the second dielectric layer 32 is no longer dry-etched to form the third step 83. That is, the second dielectric layer 32 in this example does not include the third step 83. Figure 5 As shown, there is only the second step 82, which means that the first field plate unit formed in step 4 of this embodiment only includes the fourth field plate 64 and the fifth field plate 65.

[0076] Example 6: This example provides a method for fabricating a depletion-mode gallium nitride chip. The fabrication method in this example is basically the same as that in Example 3, except that in step 3 of this example, the second dielectric layer 32 is no longer dry-etched to form the third step 83. That is, the second dielectric layer 32 in this example does not include the third step 83. Figure 5 As shown, there is only the second step 82, which means that the first field plate unit formed in step 4 of this embodiment only includes the fourth field plate 64 and the fifth field plate 65.

[0077] Example 7: This example provides a method for fabricating a depletion-type gallium nitride chip. The fabrication method in this example is basically the same as that in Example 3, except that the gate via is not etched in step 5 of this example. That is, the depletion-type gallium nitride chip prepared in this example does not include the second field plate unit 7.

[0078] Example 8: This example provides a cascaded packaged device, which is obtained by cascading a depletion-mode gallium nitride (GaN) chip and an enhancement-mode MOS chip. The depletion-mode GaN chip can be prepared using the methods described in Examples 1 and 2 above, such as... Figure 6 As shown, the depletion-mode gallium nitride chip includes a source electrode 41, a drain electrode 43, a gate electrode 42, a source electrode ohmic metal 51, a drain electrode ohmic metal 52, a first field plate unit, a second field plate unit 7, a first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33, and a substrate 1 and a stacked structure arranged sequentially from bottom to top. Along a horizontal direction parallel to the length of the substrate 1, the first dielectric layer 31, the second dielectric layer 32, the gate electrode 42, and the first field plate unit are all located between the source electrode ohmic metal 51 and the drain electrode ohmic metal 52. The stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a capping layer 25 arranged sequentially from bottom to top. The heterojunction interface between the channel layer 23 and the barrier layer 24 has a two-dimensional electron gas. Both the source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are located on the side of the capping layer 25 away from the substrate 1. The tops of both the source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are located on the capping layer 25, and the bottoms of both the source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are located in the barrier layer 24. There is no additional dielectric layer below the top of the source electrode ohmic metal 51, which reduces the vertical distance between the bottom of the source electrode ohmic metal 51 and the two-dimensional electron gas below it. When the device is under extreme short-circuit conditions, the bottom surface of the upper end of the source electrode ohmic metal 51 and the two-dimensional electron gas below it can be kept in a semi-off state under a relatively small voltage, making it less prone to short circuit. The bottom of the source electrode 41 and the bottom of the drain electrode 43 are both located in the third dielectric layer 33. The source electrode 41 is located above the source electrode ohmic metal 51 and the bottom of the source electrode 41 is connected to the top of the source electrode ohmic metal 51. The drain electrode 43 is located above the drain electrode ohmic metal 52 and the bottom of the drain electrode 43 is connected to the top of the drain electrode ohmic metal 52.

[0079] Further, the first dielectric layer 31 is located on the side of the capping layer 25 away from the substrate 1, and the bottom surface of the first dielectric layer 31 is in contact with a portion of the top surface of the capping layer 25. The middle part of the second dielectric layer 32 is located above the first dielectric layer 31, and the two ends of the second dielectric layer 32 are located outside the two ends of the first dielectric layer 31. The source electrode ohmic metal 51, the drain electrode ohmic metal 52, and the gate electrode 42 are disposed in the same layer as the first field plate unit. In this embodiment, the first field plate unit includes three field plates and a connecting part 66, namely, the first field plate 61, the second field plate 62, and the third field plate 63. Along the horizontal direction parallel to the length direction of the substrate 1, the second field plate 62 is located between the first field plate 61 and the third field plate 63; along the vertical direction, the first field plate 61 and the third field plate 63 are both located between the second dielectric layer 32 and the third dielectric layer 33, and the second field plate 62 is located between the first dielectric layer 31 and the third dielectric layer 33. The connecting part 66 is located above the first field plate 61 and the second field plate 62, and the connecting part 66 is at the same horizontal height as the third field plate 63. The two ends of the bottom of the connecting part 66 are connected to the first field plate 61 and the second field plate 62 respectively. The top end of the second field plate 62 near the drain electrode 43 is connected to the third field plate 63. The top of the second field plate unit 7 is located above the third dielectric layer 33, and the bottom of the second field plate unit 7 is located in the third dielectric layer 33. The bottom of the second field plate unit 7 is connected to the top surface of the third field plate 63 near the drain electrode 43.

[0080] Along the horizontal direction parallel to the length of substrate 1, the second dielectric layer 32 is located between the gate electrode 42 and the drain electrode ohmic metal 52. Vertically, the gate electrode 42 is located between the third dielectric layer 33 and the capping layer 25. The bottom of the first field plate 61 near the source electrode 41 and away from the second field plate 62 is connected to the top of the gate electrode 42 away from the source electrode 41. The bottom of the gate electrode 42 away from the source electrode 41 is connected to the end of the second dielectric layer 32. The top surface of the gate electrode 42 near the source electrode 41 is flush with the top surface of the source electrode ohmic metal 51. There is a gap between the end of the gate electrode 42 near the source electrode 41 and the end of the source electrode ohmic metal 51 near the gate electrode 42, and this gap is filled with the third dielectric layer 33. This prevents a high step formed by the dielectric layer between the gate electrode 42 and the adjacent source electrode ohmic metal 51, which helps improve resistance and results in better chip flatness. As shown in the figure, the middle part of the third dielectric layer 33 is located above the gate electrode 42, the first field plate unit, and the second dielectric layer 32. The end of the third dielectric layer 33 near the source electrode 41 is located above the source electrode ohmic metal 51 and part of the capping layer 25. The end of the third dielectric layer 33 near the drain electrode 43 is located above the drain electrode ohmic metal 52 and part of the capping layer 25. In this embodiment, the bottom surfaces at both ends of the second dielectric layer 32 and part of the bottom surfaces at both ends of the third dielectric layer 33 are flush with the bottom surface of the first dielectric layer 31. In this embodiment, the thickness of the first dielectric layer 31 is 100-400 nm, and the thickness of the second dielectric layer 32 is 75-310 nm.

[0081] Furthermore, the potential of the first field plate 61 at high voltage balance is equal to the potential of the second field plate 62 at high voltage balance, and also equal to the potential of the third field plate 63 at high voltage balance. The distance from the bottom surface of the first field plate 61 to the capping layer 25 is less than the distance from the bottom surface of the second field plate 62 to the capping layer 25, and the distance from the bottom surface of the second field plate 62 to the capping layer 25 is less than the distance from the bottom surface of the third field plate 63 to the capping layer 25. This ensures that the potential of the two-dimensional electron gas directly below the first field plate 61 at high voltage balance is less than the potential of the two-dimensional electron gas directly below the second field plate 62 at high voltage balance, and the potential of the two-dimensional electron gas directly below the second field plate 62 at high voltage balance is less than the potential of the two-dimensional electron gas directly below the third field plate 63 at high voltage balance.

[0082] In this embodiment, the bottom surface of the first field plate 61 is attached to the top surface of the second dielectric layer 32 below it, and the bottom surface of the third field plate 63 is also attached to the top surface of the second dielectric layer 32 below it. The bottom of the second field plate 62 is located in the first dielectric layer 31. This is because in step 3 of embodiment 1 and / or embodiment 2, when the second dielectric layer 32 is dry etched to form the third step 83, the second dielectric layer 32 is over-etched, that is, etched from the top surface of the second dielectric layer 32 down to the first dielectric layer 31 and a portion of the top of the first dielectric layer 31 is etched. Then, in step 4 of embodiment 1 and / or embodiment 2, when growing metal, the portion of metal that fills the over-etched part of the second dielectric layer 32 on the side of the third step 83 away from the source electrode 41 eventually forms the bottom of the second field plate 62. Furthermore, the thickness of the first dielectric layer 31 is greater than the sum of the thickness of the second dielectric layer 32 and the thickness of the portion of the second field plate 62 located in the first dielectric layer 31, to ensure that the height from the bottom surface of the second field plate 62 to the capping layer 25 is greater than the height from the bottom surface of the first field plate 61 to the capping layer 25. Preferably, the thickness of the portion of the second field plate 62 located in the first dielectric layer 31 accounts for 30%-40% of the total thickness of the second dielectric layer 32.

[0083] During the metal growth process, the metal grown above the second step 82 forms the first field plate 61, and the metal grown on the third step 83 forms the connection portion 66. When the second dielectric layer 32 is patterned by dry etching, the second dielectric layer 32 on the side near the third step 83 away from the source electrode 41 will be over-etched, that is, a part of the first dielectric layer 31 below the second dielectric layer 32 will be etched away. As a result, the second field plate 62 formed by the metal grown on the second dielectric layer 32 will be partially located in the first dielectric layer 31.

[0084] The depletion-mode gallium nitride (GaN) chip in this embodiment exhibits better flatness. It eliminates the traditional gate trench located between the source electrode ohmic metal 51 and the gate electrode 42. Essentially, the gate electrode 42 in this embodiment, compared to the traditional gate electrode 42, eliminates the half of the gate electrode 42 closest to the source electrode 41. This reduces the distance between the source electrode 41 and the gate electrode 42, thereby reducing the spacing between the source electrode 41 and the drain electrode 43. This results in a smaller area required to achieve the same resistance value. When this GaN chip is cascaded with a low-voltage enhancement-mode MOS chip, a smaller package area can be achieved, potentially leading to smaller package sizes. Furthermore, due to the good chip flatness, the same thickness of metal electrodes can withstand thicker wire diameters, allowing for greater current. Devices packaged based on this GaN chip have lower parasitic capacitance and faster switching speeds. When applied to circuits, they can meet higher frequency and efficiency requirements while maintaining a smaller size.

[0085] Example 9: This example provides a cascaded packaged device, which is obtained by cascading and packaging a depletion-mode gallium nitride (GaN) chip and an enhancement-mode MOS chip. The depletion-mode GaN chip can be prepared using the methods described in Examples 4 and 5 above, such as... Figure 7 As shown, the depletion-mode gallium nitride chip includes a source electrode 41, a drain electrode 43, a gate electrode 42, a source electrode ohmic metal 51, a drain electrode ohmic metal 52, a first field plate unit, a second field plate unit 7, a first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33, and a substrate 1 and a stacked structure arranged sequentially from bottom to top. Along a horizontal direction parallel to the length of the substrate 1, the first dielectric layer 31, the second dielectric layer 32, the gate electrode 42, and the first field plate unit are all located between the source electrode ohmic metal 51 and the drain electrode ohmic metal 52. The stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a capping layer 25 arranged sequentially from bottom to top. The heterojunction interface between the channel layer 23 and the barrier layer 24 has a two-dimensional electron gas. Both the source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are located on the side of the capping layer 25 away from the substrate 1. The tops of both the source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are located on the capping layer 25, and the bottoms of both the source electrode ohmic metal 51 and the drain electrode ohmic metal 52 are located in the barrier layer 24. The bottoms of the source electrode 41 and the drain electrode 43 are located in the third dielectric layer 33. The source electrode 41 is located above the source electrode ohmic metal 51 and the bottom of the source electrode 41 is connected to the top of the source electrode ohmic metal 51. The drain electrode 43 is located above the drain electrode ohmic metal 52 and the bottom of the drain electrode 43 is connected to the top of the drain electrode ohmic metal 52.

[0086] Furthermore, the first dielectric layer 31 is located on the side of the capping layer 25 away from the substrate 1, and the bottom surface of the first dielectric layer 31 is in contact with a portion of the top surface of the capping layer 25. The middle part of the second dielectric layer 32 is located above the first dielectric layer 31, and the two ends of the second dielectric layer 32 are located outside the two ends of the first dielectric layer 31. The source electrode ohmic metal 51, the drain electrode ohmic metal 52, the gate electrode 42, and the first field plate unit are disposed in the same layer. In this embodiment, the first field plate unit includes only two field plates, namely the fourth field plate 64 and the fifth field plate 65. Along the horizontal direction parallel to the length direction of the substrate 1, the fourth field plate 64 is located between the gate electrode 42 and the fifth field plate 65; along the vertical direction, both the fourth field plate 64 and the fifth field plate 65 are located between the second dielectric layer 32 and the third dielectric layer 33. The bottom of the fourth field plate 64 near the source electrode 41 is connected to the top of the gate electrode 42 away from the source electrode 41, and the top of the fourth field plate 64 away from the gate electrode 42 is connected to the bottom of the fifth field plate 65 away from the drain electrode 43. The top of the second field plate unit 7 is located above the third dielectric layer 33, and the bottom of the second field plate unit 7 is located in the third dielectric layer 33 and is connected to the top surface of the fifth field plate 65 near the drain electrode 43.

[0087] Along the horizontal direction parallel to the length of substrate 1, the second dielectric layer 32 is located between the gate electrode 42 and the drain electrode ohmic metal 52. Vertically, the gate electrode 42 is located between the third dielectric layer 33 and the capping layer 25. The gate electrode 42 is located at the end of the fourth field plate 64 near the source electrode 41, and the bottom end of the gate electrode 42, away from the source electrode 41, is connected to one end of the second dielectric layer 32. The top surface of the end of the gate electrode 42 near the source electrode 41 is flush with the top surface of the source electrode ohmic metal 51. There is a gap between the end of the gate electrode 42 near the source electrode 41 and the end of the source electrode ohmic metal 51 near the gate electrode 42, and this gap is filled with the third dielectric layer 33. This prevents a high step formed by the dielectric layer between the gate electrode 42 and its adjacent source electrode ohmic metal 51, which helps improve resistance and results in better chip flatness. As shown in the figure, the middle part of the third dielectric layer 33 is located above the gate electrode 42, the first field plate unit, and the second dielectric layer 32. The end of the third dielectric layer 33 near the source electrode 41 is located above the source electrode ohmic metal 51 and part of the capping layer 25. The end of the third dielectric layer 33 near the drain electrode 43 is located above the drain electrode ohmic metal 52 and part of the capping layer 25. In this embodiment, the bottom surfaces at both ends of the second dielectric layer 32 and part of the bottom surfaces at both ends of the third dielectric layer 33 are flush with the bottom surface of the first dielectric layer 31. In this embodiment, the thickness of the first dielectric layer 31 is 100-400 nm, and the thickness of the second dielectric layer 32 is 75-310 nm.

[0088] Furthermore, the potential of the fourth field plate 64 at high voltage equilibrium is equal to that of the fifth field plate 65 at high voltage equilibrium, while the distance from the bottom surface of the fourth field plate 64 to the capping layer 25 is less than the distance from the bottom surface of the fifth field plate 65 to the capping layer 25, to ensure that the potential of the two-dimensional electron gas directly below the fourth field plate 64 at high voltage equilibrium is less than that of the two-dimensional electron gas directly below the fifth field plate 65 at high voltage equilibrium. In this embodiment, the bottom surfaces of both the fourth field plate 64 and the fifth field plate 65 are respectively attached to the top surface of the second dielectric layer 32 below them.

[0089] Example 10: This example provides a cascaded packaged device, which is obtained by cascading a depletion-mode gallium nitride chip and an enhancement-mode MOS chip. For example... Figure 8 As shown, the structure of the depletion-type gallium nitride chip in this embodiment is basically the same as that of the depletion-type gallium nitride chip in embodiment 8. The difference is that the depletion-type gallium nitride chip in this embodiment does not include the second field plate unit 7.

[0090] Example 11: This example provides a cascaded packaged device, which is obtained by cascading a depletion-mode gallium nitride chip and an enhancement-mode MOS chip. For example... Figure 9 As shown, the structure of the depletion-type gallium nitride chip in this embodiment is basically the same as that of the depletion-type gallium nitride chip in embodiment 8. The difference is that the source electrode ohmic metal 51, drain electrode ohmic metal 52, gate electrode 42 and the first field plate unit of the depletion-type gallium nitride chip in this embodiment all include a bottom metal layer 91 and a top metal layer 92 arranged sequentially from bottom to top. The material of the bottom metal layer 91 is preferably Ti, the material of the top metal layer 92 is preferably Al, and the thickness of the bottom metal layer 91 is less than the thickness of the top metal layer 92. The thickness ratio of the bottom metal layer 91 to the top metal layer 92 is 1:30-50, preferably 1:40.

[0091] Example 12: This example provides a cascaded packaged device, which is obtained by cascading a depletion-mode gallium nitride (GaN) chip and an enhancement-mode MOS chip. The structure of the GaN chip in this example is basically the same as that of the GaN chip in Example 9, such as... Figure 10 As shown, the difference is that the depletion-type gallium nitride chip in this embodiment does not include the second field plate unit 7.

[0092] Example 13: This example provides a cascaded packaged device, which is obtained by cascading a depletion-mode gallium nitride (GaN) chip and an enhancement-mode MOS chip. The structure of the GaN chip in this example is basically the same as that of the GaN chip in Example 9. The difference is that the source electrode ohmic metal 51, drain electrode ohmic metal 52, gate electrode 42, and the first field plate unit of the GaN chip in this example all include a bottom metal layer 91 and a top metal layer 92 arranged sequentially from bottom to top. The bottom metal layer 91 is preferably made of Ti, the top metal layer 92 is preferably made of Al, and the thickness of the bottom metal layer 91 is less than the thickness of the top metal layer 92. The thickness ratio of the bottom metal layer 91 to the top metal layer 92 is 1:30-50, preferably 1:40.

[0093] The structure of the depletion-mode gallium nitride chip of the present invention, by placing the source electrode ohmic metal 51, the drain electrode ohmic metal 52, the gate electrode 42, and the first field plate unit in the same layer, and simultaneously forming the first field plate unit with at least two field plates on the second dielectric layer 32, can significantly simplify the process flow and improve production efficiency. Furthermore, the absence of a high step formed by the dielectric layer between the gate electrode 42 and its adjacent source electrode ohmic metal 51 facilitates better chip flatness and reduces the area required to achieve the same resistance value. The packaged device obtained by cascading the depletion-mode gallium nitride chip of the present invention with an enhancement-mode MOS chip has a faster switching speed and can be better applied in circuits.

[0094] The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A depletion-mode gallium nitride chip, comprising a source electrode, a drain electrode, a gate electrode, and a substrate and a stacked structure arranged sequentially from bottom to top, characterized in that, The depletion-mode gallium nitride chip further includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a first field plate unit. The first dielectric layer is located on the side of the stacked structure away from the substrate. The source electrode and the drain electrode are both located on the side of the third dielectric layer away from the substrate. The first field plate unit includes at least two field plates. At least a portion of the first field plate unit is located between the second dielectric layer and the third dielectric layer. The gate electrode is located at the end of the first field plate unit near the source electrode and between the third dielectric layer and the stacked structure. Along a horizontal direction parallel to the length of the substrate, the first dielectric layer, the second dielectric layer, the gate electrode, and the first field plate unit are all located between the source electrode ohmic metal and the drain electrode ohmic metal. A portion of the bottom surface of the second dielectric layer and a portion of the bottom surface of the third dielectric layer are flush with the bottom surface of the first dielectric layer. The stacked structure also has a source electrode ohmic metal and a drain electrode ohmic metal on the side away from the substrate. The source electrode is located above the source electrode ohmic metal, and the drain electrode is located above the drain electrode ohmic metal. The source electrode ohmic metal, the drain electrode ohmic metal, the gate electrode and the first field plate unit are disposed on the same layer.

2. The depletion-mode gallium nitride chip according to claim 1, characterized in that, The stacked structure includes a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a capping layer arranged sequentially from bottom to top. The tops of the source electrode ohmic metal and the drain electrode ohmic metal are both located on the capping layer, and the bottoms of the source electrode ohmic metal and the drain electrode ohmic metal are both located in the barrier layer. The bottom surface of the first dielectric layer is in contact with a portion of the top surface of the capping layer.

3. The depletion-mode gallium nitride chip according to claim 2, characterized in that, The first field plate unit includes a first field plate, a second field plate, and a third field plate. One end of the first field plate is connected to one end of the gate electrode. Along a horizontal direction parallel to the length of the substrate, the second field plate is located between the first field plate and the third field plate. In the vertical direction, both the first field plate and the third field plate are located between the second dielectric layer and the third dielectric layer, and the second field plate is located between the first dielectric layer and the third dielectric layer.

4. The depletion-mode gallium nitride chip according to claim 3, characterized in that, The bottom of the second field plate is located in the first dielectric layer, and the thickness of the first dielectric layer is greater than the sum of the thickness of the second dielectric layer and the thickness of the portion of the second field plate located in the first dielectric layer; the distance from the bottom surface of the first field plate to the capping layer is less than the distance from the bottom surface of the second field plate to the capping layer, and the distance from the bottom surface of the second field plate to the capping layer is less than the distance from the bottom surface of the third field plate to the capping layer.

5. The depletion-mode gallium nitride chip according to claim 3, characterized in that, The first field plate unit includes a connecting part, which is located above the first field plate and the second field plate and at the same horizontal level as the third field plate. The two ends of the bottom of the connecting part are respectively connected to the first field plate and the second field plate, and the top end of the second field plate near the drain electrode is connected to the third field plate.

6. The depletion-mode gallium nitride chip according to claim 2, characterized in that, The top surface of the gate electrode near the source electrode is flush with the top surface of the source electrode ohmic metal, and there is a gap between the end of the gate electrode near the source electrode and the end of the source electrode ohmic metal near the gate electrode; along the horizontal direction parallel to the length of the substrate, the second dielectric layer is located between the gate electrode and the drain electrode ohmic metal, and the bottom end of the gate electrode away from the source electrode is connected to one end of the second dielectric layer.

7. The depletion-mode gallium nitride chip according to claim 1, characterized in that, It also includes a second field plate unit, the top of which is located above the third dielectric layer, the bottom of which is located in the third dielectric layer and is connected to the top of the first field plate unit near the drain electrode.

8. A cascaded packaged device, characterized in that, Includes the depletion-mode gallium nitride chip as described in any one of claims 1-7, wherein the cascaded packaged device is obtained by cascading the depletion-mode gallium nitride chip and the enhancement-mode MOS chip.

9. A method for fabricating a depletion-mode gallium nitride chip, characterized in that, The preparation method is used to prepare the depletion-type gallium nitride chip as described in claim 3, and the preparation method includes the following steps: After growing a stacked structure on the substrate, a first dielectric layer is first grown on the top surface of the stacked structure, and a first step is formed by wet etching. A second dielectric layer is grown on the first step, and a second step and a one-sided gate trench are formed by wet etching. A third step is formed by dry etching, and the one-sided gate trench is located near the end of the second step and away from the third step. Source electrode ohmic metal and drain electrode ohmic metal are formed on the stacked structure, and a gate electrode is formed in a single-sided gate trench and a first field plate unit is formed on the second dielectric layer. The gate electrode is close to the end of the second dielectric layer away from the drain electrode ohmic metal. Finally, a third dielectric layer is grown, forming the source and drain electrodes.

10. The preparation method according to claim 9, characterized in that, The method of forming source electrode ohmic metal and drain electrode ohmic metal on a stacked structure, while forming a gate electrode in a single-sided gate trench and forming a first field plate unit on the second dielectric layer is as follows: Source electrode ohmic holes and drain electrode ohmic holes are formed by etching from the top surface of the stacked structure downwards, metal is regrown, and the source electrode ohmic metal, drain electrode ohmic metal, gate electrode and first field plate unit are formed by patterning. The wafer is then annealed in a high-temperature annealing furnace so that the heat source is applied from the substrate surface of the wafer, so that the source electrode ohmic metal and the drain electrode ohmic metal form ohmic contacts with the two-dimensional electron gas below them respectively.

Images