Short wavelength pin photodiode with integrated DBR and method of manufacturing the same

Abstract

The application discloses a short-wavelength PIN photodiode with an integrated DBR and a preparation method thereof, and relates to the technical field of semiconductors. x Ga 1‑x As / Al y Ga 1‑ y The DBR layer is used for reflecting light transmitted through the absorption layer back to the absorption layer to realize optical path multiplication and is used for expanding the width of a depletion region of the intrinsic region to reduce junction capacitance. The application solves the contradiction between response and bandwidth in a traditional PIN photodiode by using an intrinsic region composed of an absorption layer and an intrinsic undoped DBR layer. The design changes the DBR from a simple optical accessory into an integrated structure with core electrical functions, and breaks the performance bottleneck caused by the difficulty in simultaneously considering capacitance and transit time due to the single absorption layer thickness in the traditional design.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a short-wavelength PIN photodiode with an integrated DBR and its fabrication method. Background Technology

[0002] PIN photodiodes are core detection devices in optical communication systems. Their typical epitaxial structure includes a P-type layer, an intrinsic absorption layer (I-layer), and an N-type layer. The working principle of a PIN photodiode is as follows: under reverse bias, the intrinsic absorption layer forms a wide depletion region; incident light is absorbed within the intrinsic absorption layer, generating electron-hole pairs; these photogenerated carriers are rapidly separated and swept out under the influence of the electric field in the depletion region, forming a photocurrent.

[0003] The high-speed performance of PIN photodiodes is primarily constrained by two physical bottlenecks, and these bottlenecks create a contradiction in their requirements for the intrinsic absorption layer thickness: On the one hand, the device's response speed is limited by the intrinsic junction capacitance, which is inversely proportional to the depletion region width. Therefore, a thicker intrinsic absorption layer is needed to extend the depletion region, reduce capacitance, and improve the RC bandwidth. On the other hand, photogenerated carriers require time to traverse the absorption region (transit time). Therefore, a thinner absorption region is needed to shorten this time and improve the transit time bandwidth. However, in traditional PIN structures, light absorption and depletion region formation are both accomplished by the same intrinsic absorption layer. This leads to a fundamental design conflict: increasing the RC bandwidth requires thickening this layer, while increasing the transit time bandwidth requires thinning it. Therefore, it is difficult to balance responsivity and bandwidth, resulting in performance limitations.

[0004] To address the aforementioned contradictions, some journal articles have proposed introducing distributed Bragg reflectors (DBRs) into PIN or UTC-PDs (single-row carrier photodetectors) used in short-wavelength bands such as 850nm. By placing a DBR structure below the intrinsic absorption layer, transmitted light is reflected back to the intrinsic absorption layer for secondary absorption, thereby effectively improving quantum efficiency without increasing physical thickness. However, in this approach, the DBR is merely used as a passive "optical mirror," with its design goal purely focused on high reflectivity. The doping state and interface electrical quality of its multilayer structure are not integrated and optimized with the intrinsic absorption layer of the PIN junction. This results in the structure being unable to fulfill the electrical functions of extending the depletion region and reducing junction capacitance. Therefore, it can only improve responsivity to a limited extent, but cannot synergistically enhance the bandwidth limited by the RC constant, failing to fundamentally resolve the inherent contradiction in thickness requirements between the two bandwidth mechanisms mentioned above.

[0005] In summary, there is an urgent need to optimize and improve PIN structures containing DBRs, so that DBRs can not only perform the optical path multiplication function to ensure responsivity, but also deeply participate in and lead the formation of depletion regions and capacitance optimization, ultimately achieving a synergistic improvement in the optoelectronic performance of the device. Summary of the Invention

[0006] This invention provides a short-wavelength PIN photodiode with an integrated DBR and its fabrication method, aiming to solve the classic problem of mutual constraint between device bandwidth and responsivity through the synergistic design of the optoelectronic functions of the DBR layer.

[0007] The present invention adopts the following technical solution: A short-wavelength PIN photodiode with an integrated DBR includes, from bottom to top, a GaAs substrate, an n-type contact layer, an intrinsic region, and a p-type contact layer; the intrinsic region includes an absorption layer and a DBR layer located below the absorption layer, the DBR layer being composed of multiple pairs of intrinsically undoped Al atoms. x Ga 1-x As / Al y Ga 1-y The material layers are stacked alternately; the DBR layer is used to reflect light transmitted through the absorption layer back to the absorption layer to achieve optical path multiplication, and to expand the depletion region width of the intrinsic region to reduce junction capacitance.

[0008] Furthermore, the DBR layer has a reflectivity of more than 60% for light with a wavelength of 850nm.

[0009] Furthermore, the Al x Ga 1-x As / Al y Ga 1-y The As material layer has at least 9 alternating periodic pairs.

[0010] Furthermore, the optical thickness of each material layer constituting the DBR layer is one-quarter of the wavelength of the target wavelength in the corresponding material.

[0011] Furthermore, the DBR layer is composed of Al 0.9 Ga 0.1 It consists of alternating layers of As / GaAs material.

[0012] Furthermore, the absorber layer is made of GaAs material and has a thickness of 1-1.2 μm.

[0013] Furthermore, the GaAs substrate is a 6-inch GaAs substrate.

[0014] A method for fabricating a short-wavelength PIN photodiode with an integrated DBR, characterized by comprising the following steps: Step S1: Provide a GaAs substrate; Step S2: An n-type contact layer, a DBR layer, an absorber layer, and a p-type contact layer are grown on the GaAs substrate. The DBR layer consists of multiple pairs of intrinsically undoped Al atoms. x Ga 1-x As / Aly Ga 1-y As material layers are stacked alternately.

[0015] Furthermore, before growing the absorber layer, the surface of the DBR layer is subjected to a high-temperature thermal cleaning treatment.

[0016] Furthermore, the process temperature range for growing the absorber layer is 600°C to 650°C, and a growth interruption mechanism is executed after growing the DBR layer and before starting to grow the absorber layer: for a preset duration, the supply of group V source and the growth temperature are maintained, while the supply of group III source is interrupted.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention addresses the inherent region problem in traditional PIN photodiodes by synergistically resolving the conflict between responsivity and bandwidth through a composite intrinsic region consisting of an absorption layer and an intrinsically undoped DBR layer. The DBR layer, while achieving optical path multiplication to ensure high responsivity, also significantly expands the depletion region width as the main body of the depletion region, thereby significantly reducing junction capacitance and increasing RC bandwidth. This design transforms the DBR from a mere optical accessory into an integrated structure with core electrical functions, breaking through the performance bottleneck caused by the difficulty in balancing capacitance and transit time in traditional designs due to the thinness of a single absorption layer.

[0018] 2. The fabrication method of this invention precisely controls the heterogeneous interface quality between the DBR layer and the absorption layer through key processes such as high-temperature thermal cleaning, optimized growth temperature, and the introduction of growth interruptions. This effectively removes the surface oxide layer and achieves an atomically flat interface, ensuring the excellent optical and electrical performance of the intrinsic DBR layer and the high crystal quality of the thin absorption layer. This process not only reliably realizes the innovative structure of the composite intrinsic region but also ensures the high performance and high yield of the device, laying a solid foundation for large-scale industrial manufacturing. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the extensional structure of the present invention.

[0020] In the figure: 1-GaAs substrate; 2-n-type contact layer; 3-n-type buffer layer; 4-DBR layer; 5-absorber layer; 6-window layer; 7-p-type contact layer. Detailed Implementation

[0021] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. Many details are described below to provide a comprehensive understanding of the invention; however, those skilled in the art will be able to implement the invention without these details.

[0022] Reference Figure 1The present invention provides a short-wavelength PIN photodiode with an integrated DBR, comprising GaAs substrate 1, n-type contact layer 2, n-type buffer layer 3, intrinsic region, window layer 6 and p-type contact layer 7 stacked from bottom to top, wherein the intrinsic region includes absorption layer 5 and DBR layer 4 located below absorption layer 5.

[0023] Reference Figure 1 The functions, material design rationale, and beneficial effects of each epitaxial layer are explained in detail below: GaAs substrate 1: The GaAs substrate 1 serves as the foundation and mechanical support for the epitaxial growth of the entire device. This invention preferably uses a 6-inch semi-insulating GaAs substrate 1, whose core advantages are: compared to the 3-inch or 4-inch substrates commonly used in traditional 850nm PIN-PD, the 6-inch substrate can significantly increase the number of chips produced per process cycle, significantly reduce unit manufacturing costs, and provide fundamental conditions for the large-scale commercialization of high-performance devices. Simultaneously, the semi-insulating characteristics help reduce parasitic capacitance, further improving high-frequency performance.

[0024] n-type contact layer 2: The n-type contact layer 2 is grown on the substrate, typically consisting of highly doped n-type... + - It is made of GaAs material and is used to form a low-resistance ohmic contact with the cathode metal to ensure efficient longitudinal current conduction.

[0025] n-type buffer layer 3: The n-type buffer layer 3 is usually made of n-type AlGaAs material. This layer mainly plays a transitional and buffering role: firstly, it connects the substrate and the subsequent DBR layer 4 in terms of lattice and energy band; secondly, its doping concentration is between that of the heavily doped n-type contact layer 2 and the intrinsic DBR layer 4, which helps to optimize the longitudinal electric field distribution, suppress carrier injection noise, and provide a smooth surface for the growth of high-quality DBR layer 4.

[0026] DBR layer 4: DBR layer 4 is one of the core innovative structures of this invention, consisting of multiple pairs of intrinsically undoped Al atoms. x Ga 1-x As / Al y Ga 1-y The DBR layer is composed of alternating stacked As material layers. Through precise design, this invention enables the DBR layer 4 to simultaneously perform key optical and electrical functions: (1) Optically, the DBR layer 4 is configured as a highly efficient reflector for the target wavelength (e.g., 850nm). By designing the optical thickness of each layer to be one-quarter (λ / 4n) of the wavelength of the target wavelength in the corresponding material, and using at least 9 pairs of alternating periods, it can be ensured that its reflectivity is stably greater than 60%. This specific reflectivity threshold is the result of systematic optimization: it first meets the minimum performance requirements for effective optical synergy with the upper absorption layer 5 and to achieve a significant "optical path multiplication" effect, thus ensuring the realization of high responsivity; at the same time, deliberately not pursuing the ultimate high reflectivity (e.g., >90%) is based on profound considerations for the industrial manufacturing of large-size substrates (6 inches): setting the reflectivity target above 60% rather than higher can significantly reduce the extreme requirements for the thickness and composition uniformity of each layer of DBR, thereby obtaining higher epitaxial growth yield and process window on the 6-inch GaAs substrate 1, ensuring that the high-performance design has the feasibility and cost advantage for large-scale production.

[0027] (2) Electrically, the intrinsically undoped nature of DBR layer 4 and the overall thickness of dozens of layers make it the main component for extending the depletion region of the PIN junction. Under reverse bias, this DBR layer 4 can significantly increase the depletion region width (W). According to the junction capacitance formula (C∝A / W), this directly leads to a significant reduction in the intrinsic junction capacitance of the device, becoming the key to improving the bandwidth determined by the RC constant. As a preferred option, DBR layer 4 is made of Al 0.9 Ga 0.1 The material is composed of alternating As / GaAs layers. The high aluminum content of AlGaAs can provide a larger refractive index difference, which can achieve higher reflectivity and better electrical expansion effect under the same period logarithm.

[0028] Absorption Layer 5: Absorption layer 5 is grown on top of DBR layer 4 and is made of intrinsic GaAs material. Its thickness is precisely optimized to a relatively thin range of 1-1.2 μm. The primary benefit of this design is that it greatly shortens the transit distance of photogenerated carriers, thereby minimizing the transit time and effectively improving the bandwidth determined by the carrier transport velocity. The reason why its relatively thin physical thickness does not sacrifice responsivity is due to its deep synergy with the underlying DBR layer 4: the optical path multiplication effect provided by DBR layer 4 effectively and significantly increases the path of light within absorption layer 5, enabling the device to achieve high speed while still maintaining high photogenerated carrier generation efficiency.

[0029] Window layer 6: Window layer 6 is typically made of p-type AlGaAs material. Its wide band gap can form a barrier to minority carriers (electrons) in absorption layer 5, effectively preventing them from diffusing to the surface and undergoing nonradiative recombination, thereby significantly reducing surface leakage current and improving the internal quantum efficiency and reliability of the device.

[0030] p-type contact layer 7: The p-type contact layer 7 is composed of heavily doped p-type contact layers. + Composed of GaAs material, its function is to form a low-resistance, stable ohmic contact with the anode metal to complete the photoelectric signal output of the device.

[0031] The main innovation of this invention lies in the synergistic design of the composite intrinsic region, which systematically solves the contradiction between responsivity and bandwidth in traditional PIN photodiodes through structural innovation. The specific analysis is as follows: (1) Photoelectric integration of DBR layer 4: By designing DBR layer 4 as an intrinsically undoped multilayer structure that follows precise optical rules (λ / 4n, high reflectivity), this invention makes DBR layer 4 no longer a simple optical accessory, but an active region core that plays the dual roles of optical path multiplier and depletion region expander. This photoelectric integration design essentially transforms its dual structural roles directly into key performance gains of high responsivity and low capacitance (i.e., high RC bandwidth).

[0032] (2) Optimization and synergy of absorption layer 5: The absorption layer 5 of the present invention adopts a thin layer design of 1-1.2 μm, which is a direct optimization for the carrier transit time bottleneck, aiming to maximize the transit time bandwidth. Its performance depends on the optical coupling with DBR layer 4, and the two together constitute a highly efficient absorption enhancement cavity.

[0033] (3) System-level synergy with 6-inch GaAs substrate 1: This invention combines the above-mentioned high-performance device structure design with a 6-inch low-cost substrate platform. This is not just a replacement of components, but a system-level innovation from the perspectives of manufacturability and commercial competitiveness. This ensures that the high-performance device solution not only remains in the laboratory, but can also be transformed into a mass-produced product with market competitiveness due to its significant manufacturing cost advantage, achieving a dual breakthrough in performance and cost.

[0034] Reference Figure 1 This embodiment further provides a method for fabricating a short-wavelength PIN photodiode with an integrated DBR. The method first fabricates a high-quality epitaxial layer on a low-cost, large-size substrate, and then achieves a photoelectric synergistic structure between the DBR layer 4 and the absorption layer 5 through precise control. The key steps of this fabrication process are described in detail below: Step S1: Provide and process GaAs substrate 1 A 6-inch semi-insulating GaAs substrate with a (100) crystal orientation was provided. The substrate was cleaned with acetone, isopropanol and deionized water in sequence, followed by thermal deoxidation in a high-temperature hydrogen atmosphere to obtain a clean, atomically flat substrate surface, laying the foundation for subsequent high-quality epitaxial growth.

[0035] Step S2: Grow an n-type contact layer 2, an n-type buffer layer 3, a DBR layer 4, an absorber layer 5, a window layer 6, and a p-type contact layer 7 on the GaAs substrate 1. Specifically, this includes the following steps: Step S21: Grow n-type contact layer 2 and buffer layer The treated substrate was placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber. After the system was evacuated to a high vacuum, the substrate temperature was raised to a suitable growth temperature (e.g., 580-620℃) under a hydrogen atmosphere. First, highly doped n-type substrates were grown. + - The GaAs layer serves as the n-type contact layer 2, with a thickness of approximately 300-500 nm and a doping concentration of approximately 1 × 10⁻⁶. 18 cm -3 Subsequently, an n-type AlGaAs layer is grown as an n-type buffer layer 3 with a thickness of approximately 100-300 nm. This layer is used to optimize the lattice and band transition and provide a smooth surface.

[0036] Step S22: Grow an intrinsically undoped DBR layer 4 An intrinsically undoped DBR layer 4, which is the core of this invention, is grown on top of the n-type buffer layer 3. Al is grown alternately using an MOCVD process. 0.9 Ga 0.1 As and GaAs layers. By precisely controlling the flow rate and time of source materials such as trimethylaluminum (TMAl) and trimethylgallium (TMGa), the optical thickness of each layer is ensured to be one-quarter (λ / 4n) of the wavelength of the target wavelength (850nm) in the corresponding material. The number of periodic pairs is at least 9 pairs to ensure a reflectivity greater than 60% for the target wavelength. The entire growth process is carried out within an optimized temperature range of 600-650℃ to guarantee the material's crystal quality and steep interface.

[0037] Step S23: Grow the absorption layer 5 and optimize the interface After the growth of DBR layer 4 is completed, the growth of absorption layer 5 is carried out. This is a key step in forming a high-quality heterojunction, and special treatment is required to solve the interface quality problems caused by the easy oxidation of AlGaAs surface and the difference in the mobility of Al and Ga atoms. Step S231, High-Temperature Thermal Cleaning: Because the aluminum atoms in AlGaAs in DBR layer 4 are highly reactive, they rapidly form extremely stable alumina upon exposure to air or even impure hydrogen. Therefore, before growing the absorber layer 5 using MOCVD, the surface of DBR layer 4 must undergo high-temperature thermal cleaning in a pure hydrogen or nitrogen atmosphere. Specifically, before growing absorber layer 5, a brief high-temperature thermal cleaning treatment is performed on the surface of the newly grown AlGaAs (the uppermost layer of DBR layer 4) under a continuous arsine (AsH3) atmosphere and at the growth temperature (600-650℃). This step aims to remove the extremely stable alumina that may form due to environmental exposure or an impure atmosphere, providing a clean and activated surface for subsequent epitaxy.

[0038] Step S232: Introducing a growth interruption to smooth the interface: After thermal cleaning, all group III metal-organic sources (TMGa, TMAl) are turned off. Under constant arsenic atmosphere and temperature, a growth interruption period lasting several seconds to tens of seconds (e.g., 5-30 seconds) is introduced. During this period, surface atoms gain sufficient migration time driven by thermal energy, migrating from higher energy positions to lower energy lattice positions, thereby achieving atomic-level smoothness on the AlGaAs surface. This lays a decisive foundation for growing a smooth heterostructure interface.

[0039] Step S233: Optimize the temperature for growing the absorption layer 5: A moderate compromise growth temperature range (600-650℃) is adopted. This choice takes into account the characteristics of Al atom mobility (requiring higher temperatures to obtain a flat surface) and Ga atom mobility (allowing for flat growth at lower temperatures), aiming to simultaneously ensure the stability of the underlying AlGaAs surface structure and the high crystal quality of the upper GaAs absorption layer 5. At this optimized temperature, a group III source is introduced to precisely grow an intrinsic GaAs absorption layer 5 with a thickness of 1.0-1.2 μm.

[0040] Step S24: Growth window layer 6 and p-type contact layer 7 Above the absorber layer 5, a p-type AlGaAs capping layer is grown as a window layer 6, with a thickness of approximately 100-300 nm, to suppress carrier surface recombination. Finally, heavily doped p-type AlGaAs is grown... + - The GaAs ohmic contact layer, as the p-type contact layer 7, has a thickness of approximately 100-200 nm and is used to form a good anodic contact.

[0041] Step S3: Device Back-End Processing and Microstructure Treatment After all epitaxial growth is completed, standard device fabrication processes are performed: Step S31: Define the device mesa by photolithography and dry etching or wet etching processes.

[0042] Step S32: Deposit a passivation layer (such as SiN) x Surface passivation is performed, and electrode contact holes are cut by photolithography.

[0043] Step S33: Evaporate and alloy the n-side and p-side metal electrodes respectively to form an ohmic contact.

[0044] Step S34: Optionally, microstructure processing (e.g., fabrication of surface plasmon gratings) is performed on the surface of the p-type contact layer 7 to further optimize fiber coupling efficiency.

[0045] Step S35: Finally, perform dicing, packaging, and performance testing to complete the device fabrication.

[0046] The fabrication method provided in this embodiment utilizes precisely controlled MOCVD epitaxy on a 6-inch GaAs substrate 1 to sequentially grow an n-type contact layer 2, an n-type buffer layer 3, a DBR layer 4, an absorption layer 5, a window layer 6, and a p-type contact layer 7. The core of this process lies in the precise control of the optical thickness of the DBR layer 4 and the high-temperature cleaning and growth interruption before the growth of the absorption layer 5. These steps together ensure the high reflectivity electrical quality of the DBR layer 4 and the atomically flat interface of the absorption layer 5, thereby achieving high-performance and high-yield device fabrication.

[0047] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using the design concept shall be considered an infringement of the protection scope of the present invention.

Claims

1. A short-wavelength PIN photodiode with an integrated DBR, characterized in that: It includes a GaAs substrate, an n-type contact layer, an intrinsic region, and a p-type contact layer stacked sequentially from bottom to top; The intrinsic region includes an absorption layer and a DBR layer located below the absorption layer, wherein the DBR layer consists of multiple pairs of intrinsically undoped Al atoms. x Ga 1-x As / Al y Ga 1-y The Al material is composed of alternating layers of As; x Ga 1-x As / Al y Ga 1-y The number of alternating periodic pairs of the As material layers is at least 9, the optical thickness of each material layer constituting the DBR layer is one-quarter of the wavelength of the target wavelength in the corresponding material, the reflectivity of the DBR layer for light with a wavelength of 850nm is greater than 60%, and the GaAs substrate is a 6-inch GaAs substrate. The DBR layer is composed of Al 0.9 Ga 0.1 The material is composed of alternating layers of As / GaAs material; The DBR layer is used to reflect light transmitted through the absorption layer back to the absorption layer to achieve optical path multiplication, and to expand the depletion region width of the intrinsic region to reduce junction capacitance, thereby simultaneously undertaking optical and electrical functions and achieving synergistic improvement of the device's optoelectronic performance.

2. A short-wavelength PIN photodiode with an integrated DBR as described in claim 1, characterized in that: The absorption layer is made of GaAs material and has a thickness of 1-1.2 μm.

3. A method for fabricating a short-wavelength PIN photodiode with an integrated DBR as described in claim 1 or 2, characterized in that: Includes the following steps: Step S1: Provide a GaAs substrate; Step S2: An n-type contact layer, a DBR layer, an absorber layer, and a p-type contact layer are grown on the GaAs substrate. The DBR layer consists of multiple pairs of intrinsically undoped Al atoms. x Ga 1-x As / Al y Ga 1-y As material layers are stacked alternately.

4. The method for fabricating a short-wavelength PIN photodiode with an integrated DBR as described in claim 3, characterized in that: Before growing the absorber layer, the surface of the DBR layer is subjected to a high-temperature thermal cleaning treatment.

5. The method for fabricating a short-wavelength PIN photodiode with an integrated DBR as described in claim 3, characterized in that: The process temperature range for growing the absorber layer is 600°C to 650°C. After growing the DBR layer and before starting to grow the absorber layer, a growth interruption mechanism is executed: for a preset duration, the supply of group V source and the growth temperature are maintained, while the supply of group III source is interrupted.

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