An organic electrochemical transistor synchronous mass long-time test system and an OECT preparation method

Abstract

The application provides an organic electrochemical transistor synchronous batch long-time test system and an OECT preparation method, the system comprises host computer software, a plurality of test units and a plurality of OECT devices, the host computer software comprises front-end modular design and rear-end multi-process architecture, the front-end modular design comprises equipment control module, workflow engine module, real-time visualization module, data management module, communication interface and self-defined UI component, the rear-end multi-process architecture comprises main process, test process, data transmission process and data saving process, the test unit comprises main control and peripheral, driving voltage output circuit, input current measurement module and power management module, and the OECT device sequentially comprises a substrate, a bottom electrode, an organic semiconductor layer, a top electrode, namely a drain electrode, an SU-8 packaging layer, a PDMS small groove and an electrolyte solution from bottom to top. The application scheme realizes the portability, low cost and organic unity of multiple device synchronous test, and improves the test efficiency.

Description

Technical Field

[0001] This invention relates to the field of organic electrochemical transistor testing and fabrication technology, and in particular to a synchronous, high-volume, long-term testing system for organic electrochemical transistors and an OECT fabrication method. Background Technology

[0002] Organic electrochemical transistors (OECTs) are a novel type of organic semiconductor device with significant potential applications in fields such as biosensing and neuromorphic computing. The working principle of OECT devices involves controlling the device's conductivity through the doping / dedoping process of ions within the organic semiconductor material.

[0003] OECT devices typically employ a side-gate vertical structure, comprising three electrodes: source, drain, and gate. The gate is coupled to the organic semiconductor channel via an electrolyte solution. To accurately evaluate the performance of OECT devices, transfer characteristic tests and transient characteristic tests are required.

[0004] Transfer characteristic testing obtains the device's transfer characteristic curve by scanning the gate voltage and measuring the corresponding drain current, which can extract important parameters such as transconductance and on / off ratio. Transient characteristic testing measures the transient response of the drain current by applying a periodic square wave signal to the gate, thus evaluating the device's response speed and stability.

[0005] Existing OECT device testing mainly uses commercial source meters (such as Keithley 2400 series and Keysight B2900 series). These devices are connected to computers via GPIB or USB interfaces, and the testing process is controlled by software such as LabVIEW or MATLAB. During testing, the device is usually placed on a probe station, and the electrolyte solution is directly dropped onto the device surface.

[0006] Existing OECT device packaging methods mainly include covering the device with a glass cover or plastic sheet, but the sealing performance is poor; using microfluidic chip technology, but the fabrication process is complex and requires precision equipment; and directly immersing the device in an electrolyte solution for testing, but the operation is inconvenient.

[0007] In terms of testing software, most existing testing software is a standalone version that uses a serial processing method, which can only test one device at a time. Data acquisition and display are usually separate, making it impossible to achieve true real-time monitoring.

[0008] Existing OECT device testing methods cannot simultaneously meet the comprehensive requirements of portability, low cost, and simultaneous testing of multiple devices. Specifically, this manifests in the following ways:

[0009] The contradiction between portability and stability: existing portable testing solutions have poor stability, while stable testing systems are bulky and cannot meet the needs of on-site testing.

[0010] The contradiction between cost and performance: Existing high-performance testing equipment is expensive (more than 100,000 yuan per unit), while low-cost solutions cannot meet the accuracy requirements, and there is a lack of cost-effective solutions.

[0011] The contradiction between parallel testing and system complexity: existing multi-channel testing systems are highly complex and difficult to integrate, while simple systems cannot support true parallel testing and independent workflow configuration;

[0012] The conflict between real-time performance and data integrity: Existing systems struggle to ensure the complete acquisition and processing of large amounts of parallel data while maintaining real-time response.

[0013] In terms of device packaging, the electrolyte solution in existing packaging solutions is exposed to air and is prone to evaporation, which affects the stability and repeatability of the test. In addition, the open structure used is easily bumped, causing test interruption or device damage. Existing microfluidic packaging methods require complex photolithography or laser processing equipment, which is costly.

[0014] Existing test software systems adopt a single-process architecture, with data acquisition, processing, and display executed serially. This results in slow response times, an inability to support parallel testing of multiple devices, and an inability to meet batch testing requirements. Furthermore, they lack flexible workflow configuration capabilities, making it difficult to implement complex test sequences. Summary of the Invention

[0015] To address the aforementioned issues, this invention proposes a synchronous, high-volume, long-duration testing system for organic electrochemical transistors (OECTs) and an OECT fabrication method, achieving a unified approach to portability, low cost, and simultaneous testing of multiple devices, thereby improving testing efficiency.

[0016] On one hand, this invention provides a synchronous, large-scale, long-term testing system for organic electrochemical transistors (OECTs). The system includes host computer software, multiple test units, and multiple OECT devices. The host computer software includes a front-end modular design and a back-end multi-process architecture. The front-end modular design includes a device control module, a workflow engine module, a real-time visualization module, a data management module, a communication interface, and custom UI components. The back-end multi-process architecture includes a main process, a test process, a data transmission process, and a data storage process. The test units include a main controller and peripherals, a drive voltage output circuit, an input current measurement module, and a power management module. The OECT devices adopt a side-gate vertical structure, consisting of, from bottom to top: a substrate, a bottom electrode, an organic semiconductor layer, a top electrode (drain), an SU-8 package layer, a PDMS tank, and an electrolyte solution.

[0017] Furthermore, the device control module is responsible for managing multiple devices concurrently, controlling multiple test units simultaneously; monitoring device status, displaying the connection status and test progress of each device in real time; and automatically identifying devices, automatically scanning and recognizing connected test units.

[0018] The workflow engine module is responsible for visual process configuration, using a point-and-click interface to configure test steps, and is responsible for dynamic step management, dynamically adding, deleting, and modifying test steps at runtime.

[0019] The real-time visualization module is responsible for high-performance data rendering, using PyQtGraph for efficient real-time plotting; it is also responsible for data separation between steps, intelligently identifying changes in test steps and automatically separating and displaying the data; it also has a memory protection mechanism, with a configurable circular buffer to prevent memory overflow.

[0020] The data management module is responsible for historical data retrieval, supporting the retrieval of historical data by device, time, and test type; it also supports batch multi-select export and interactive data analysis.

[0021] The communication interface is responsible for multi-protocol data decoding, supporting Transfer and Transient data formats; it is responsible for end sequence detection, intelligently detecting data stream end identifiers; and it is responsible for TLV command generation, automatically generating standardized device control commands.

[0022] Custom UI components feature anti-misoperation design, custom renderers, and status indicators.

[0023] Furthermore, the main process is the user interface, responsible for interacting with the user, receiving control commands and displaying test results, managing the lifecycle of test tasks, and sending user operation instructions to the test process through a command queue.

[0024] The testing process is responsible for serial communication with all lower-level devices, i.e., test unit devices, executing specific test tasks, collecting raw data in real time, and putting the raw data collected from the devices into the real-time data queue and the test data queue.

[0025] The data transmission process retrieves data from the real-time data queue, processes and forwards the data transmitted from the test process, sending it to the front-end real-time visualization component on one hand, and caching and preprocessing it on the other hand for later saving;

[0026] The data saving process retrieves data from the test data queue, is responsible for persistently saving the processed data to disk, and provides feedback on the saving status through the save queue. It supports incremental writing and asynchronous batch processing.

[0027] Furthermore, the main control and peripherals include software function modules, a UART interface, direct memory access (DMA), and a timer. The drive voltage output circuit includes analog-to-digital conversion and drive isolation. The input current measurement module includes transimpedance amplification and digital-to-analog conversion. The power management module provides a stable power supply for the entire system. The software function modules include the application layer, protocol layer, hardware abstraction layer, drive interface layer, MCU peripheral resources, and external devices. The main control and peripherals are responsible for receiving and parsing serial commands from the host computer system and scheduling other hardware modules to work according to the commands. The drive voltage output circuit provides stable and accurate drive voltages to the source, drain, and gate of the OECT device according to the main control instructions. The input current measurement module converts the microampere-level current signal generated by the OECT device into a voltage signal through a transimpedance amplifier, performs high-resolution digital sampling, and then realizes current input measurement through digital-to-analog conversion.

[0028] Furthermore, the workflow of the test unit is as follows: The main control MCU receives TLV protocol instructions from the host computer software system through the UART interface. After receiving the instructions, the MCU controls the digital-to-analog converter (DAC) through the SPI bus. The DAC generates a precise analog voltage, which is applied to the corresponding electrode of the OECT device after passing through the drive voltage output circuit. The response current of the OECT device flows through the input current measurement circuit and is converted into a voltage signal. Then, it is sampled by the analog-to-digital converter (ADC). The ADC transmits the digitized measurement results back to the MCU through the I2C bus. The MCU packages the collected data into TLV format and efficiently sends it back to the host computer software system via UART through DMA.

[0029] Furthermore, the bottom electrode includes a source and a gate. The gate is made of gold or silver chloride. The source and gate are directly fabricated on the substrate and are on the same plane. An organic semiconductor layer covers the source, and the drain is located on top of the organic semiconductor layer. The source, organic semiconductor layer, and drain form a sandwich structure in the vertical direction. The SU-8 packaging layer is a photoresist material that is patterned and covered on the electrodes and semiconductor layer of each device. The PDMS trench is integrally attached to the substrate carrying multiple devices. The grid structure inside the trench corresponds to the position of the multiple devices on the substrate. The electrolyte solution is filled in a sealed pool formed by the independent chambers of the PDMS trench and the substrate. Under the action of the gate voltage, ions in the electrolyte will be injected into or extracted from the organic semiconductor layer, thereby changing its conductivity and realizing the gate's control of the channel current.

[0030] The present invention also provides a method for preparing OECT, the method comprising the following steps:

[0031] Step S1, Mask fabrication: Two types of masks are designed. The first type is used for bottom electrode and side gate evaporation, and the second type is used for top electrode evaporation. Both types of masks have positioning marks at the same position to facilitate precise alignment of different evaporation cycles.

[0032] Step S2, substrate preparation: The substrate can be one or more of the following: glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), polyurethane (PU), flexible plastic substrate, metal substrate, or ceramic substrate.

[0033] Step S3, bottom electrode fabrication: The bottom electrode, i.e., the source electrode and the side gate electrode, is fabricated on the substrate. The electrode material can be one or more of the following: gold, silver, copper, aluminum, platinum, palladium, nickel, titanium, chromium, molybdenum, tungsten, graphene, carbon nanotubes, conductive polymers, and transparent conductive oxides (such as ITO and FTO). The fabrication method can be one or more of the following: physical vapor deposition (such as evaporation, magnetron sputtering, electron beam evaporation, thermal evaporation), chemical vapor deposition, solution processing (such as spin coating of suspensions containing metal nanoparticles, spraying, dip coating, brush coating), printing technology (such as screen printing, inkjet printing, gravure printing, flexographic printing, aerosol printing), electrochemical deposition, laser sintering, laser direct writing, or photolithography etching.

[0034] Step S4, Organic Semiconductor Layer Preparation: The organic semiconductor material can be one or more of the following: polythiophene, polyaniline, polypyrrole, phthalocyanine, naphthalenephthalocyanine, pentacene, or other conjugated polymers; the preparation method can be one or more of the following: solution processing (e.g., spin coating, spray coating, dip coating, blade coating, slot coating), printing technology (e.g., screen printing, inkjet printing, gravure printing, flexographic printing, aerosol printing, electrofluid printing), vapor deposition (e.g., vacuum evaporation, molecular beam epitaxy), self-assembly, or solution shearing; patterning can be one or more of the following: traditional photolithography (ultraviolet lithography, electron beam lithography, ion beam lithography), laser direct writing, stencil printing, mask evaporation, selective deposition, or laser ablation;

[0035] Step S5, Top electrode fabrication: The top electrode material and fabrication method are the same as those of the bottom electrode. The same or different materials and processes can be selected according to the device design requirements.

[0036] Step S6, Encapsulation layer preparation: The encapsulation material can be one or more of SU-8 photoresist, polyimide, parylene, PDMS, polystyrene, epoxy resin, silicone rubber, fluoropolymer, or other insulating polymers; the preparation method can be one or more of solution processing (such as spin coating, spray coating, dip coating, blade coating), printing technology, lamination, hot pressing, chemical vapor deposition, or plasma polymerization; patterning can be one or more of photolithography, laser processing, machining, or template forming.

[0037] Step S7, the fabrication and packaging of PDMS microcells, includes:

[0038] Step S71, prepare the PDMS cell, specifically as follows:

[0039] Step S711: Use a glass plate at the bottom to ensure the bottom of the PDMS is smooth;

[0040] Step S712: The 3D printed grid is pasted onto the back of the glass plate to precisely position the columns.

[0041] Step S713: 3D print the pillars and frame, with the pillar height being 1mm lower than the frame height;

[0042] Step S714: Use hot melt adhesive to fix the column and frame to the glass plate;

[0043] Step S715: Mix the PDMS prepolymer and the curing agent at a ratio of 10:1;

[0044] Step S716: Pour the mixed solution into the mold and degas it under vacuum;

[0045] Step S717: The solution obtained in step S716 is heated and cured at 50°C for 1 hour in a vacuum drying oven;

[0046] Step S718: After demolding, a PDMS groove with a smooth bottom and a sealed top is obtained;

[0047] Step S72, packaging and assembly, specifically:

[0048] Step S721: Apply uncured PDMS, i.e., a solution of PDMS prepolymer and curing agent mixed in a 10:1 ratio, to the bottom of the PDMS tank.

[0049] Step S722: Precisely attach the PDMS small groove to the substrate and let it stand overnight to cure;

[0050] Step S723: Inject electrolytes using a two-needle injection method. One needle is used to inject PBS buffer or other electrolyte solution, while the other needle is used to vent air and balance the internal and external air pressure.

[0051] In step S724, after the needle is removed, the self-healing properties of PDMS automatically seal the needle hole, achieving a complete seal.

[0052] Furthermore, the electrode lead-out method is as follows: the source, drain, and gate are all led out to both sides of the substrate, with 9 electrodes (gold fingers) on each side, corresponding to 3 devices. The gold finger spacing matches the test fixture, making it convenient to clamp and use directly.

[0053] Furthermore, in addition to 3D printing, the mold forming technology in steps S712 and S713 can also be CNC machined molds, laser-cut molds, injection molds, or die-casting molds.

[0054] Furthermore, in step S714, in addition to hot melt welding, the assembly and connection methods can also include adhesive bonding, ultrasonic welding, mechanical clamping, or threaded connection.

[0055] Furthermore, the material in step S715 may also be one or more of silicone rubber, polyurethane, epoxy resin, thermoplastic elastomer, thermosetting resin, or other elastic materials with good sealing performance.

[0056] Furthermore, the injection method in step S723 can also be one or more of the following: syringe injection, microsyringe injection, microfluidic pump injection, capillary injection, vacuum injection, or pressure injection.

[0057] The organic electrochemical transistor (OECT) synchronous high-volume long-term testing system and OECT fabrication method provided by this invention systematically solves the key technical problems in existing OECT device testing through innovative PDMS packaging technology, low-cost embedded test units, and efficient multi-process software architecture. While ensuring testing accuracy, it significantly reduces testing costs and improves testing efficiency, providing important technical support for the industrial application of OECT devices. It has the following beneficial technical effects:

[0058] An integrated solution for portable multi-device synchronous testing: By adopting an STM32-based embedded test unit (only 1 / 100 the size of a traditional source meter) and a USB hub parallel connection architecture, it enables the synchronous testing of dozens of devices. Compared with the traditional single source meter testing one by one, the test time is greatly reduced and the device size is reduced by 99%.

[0059] Low-cost, high-precision testing solution: By adopting a high-precision DAC / ADC chip combination (16-bit resolution) and transimpedance amplifier circuit design, it achieves testing accuracy of less than 1% of Keithley source meters while costing only 1 / 60th of professional source meters, effectively resolving the contradiction between cost and performance;

[0060] High-efficiency data processing with multi-process parallel architecture: By adopting a four-process separation architecture (main process, test process, data transmission process, data storage process) and a multi-queue communication mechanism (command queue, real-time data queue, storage queue), high-speed data acquisition of more than 10kHz per second is achieved, while ensuring a smooth interface of more than 10fps, thus resolving the contradiction between real-time performance and data integrity.

[0061] Innovative PDMS encapsulation technology: By adopting an integrated PDMS trough design (smooth bottom, sealed top) and dual-needle injection-self-healing sealing technology, long-term stable testing of electrolyte solutions can be achieved without replenishment for more than two weeks. Compared with open structures, the electrolyte volatility is reduced by more than 95%.

[0062] Standardized device fabrication and connection: By adopting a gold finger guide design (spacing matched with test fixtures), batch plug-and-play connection of devices is achieved, reducing deployment time from 30 minutes for traditional probe stations to 5 minutes;

[0063] Intelligent workflow management: By adopting a visual workflow engine and an automatic data separation algorithm between steps, it supports the automatic execution of complex test sequences such as Transfer and Transient, reducing configuration time by 90% compared to programming methods, and can identify and separate data from different test steps in real time;

[0064] Modular hardware and software design: By adopting the TLV protocol for standardized communication and a front-end and back-end separation software architecture, hot-swappable test units and flexible expansion of software functions are realized, allowing users to dynamically adjust the test scale (from one to dozens of devices) according to their needs.

[0065] Real-time visualization and data management: By adopting a high-performance rendering engine based on PyQtGraph and a circular buffer memory protection mechanism, we have achieved real-time display of 3.5 million data points / devices and complete data storage for long-term testing (two weeks), with memory usage remaining stable within 2GB. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 This is a schematic diagram of the structure of a synchronous large-scale long-term testing system for organic electrochemical transistors provided in an embodiment of the present invention;

[0068] Figure 2 This is a schematic diagram of the structure of the OECT device provided in an embodiment of the present invention;

[0069] Figure 3 This is a schematic diagram of the physical connection relationship of each part of the test system provided in the embodiment of the present invention;

[0070] Figure 4 This is a schematic diagram showing the changes in the transfer curve over a two-week period, as provided in an embodiment of the present invention. Detailed Implementation

[0071] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0072] On the one hand, this invention provides a system for simultaneous, large-scale, long-term testing of organic electrochemical transistors, the system structure of which is as follows: Figure 1 As shown, the system includes host computer software, multiple test units, and multiple OECT devices. The host computer software is the application control layer, the embedded test units are the hardware execution layer, and the OECT devices are the device carrying layer. These three layers work closely together through standardized interfaces and protocols to form a complete integrated test system that combines portability, low cost, high efficiency (multi-device synchronization), and high stability.

[0073] The host computer software includes a front-end modular design and a back-end multi-process architecture. The front-end modular design includes a device control module, a workflow engine module, a real-time visualization module, a data management module, a communication interface, and custom UI components. The host computer software system adopts a front-end and back-end separation and multi-process architecture. The front-end (functional modular design) is responsible for user interaction and business logic, while the back-end (multi-process architecture) is responsible for task execution and data processing.

[0074] The device control module is responsible for managing multiple devices concurrently, supporting the simultaneous control of multiple test units; it is responsible for monitoring device status, displaying the connection status and test progress of each device in real time; and it is responsible for automatic device identification, automatically scanning and identifying connected test units.

[0075] The workflow engine module is responsible for visual process configuration, using a point-and-click interface to configure test steps, supporting complex nested test sequences, and also responsible for dynamic step management, dynamically adding, deleting, and modifying test steps at runtime.

[0076] The real-time visualization module is responsible for high-performance data rendering, using PyQtGraph for efficient real-time plotting; it is also responsible for data separation between steps, intelligently identifying changes in test steps and automatically separating and displaying the data; it also has a memory protection mechanism, with a configurable circular buffer to prevent memory overflow.

[0077] The data management module is responsible for historical data retrieval, supporting the retrieval of historical data by device, time, and test type; it supports batch multi-select export, supports Ctrl / Shift multi-select operation and batch data export, and is also responsible for interactive data analysis, displaying data point details when the mouse hovers over it;

[0078] The communication interface is responsible for multi-protocol data decoding, supporting Transfer (5 bytes) and Transient (7 bytes) data formats; it is responsible for end sequence detection, intelligently detecting the end identifier of the data stream; it is also responsible for TLV command generation, automatically generating standardized device control commands;

[0079] Custom UI components feature anti-accidental operation design, disabling the numerical input box with the mouse wheel; a custom renderer for optimized device list and history display; and status indicators with intuitive color-coded displays of device and test status.

[0080] The backend multi-process architecture includes a main process, a test process, a data transmission process, and a data storage process. The host computer software system acts as the brain of the test system, responsible for defining test tasks, managing the collaboration of multiple devices, processing and visualizing data in real time, and storing and analyzing historical data. Users issue instructions through this software layer, and the software decomposes high-level instructions (such as "start transfer feature test") into standardized low-level commands and distributes them to the designated hardware execution layer modules, i.e., embedded test units. At the same time, it receives data from the hardware layer and performs real-time plotting and asynchronous storage.

[0081] The main process (Qt UI process) is the user interface, responsible for interacting with the user, receiving control commands and displaying test results, and managing the lifecycle of test tasks. After receiving user operation instructions, it sends them to the test process through the command queue.

[0082] TestProcess: This is the core of device control. It is responsible for serial communication with all lower-level devices (test units), executing specific test tasks (such as Transfer or Transient tests), collecting raw data in real time, and putting the raw data collected from the device into the real-time data queue and the test data queue.

[0083] Data Transmission Process: Retrieves data from the real-time data queue, processes and forwards the data transmitted from the test process, sending it to the front-end real-time visualization component on one hand, and caching and preprocessing it on the other hand for later saving;

[0084] DataSaveProcess: Retrieves data from the test data queue, is responsible for persistently saving the processed data to disk (e.g., CSV / HDF5 format), and provides feedback on the saving status through the save queue. It supports incremental writing and asynchronous batch processing.

[0085] The processes communicate collaboratively through command queues, result queues, real-time data queues, and save request queues to form a highly efficient data processing pipeline. This architecture has good parallel performance in a multi-core environment and can effectively cope with complex scenarios of concurrent testing and real-time data processing on multiple devices. This architecture completely separates time-consuming operations (such as device communication and file I / O) from UI responses. Even when controlling multiple devices to perform high-speed data acquisition at the same time, the software interface remains smooth, and data processing and storage are not lost, ensuring the high performance and high stability of the system.

[0086] The front-end modular design provides a graphical user interface (GUI) through which users can connect devices, configure test parameters, design workflows (test sequences), and monitor real-time data. The back-end multi-process architecture implements multi-process concurrency control, adopting a "four-process" architecture that separates the main process (UI), test process (device communication), data transmission process, and data storage process. This architecture is key to achieving true parallel and interference-free testing of multiple devices, ensuring smooth interface, real-time data transmission, and data storage integrity. The workflow engine module allows users to flexibly configure complex test sequences, such as loop tests and multi-step combination tests, through a visual interface, thereby automating the testing process.

[0087] The test unit, acting as the hands and feet of the test system, serves as a bridge connecting the brain (host computer software) and the test object (OECT device). It is responsible for accurately executing the instructions issued by the host computer, applying electrical signals to the OECT device, and acquiring its electrical response with high precision. Each test unit connects to the host computer via a USB-to-UART converter, forming a one-to-one control link. Multiple test units can be connected in parallel to the same host computer via a USB hub. The output of the test unit is connected to the electrodes of the device carrier layer (i.e., the OECT device) through a standardized fixture. This layer converts the digital commands from the host computer into analog electrical signal excitations for the OECT device and converts the analog electrical signal response of the device into a digital data stream, which is then fed back to the host computer. Its modular, miniaturized, and low-cost design is key to achieving the portability and cost-effectiveness of the entire system.

[0088] The test unit includes a main control and peripherals, a drive voltage output circuit, an input current measurement module, and a power management module. The main control and peripherals include software function modules, a UART interface, DMA (Direct Memory Access), and a timer. The drive voltage output circuit includes analog-to-digital conversion and drive isolation. The input current measurement module includes transimpedance amplification and digital-to-analog conversion. The power management module provides a stable power supply for the entire system. The software function modules include an application layer, a protocol layer, a hardware abstraction layer, a driver interface layer, MCU peripheral resources, and external devices. The application layer is the top-level logic, responsible for executing specific test tasks, mainly including a transfer characteristic test module and a transient test module, used to implement transfer characteristic and transient characteristic tests of OECT devices, respectively. The protocol layer is responsible for the parsing and management of communication protocols, including a TLV protocol parsing module and a state machine management module. The TLV protocol parsing module parses TLV (Type-Length-Value) protocol instructions sent by the host computer through the UART interface, and the state machine management module manages the different working states of the test unit during the test process. The hardware abstraction layer... The application layer provides a standardized hardware access interface for upper-layer applications (protocol layer and application layer), eliminating their need to concern themselves with the specific implementation of the underlying hardware and shielding them from hardware differences. The driver interface layer is responsible for direct data interaction and control with MCU peripheral resources (such as UART, SPI, I2C) and external devices (such as DAC, ADC). This layered architecture allows the application layer to focus on the testing task itself without worrying about the underlying communication protocols and hardware driver details, greatly improving system stability and maintainability. It achieves high cohesion and low coupling of software functions, facilitating maintenance and expansion.

[0089] The test unit's workflow is as follows: Centered on the main controller (MCU) and peripherals, the MCU receives TLV protocol instructions from the host computer software system via the UART interface. After receiving the instructions, the MCU controls the DAC (digital-to-analog converter) via the SPI bus. The DAC generates a precise analog voltage, which is applied to the corresponding electrode of the OECT device (drive voltage) after passing through the drive voltage output circuit (drive isolation to implement voltage follower). The response current (current input) of the OECT device flows through the input current measurement circuit (including transimpedance amplifier) ​​and is converted into a voltage signal. Then, it is sampled by the ADC (analog-to-digital converter). The ADC transmits the digitized measurement results back to the MCU via the I2C bus. The MCU packages the acquired data into TLV format and efficiently sends it back to the host computer software system via UART through DMA, reducing the CPU load.

[0090] Main controller module (MCU): Typically an STM32 or other microcontroller, responsible for receiving and parsing serial commands from the host computer system (via the TLV protocol), and scheduling other hardware modules to work according to the commands.

[0091] Drive voltage output circuit: Includes a high-precision digital-to-analog converter (DAC) that provides stable and accurate drive voltages to the source, drain, and gate of the OECT device according to the master control instructions.

[0092] Input current measurement module: includes a high-precision analog-to-digital converter (ADC) and a transimpedance amplifier circuit. The transimpedance amplifier converts the microampere-level current signal generated by the OECT device into a voltage signal, performs high-resolution digital sampling, and then realizes current input measurement through digital-to-analog conversion.

[0093] OECT devices serve as the object and foundation of testing, providing stable, reliable, and standardized devices under test. The packaging technology of this invention is key to ensuring long-term stability and repeatability of testing.

[0094] OECT devices employ a side-gate vertical structure, such as Figure 2 As shown, from bottom to top, the components are: substrate, bottom electrode, organic semiconductor layer, top electrode (i.e., drain), SU-8 package layer, PDMS tank, and electrolyte solution. The bottom electrode includes a source and a gate, with the gate made of gold or silver chloride. The OECT device, as the object under test (DUT), has its source, drain, and gate connected to the drive voltage output circuit and input current measurement module of the test unit, respectively, forming a complete test loop. The system supports the simultaneous connection of multiple independent OECT devices, allowing parallel and independent testing by the host computer and their respective test units.

[0095] The substrate, as the base layer, is located at the bottom and provides mechanical support for the entire OECT device. It is a common substrate that supports multiple devices and is preferably a glass substrate.

[0096] The bottom electrode (source and gate), organic semiconductor layer, and drain are the electrodes and semiconductor layer, which are the core functional areas. The source and gate are directly fabricated on the glass substrate and are on the same plane. The organic semiconductor layer covers the source and is the core active material of the device. Its conductivity is regulated by ions. The drain is fabricated on top of the organic semiconductor layer. The source, organic semiconductor layer, and drain form a "sandwich" structure in the vertical direction, forming a vertical channel for current to flow from the source to the drain.

[0097] The SU-8 encapsulation layer, PDMS trench, and electrolyte solution constitute the encapsulation and isolation layer. The SU-8 encapsulation layer is a photoresist material that is patterned over the electrodes and semiconductor layers of each device, defining the electrical boundaries of individual devices and precisely exposing the active regions of the devices (i.e., above the channel and the gate region). At the same time, it covers and protects the leads and electrodes in non-working areas, preventing electrolyte infiltration from causing short circuits. The PDMS (polydimethylsiloxane) trench is a one-piece sealed container containing multiple independent chambers. It is integrally bonded to a glass substrate carrying multiple devices. Its size is greater than or equal to the area defined by a single SU-8. The grid structure inside corresponds to the positions of the multiple devices on the substrate, forming multiple independent and non-interconnected structures. The "pool" serves as a multi-device isolation and physical protection / environmental isolation. Multi-device isolation ensures that the electrolyte solution of each device is confined to its own chamber, preventing cross-contamination and electrical interference. This is a prerequisite for achieving synchronous and independent testing. Physical protection and environmental isolation are achieved by the PDMS tank and the glass substrate below forming a sealed structure, effectively preventing the electrolyte in all chambers from evaporating, leaking, and becoming contaminated. The electrolyte is filled in the sealed pool formed by the independent chambers of the PDMS tank and the glass substrate. It is the key medium for realizing OECT operation. Its function is ion coupling. Under the action of the gate voltage, ions in the electrolyte will be injected / extracted from the organic semiconductor layer, thereby changing its conductivity and realizing the gate's control of the channel current.

[0098] The entire OECT device first uses the SU-8 layer to precisely define the independent electrical boundaries and active regions for each device on the substrate. Then, an integrated multi-chamber PDMS groove is used as a sealing and isolation structure to cover the entire substrate. This combined packaging method not only provides a stable working environment for each device, but more importantly, it achieves physical and chemical isolation between multiple devices on a single substrate, thus forming a stable and reliable micro-device array suitable for large-scale synchronous testing.

[0099] On the other hand, the present invention also provides a method for preparing OECT, the method comprising the following steps:

[0100] Step S1, Mask fabrication: Two types of masks are designed. The first type is used for bottom electrode and side gate evaporation, and the second type is used for top electrode evaporation. Both types of masks have positioning marks at the same position to facilitate precise alignment of different evaporation cycles.

[0101] Step S2, substrate preparation: The substrate can be one or more of the following: glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), polyurethane (PU), flexible plastic substrate, metal substrate, or ceramic substrate.

[0102] Step S3, bottom electrode fabrication: The bottom electrode, i.e., the source electrode and the side gate electrode, is fabricated on the substrate. The electrode material can be one or more of the following: gold, silver, copper, aluminum, platinum, palladium, nickel, titanium, chromium, molybdenum, tungsten, graphene, carbon nanotubes, conductive polymers, and transparent conductive oxides (such as ITO and FTO). The fabrication method can be one or more of the following: physical vapor deposition (such as evaporation, magnetron sputtering, electron beam evaporation, thermal evaporation), chemical vapor deposition, solution processing (such as spin coating of suspensions containing metal nanoparticles, spraying, dip coating, brush coating), printing technology (such as screen printing, inkjet printing, gravure printing, flexographic printing, aerosol printing), electrochemical deposition, laser sintering, laser direct writing, or photolithography etching.

[0103] Step S4, Organic Semiconductor Layer Preparation: The organic semiconductor material can be one or more of the following: polythiophene, polyaniline, polypyrrole, phthalocyanine, naphthalenephthalocyanine, pentacene, or other conjugated polymers; the preparation method can be one or more of the following: solution processing (e.g., spin coating, spray coating, dip coating, blade coating, slot coating), printing technology (e.g., screen printing, inkjet printing, gravure printing, flexographic printing, aerosol printing, electrofluid printing), vapor deposition (e.g., vacuum evaporation, molecular beam epitaxy), self-assembly, or solution shearing; patterning can be one or more of the following: traditional photolithography (ultraviolet lithography, electron beam lithography, ion beam lithography), laser direct writing, stencil printing, mask evaporation, selective deposition, or laser ablation;

[0104] Step S5, Top electrode fabrication: The top electrode material and fabrication method are the same as those of the bottom electrode. The same or different materials and processes can be selected according to the device design requirements.

[0105] Step S6, Encapsulation layer preparation: The encapsulation material can be one or more of SU-8 photoresist, polyimide, parylene, PDMS, polystyrene, epoxy resin, silicone rubber, fluoropolymer, or other insulating polymers; the preparation method can be one or more of solution processing (such as spin coating, spray coating, dip coating, blade coating), printing technology, lamination, hot pressing, chemical vapor deposition, or plasma polymerization; patterning can be one or more of photolithography, laser processing, machining, or template forming.

[0106] Step S7, the fabrication and packaging of PDMS microcells, includes:

[0107] Step S71, prepare the PDMS cell, specifically as follows:

[0108] Step S711: Use a glass plate at the bottom to ensure the bottom of the PDMS is smooth;

[0109] Step S712: The 3D printed grid is pasted onto the back of the glass plate to precisely position the columns.

[0110] Step S713: 3D print the pillars and frame, with the pillar height being 1mm lower than the frame height;

[0111] Step S714: Use hot melt adhesive to fix the column and frame to the glass plate;

[0112] Step S715: Mix the PDMS prepolymer and the curing agent at a ratio of 10:1;

[0113] Step S716: Pour the mixed solution into the mold and degas it under vacuum;

[0114] Step S717: The solution obtained in step S716 is heated and cured at 50°C for 1 hour in a vacuum drying oven;

[0115] Step S718: After demolding, a PDMS groove with a smooth bottom and a sealed top is obtained;

[0116] Step S72, packaging and assembly, specifically:

[0117] Step S721: Apply uncured PDMS, i.e., a solution of PDMS prepolymer and curing agent mixed in a 10:1 ratio, to the bottom of the PDMS tank.

[0118] Step S722: Precisely attach the PDMS small groove to the substrate and let it stand overnight to cure;

[0119] Step S723: Inject electrolytes using a two-needle injection method. One needle is used to inject PBS buffer or other electrolyte solution, while the other needle is used to vent air and balance the internal and external air pressure.

[0120] In step S724, after the needle is removed, the self-healing properties of PDMS automatically seal the needle hole, achieving a complete seal.

[0121] Furthermore, the electrode lead-out method is as follows: the source, drain, and gate are all led out to both sides of the substrate, with 9 electrodes (gold fingers) on each side, corresponding to 3 devices. The gold finger spacing matches the test fixture, making it convenient to clamp and use directly.

[0122] Furthermore, in addition to 3D printing, the mold forming technology in steps S712 and S713 can also be CNC machined molds, laser-cut molds, injection molds, or die-casting molds.

[0123] Furthermore, in step S714, in addition to hot melt welding, the assembly and connection methods can also include adhesive bonding, ultrasonic welding, mechanical clamping, or threaded connection.

[0124] Furthermore, the material in step S715 may also be one or more of silicone rubber, polyurethane, epoxy resin, thermoplastic elastomer, thermosetting resin, or other elastic materials with good sealing performance.

[0125] Furthermore, the injection method in step S723 can also be one or more of the following: syringe injection, microsyringe injection, microfluidic pump injection, capillary injection, vacuum injection, or pressure injection.

[0126] To ensure a smooth bottom and a sealed top for the PDMS slot, this invention uses a glass plate as the bottom mold, 3D prints columns and frames, with the columns being 1mm lower than the frames to ensure a sealed top. A 3D printed grid is used to precisely position the columns, and the elastic material properties enable automatic healing of pinholes. Multiple devices can be packaged in a single fabrication.

[0127] A preferred embodiment of the preparation method is as follows:

[0128] The first gold electrode, namely the bottom electrode and the side gate, is deposited on a 3cm×3cm glass substrate.

[0129] Spin-coating an organic semiconductor solution forms an active layer, namely an organic semiconductor layer;

[0130] Use a laser direct writing device (LPKF) to remove irrelevant areas;

[0131] The top electrode is vapor-deposited to form a sandwich structure;

[0132] Spin-coating SU-8 photoresist and encapsulating inactive areas using photolithography;

[0133] Electrode lead-out design: The source, drain, and gate are all led out to both sides of the glass substrate, with 9 electrodes (gold fingers) on each side, corresponding to 3 devices. The gold finger spacing matches the test fixture for easy direct clamping and use.

[0134] The fabrication and packaging of PDMS microcells include:

[0135] The preparation of PDMS microcells is as follows:

[0136] The bottom is made of a 10cm x 10cm glass plate to ensure a smooth bottom for the PDMS.

[0137] 3D-printed grids are glued to the back of the glass plate to precisely position the columns;

[0138] 3D printed columns and frames;

[0139] Use hot melt adhesive to fix the columns and frames to the glass plate;

[0140] Mix the PDMS prepolymer and the curing agent at a ratio of 10:1;

[0141] Pour the mixed solution into the mold and degas under vacuum;

[0142] The solution obtained in step S16 was cured by heating at 50°C for 1 hour in a vacuum drying oven.

[0143] After demolding, a PDMS trough with a smooth bottom and a sealed top is obtained;

[0144] Packaging and assembly, specifically:

[0145] Apply a small amount of uncured PDMS to the bottom of the PDMS tank;

[0146] Precisely attach the PDMS micro-cells to the substrate and let them cure overnight.

[0147] Electrolytes are injected using a two-needle injection method. One needle is used to inject PBS buffer or other electrolyte solution, while the other needle is used to expel air and balance the internal and external air pressure.

[0148] After the needle is removed, the self-healing properties of PDMS automatically seal the needle hole, achieving a complete seal.

[0149] The technical effects of the present invention will be verified through specific embodiments below.

[0150] Example 1: Batch Screening Test of OECT Devices

[0151] Test scenario: To screen the performance of a batch of newly fabricated OECT devices and test their transfer characteristic curves.

[0152] The implementation steps are as follows:

[0153] Device fabrication: Six OECT devices were fabricated on a 3cm×3cm glass substrate according to the OECT device fabrication method provided in this invention, using a side-gate vertical structure;

[0154] PDMS encapsulation: PDMS grooves are prepared using the PDMS groove preparation method provided in this invention, and then PDMS encapsulation is performed using a bottom-smooth and top-sealed design;

[0155] Electrolyte injection: PBS buffer was injected using a two-needle injection method, with one needle injected and the other vented.

[0156] System connection: according to Figure 3 The connection method shown connects the six devices to the six test units, which are then connected to the PC via a USB docking station.

[0157] Workflow configuration: Configure the Transfer test parameters in the host computer software, with gate voltage ranging from -0.3V to 0.4V in 10mV increments, drain voltage of 0.1V, and sampling interval of 300ms;

[0158] Parallel testing: Simultaneously start testing of 6 devices and observe the transfer characteristic curves in real time.

[0159] Test results are as follows Figure 4 As shown, the specific manifestation is as follows:

[0160] Efficiency improvement: All tests on 6 devices were completed within 1 minute, which is 83% faster than testing each device individually with a single source meter (6 minutes).

[0161] Cost Comparison: The entire system costs approximately 10,000 yuan, a 98% reduction compared to 6 professional source tables (600,000 yuan).

[0162] Accuracy verification: Compared with FS Pro professional source table, the error of the Transfer characteristic curve is less than 1%;

[0163] Stability performance: PDMS encapsulation effectively prevents electrolyte evaporation, eliminating the need for electrolyte replenishment during testing.

[0164] Example 2: Long-term evaluation of device stability

[0165] Test scenario: Evaluating the stability of multiple OECT devices under repeated switching requires long-term continuous testing.

[0166] The implementation steps are as follows:

[0167] Multi-step workflow configuration:

[0168] Step 1: Transfer test (gate voltage: -0.3V to 0.4V, step 10mV, drain voltage: 0.1V, sampling interval: 300ms).

[0169] Step 2: Transient test (gate voltage: -0.3V / 0.4V, pulse period: 125ms low level, 125ms high level, test cycle: 2000 times, sampling interval: 1ms).

[0170] Step 3: Loop (repeat steps 1-2 a total of 2000 times).

[0171] Automated execution: Use the workflow engine to automatically execute complex test sequences;

[0172] Real-time monitoring: Through the inter-step data separation algorithm, the results of different test steps can be viewed in real time;

[0173] Data Management: The system automatically saves all test data and supports historical data retrieval and analysis.

[0174] The test results are as follows:

[0175] Test scale: Continuous operation for two weeks, with 350,588,000 data points automatically collected for each device;

[0176] System stability: The multi-process architecture ensures long-term stable operation without system crashes;

[0177] Encapsulation effect: PDMS encapsulation effectively prevents electrolyte evaporation, requiring no manual intervention throughout the process;

[0178] Data integrity: All test data is fully saved, supporting subsequent in-depth analysis;

[0179] User experience: The visual interface displays the test progress in real time and supports parameter adjustment during the test.

[0180] As can be seen, this invention achieves breakthroughs in portability: a 90% reduction in size, from desktop rack-mounted to portable case-type, supporting on-site testing; an 85% reduction in weight: the entire system weighs less than 2kg, allowing for single-person operation; a 95% reduction in deployment time: plug-and-play, system setup completed within 5 minutes; breakthroughs in cost-effectiveness: hardware costs reduced by 97%, from over 600,000 RMB to less than 20,000 RMB; a 83% reduction in single-test costs, with parallel testing efficiency improved by 6-24 times; a 70% reduction in maintenance costs, with modular design facilitating maintenance and upgrades; breakthroughs in testing efficiency: parallelism improved by 6-24 times, simultaneously testing 6-24 devices vs. a single device; improved data processing efficiency, with multi-process architecture vs. single-process; a 90% reduction in workflow configuration time, with visual configuration vs. programming configuration; and expanded application scenarios: laboratory batch screening, high-throughput device performance evaluation; rapid on-site testing, portable equipment on-site testing; teaching experimental platform, low-cost multi-student simultaneous experiments; industrial pilot production, batch device consistency verification.

[0181] This invention achieves a portable and stable testing platform through simplified packaging, mass production, and standard connections. It realizes a low-cost and high-efficiency testing system through hardware miniaturization, software parallelism, and communication standards. It achieves real-time and complete data processing through multi-process separation, data diversion, and intelligent parsing. It realizes a flexible and easy-to-use testing tool through modular design, workflow engine, and visual configuration. This invention is the first to achieve a three-dimensional unification of portability, low cost, and multi-device synchronization in the field of OECT testing, providing key technical support for the field to move from the laboratory to industrialization.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A synchronous, high-volume, long-duration testing system for organic electrochemical transistors, characterized in that, The system includes host computer software, multiple test units, and multiple OECT devices. The host computer software includes a front-end modular design and a back-end multi-process architecture. The front-end modular design includes a device control module, a workflow engine module, a real-time visualization module, a data management module, a communication interface, and custom UI components. The back-end multi-process architecture includes a main process, a test process, a data transmission process, and a data storage process. The test units include a main controller and peripherals, a drive voltage output circuit, an input current measurement module, and a power management module. The OECT devices adopt a side-gate vertical structure, which, from bottom to top, consists of: a substrate, a bottom electrode, an organic semiconductor layer, a top electrode (drain), an SU-8 package layer, a PDMS tank, and an electrolyte solution. Among them, the device control module is responsible for the concurrent management of multiple devices, controlling multiple test units at the same time; it is responsible for monitoring the device status, displaying the connection status and test progress of each device in real time; and it is responsible for automatic device identification, automatically scanning and identifying connected test units. The workflow engine module is responsible for visual process configuration, using a point-and-click interface to configure test steps, and is responsible for dynamic step management, dynamically adding, deleting, and modifying test steps at runtime. The real-time visualization module is responsible for high-performance data rendering, using PyQtGraph for efficient real-time plotting; it is also responsible for data separation between steps, intelligently identifying changes in test steps and automatically separating and displaying the data; it also has a memory protection mechanism, with a configurable circular buffer to prevent memory overflow. The data management module is responsible for historical data retrieval, supporting the retrieval of historical data by device, time, and test type; it also supports batch multi-select export and interactive data analysis. The communication interface is responsible for multi-protocol data decoding, supporting Transfer and Transient data formats; it is responsible for end sequence detection, intelligently detecting data stream end identifiers; and it is responsible for TLV command generation, automatically generating standardized device control commands. Custom UI components feature anti-misoperation design, custom renderers, and status indicators; The main process is the user interface, responsible for interacting with the user, receiving control commands and displaying test results, and managing the lifecycle of test tasks. After receiving user operation instructions, it sends them to the test process through a command queue. The testing process is responsible for serial communication with all lower-level devices, i.e., test unit devices, executing specific test tasks, collecting raw data in real time, and putting the raw data collected from the devices into the real-time data queue and the test data queue. The data transmission process retrieves data from the real-time data queue, processes and forwards the data transmitted from the test process, sending it to the front-end real-time visualization component on one hand, and caching and preprocessing it on the other hand for later saving; The data saving process retrieves data from the test data queue, is responsible for persistently saving the processed data to disk, and provides feedback on the saving status through the save queue. It supports incremental writing and asynchronous batch processing.

2. The organic electrochemical transistor synchronous mass long-term testing system according to claim 1, characterized in that, The main control and peripherals include software function modules, a UART interface, direct memory access (DMA), and a timer. The drive voltage output circuit includes analog-to-digital conversion and drive isolation. The input current measurement module includes transimpedance amplification and digital-to-analog conversion. The power management module provides a stable power supply for the entire system. The software function modules include the application layer, protocol layer, hardware abstraction layer, drive interface layer, MCU peripheral resources, and external devices. The main control and peripherals are responsible for receiving and parsing serial commands from the host computer software and scheduling other hardware modules to work according to the commands. The drive voltage output circuit provides stable and accurate drive voltages to the source, drain, and gate of the OECT device according to the main control instructions. The input current measurement module converts the microampere-level current signal generated by the OECT device into a voltage signal through a transimpedance amplifier, performs high-resolution digital sampling, and then realizes current input measurement through digital-to-analog conversion.

3. The organic electrochemical transistor synchronous large-scale long-term testing system according to claim 2, characterized in that, The workflow of the test unit is as follows: The main control MCU receives TLV protocol instructions from the host computer software through the UART interface. After receiving the instructions, the MCU controls the digital-to-analog converter (DAC) through the SPI bus. The DAC generates a precise analog voltage, which is applied to the corresponding electrode of the OECT device after passing through the drive voltage output circuit. The response current of the OECT device flows through the input current measurement circuit and is converted into a voltage signal. Then, the analog-to-digital converter (ADC) samples the signal. The ADC transmits the digitized measurement results back to the MCU through the I2C bus. The MCU packages the acquired data into TLV format and efficiently sends it back to the host computer software via UART through DMA.

4. The organic electrochemical transistor synchronous mass long-term testing system according to claim 1, characterized in that, The bottom electrode includes a source and a gate. The gate is made of gold or silver chloride. The source and gate are directly fabricated on the substrate and are on the same plane. An organic semiconductor layer covers the source, and the drain is located on top of the organic semiconductor layer. The source, organic semiconductor layer, and drain form a sandwich structure in the vertical direction. The SU-8 packaging layer is a photoresist material that is patterned and covered on the electrodes and semiconductor layer of each device. The PDMS trench is integrally bonded to the substrate carrying multiple devices. The grid structure inside the trench corresponds to the position of the multiple devices on the substrate. The electrolyte solution is filled in a sealed pool formed by the independent chambers of the PDMS trench and the substrate. Under the action of the gate voltage, ions in the electrolyte will be injected into or extracted from the organic semiconductor layer, thereby changing its conductivity and realizing the gate's control of the channel current.

5. A method for preparing OECT, characterized in that, The method includes the following steps: Step S1, Mask fabrication: Two types of masks are designed. The first type is used for bottom electrode and side gate evaporation, and the second type is used for top electrode evaporation. Both types of masks have positioning marks at the same position to facilitate precise alignment of different evaporation cycles. Step S2, substrate preparation: The substrate is selected from one or more of the following: glass, silicon wafer, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), polyurethane (PU), metal substrate, or ceramic substrate. Step S3, bottom electrode fabrication: The bottom electrode, i.e., the source electrode and the side gate electrode, is fabricated on the substrate. The electrode material is selected from one or more of the following: gold, silver, copper, aluminum, platinum, palladium, nickel, titanium, chromium, molybdenum, tungsten, graphene, carbon nanotubes, conductive polymers, and transparent conductive oxides. The fabrication method is one or more of the following: physical vapor deposition, chemical vapor deposition, solution processing, printing technology, electrochemical deposition, laser sintering, laser direct writing, or photolithography. Step S4, Organic Semiconductor Layer Preparation: The organic semiconductor material is selected from one or more of the following: polythiophene, polyaniline, polypyrrole, phthalocyanine, naphthalenephthalocyanine, pentacene, or other conjugated polymers; the preparation method adopts one or more of the following: solution processing, printing technology, vapor deposition, self-assembly, or solution shearing; patterning adopts one or more of the following: traditional photolithography, laser direct writing, stencil printing, mask evaporation, selective deposition, or laser ablation. Step S5, Top electrode preparation: The top electrode material and preparation method are the same as those for the bottom electrode; Step S6, encapsulation layer preparation: The encapsulation material is selected from one or more of SU-8 photoresist, polyimide, parylene, PDMS, polystyrene, epoxy resin, silicone rubber, and fluorinated polymer; the preparation method adopts one or more of solution processing, printing technology, lamination, hot pressing, chemical vapor deposition, or plasma polymerization; the patterning adopts one or more of photolithography, laser processing, machining, or template forming. Step S7, the fabrication and packaging of PDMS microcells, includes: Step S71, prepare the PDMS cell, specifically as follows: Step S711: Use a glass plate at the bottom to ensure the bottom of the PDMS is smooth; Step S712: The 3D printed grid is pasted onto the back of the glass plate to precisely position the columns. Step S713: 3D print the pillars and frame, with the pillar height being 1mm lower than the frame height; Step S714: Use hot melt adhesive to fix the column and frame to the glass plate; Step S715: Mix the PDMS prepolymer and the curing agent at a ratio of 10:1; Step S716: Pour the mixed solution into the mold and degas it under vacuum; Step S717: The solution obtained in step S716 is heated and cured at 50°C for 1 hour in a vacuum drying oven; Step S718: After demolding, a PDMS groove with a smooth bottom and a sealed top is obtained; Step S72, packaging and assembly, specifically: Step S721: Apply uncured PDMS to the bottom of the PDMS tank; Step S722: Attach the PDMS small groove to the substrate and allow it to cure. Step S723: Inject electrolytes using a two-needle injection method. One needle is used to inject PBS buffer or other electrolyte solution, while the other needle is used to vent air and balance the internal and external air pressure. In step S724, after the needle is removed, the self-healing properties of PDMS automatically seal the needle hole, achieving a complete seal.

6. The OECT preparation method according to claim 5, characterized in that, The mold forming technology in steps S712 and S713 also includes CNC machining molds, laser cutting molds, injection molds or die casting molds.

7. The OECT preparation method according to claim 5, characterized in that, The assembly and connection methods in step S714 also include adhesive bonding, ultrasonic welding, mechanical snap-fitting, or threaded connection; the injection methods in step S723 also include syringe injection, microsyringe injection, microfluidic pump injection, capillary injection, vacuum injection, or pressure injection.

8. The OECT preparation method according to claim 5, characterized in that, The material used in step S715 can also be one or more of silicone rubber, polyurethane, and epoxy resin.

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