An LVDT detection circuit for an aircraft braking and steering control system

Abstract

This invention provides an LVDT (Low-Low Temperature Detection) circuit for an aircraft braking and steering control system. Based on the safety and reliability requirements of aircraft braking and steering systems and addressing the disadvantages of traditional LVDT detection methods, it creatively proposes an LVDT detection method with isolated differential excitation output and differential demodulation. This method can significantly improve the system's reliability, anti-interference capability, and accuracy. Simultaneously, it saves power consumption and cable weight. It has high engineering application value and significant potential for widespread application.

Description

Technical Field

[0001] This invention belongs to the technical field of aircraft braking and steering control systems, and specifically relates to an LVDT detection circuit for an aircraft braking and steering control system. Background Technology

[0002] With the development trend of large aircraft and more electric aircraft, the safety and reliability requirements of aircraft braking and steering control systems are getting higher and higher. Various types of LVDT sensors are used in various systems on the aircraft. LVDT sensors are mainly composed of primary coil, secondary coil, iron core, etc.

[0003] Traditional LVDT (Linear Variable Differential Sensor) detection methods mainly use highly integrated chips like the AD698 for excitation output and LVDT position demodulation. The advantage of these integrated chips is their simple principle and flexible configuration, but their disadvantages are obvious: poor accuracy, insufficient anti-interference, low reliability, insufficient excitation drive capability, and limited application range. There is another type of LVDT detection method on the market, which mainly uses a complete set of excitation and demodulation circuits built with analog devices. The excitation source of this type of LVDT detection method is mostly a single-ended sinusoidal excitation source. The three cables required for the primary side of the excitation source are a single-ended sinusoidal excitation power line, a ground return line, and a shielding cable.

[0004] Both this type of single-ended excitation output and the excitation output of integrated chips like AD698 are essentially single-ended excitation outputs. Single-ended excitation outputs are easily affected by loop ground interference. The potential difference of the primary side loop ground will be superimposed on the secondary coil of the secondary side, causing the output zero point to drift, which seriously affects the demodulation accuracy. At the same time, another major disadvantage of single-ended excitation output is that the excitation voltage is high, the system power consumption is high, and the scalability is poor. The mainstream approach on the market is to provide one excitation source to one group of LVDT sensors. When the number of LVDT sensors in the system is large, this method requires a large number of cables and detection circuits, resulting in high cost. Summary of the Invention

[0005] Purpose of the invention: To address the shortcomings of traditional LVDT detection methods, a new LVDT detection circuit for aircraft braking and steering control systems is proposed.

[0006] This invention provides an LVDT detection circuit for an aircraft braking and steering control system, comprising: an FPGA, a primary-side excitation generation circuit, and an isolated differential push-pull output circuit;

[0007] The primary-side excitation generation circuit includes: a counter, an analog switch, a low-pass filter, and a proportional amplifier;

[0008] The counter is used to receive the clock signal output by the FPGA. Each time a rising / falling edge of the clock is detected, the N-bit binary counter is incremented by 1, resulting in a cyclic count of 2. N A digital signal;

[0009] The analog switch has one output and two... N One voltage input; the analog switch operates according to a 2-cycle provided by the counter. N A digital signal is used to cyclically open the corresponding channel, so that the output of the analog switch forms a periodic stepped square wave, which is then passed through a low-pass filter and a proportional amplifier to obtain a sine wave.

[0010] The isolated differential push-pull output circuit includes: a first phase adjustment circuit, a second phase adjustment circuit, a first isolated output circuit, and a second isolated output circuit;

[0011] The first phase adjustment circuit and the second phase adjustment circuit are used to adjust the sine wave into two sine waves with a phase difference of 180°, and apply them to the two ends of the primary side of the LVDT sensor through the first isolation output circuit and the second isolation output circuit, respectively.

[0012] Optionally, the operational amplifiers of the first phase adjustment circuit and the second phase adjustment circuit use different input terminals to receive sine waves.

[0013] Optionally, the maximum voltage input of the analog switch is half the voltage required for detection by the LVDT sensor.

[0014] Optionally, the low-pass filter includes: a first second-order low-pass filter and a second second-order low-pass filter;

[0015] The first and second-order low-pass filters are used to filter out low-frequency noise, and the second and second-order low-pass filters are used to filter out high-frequency noise.

[0016] Optionally, the isolated differential push-pull output circuit may also include: an excitation differential retrieval circuit;

[0017] The excitation differential sampling circuit includes: a proportional subtraction circuit, a precision full-wave rectifier circuit, a filter circuit, and an ADC;

[0018] The two input terminals of the proportional subtraction circuit are respectively connected to two sine waves with a phase difference of 180° provided by the first phase adjustment circuit and the second phase adjustment circuit, and the output terminal is connected to the rectifier circuit to provide the subtracted sine wave.

[0019] The rectifier circuit is used to rectify the subtracted sine wave into a DC signal and provide it to the filter circuit;

[0020] The filter circuit is used to filter out noise in the DC signal and provide it to the ADC;

[0021] The ADC is used to convert DC signals into digital signals and provide them to the FPGA;

[0022] The FPGA is used to perform self-testing of the excitation applied to both ends of the primary side of the LVDT sensor based on the voltage value of the received digital signal.

[0023] Optionally, the rectifier circuit includes: operational amplifier A8B, operational amplifier A7A, diode V6, and diode V7;

[0024] The non-inverting input of op-amp A8B is connected to the output of the proportional subtraction circuit, the inverting input is connected to the output via diode V6, and the output is connected to the non-inverting input of op-amp A7A via diode V7.

[0025] The inverting input of op-amp A7A is connected to the inverting input of op-amp A8B via a rectifier resistor, and the output is connected to the filter circuit.

[0026] Optionally, the LVDT detection circuit of the aircraft braking and steering control system may also include: LVDT secondary-side demodulation circuit;

[0027] The LVDT secondary-side demodulation circuit includes: two RFI-resistant filters, an instrumentation amplifier, a rectifier circuit, a filter circuit, and an AD converter;

[0028] Each anti-RFI filter includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a third capacitor;

[0029] One end of the first resistor is connected to the common terminal of the secondary side of the LVDT sensor, and the other end is connected to the inverting input terminal of the instrumentation amplifier. One end of the second resistor is connected to the first or second acquisition terminal of the secondary side of the LVDT sensor, and the other end is connected to the non-inverting input terminal of the instrumentation amplifier.

[0030] The third resistor and the first capacitor are connected in parallel, with their two ends connected to the non-inverting input and the inverting input of the instrumentation amplifier, respectively.

[0031] One end of the fourth resistor and the second capacitor are respectively connected to the two ends of the first resistor, and the other end is grounded;

[0032] One end of the fifth resistor and one end of the third capacitor are connected to the two ends of the second resistor, respectively, and the other end is grounded;

[0033] The output of the instrumentation amplifier is connected in sequence to the rectifier circuit, the filter circuit and the AD converter, and provides the first secondary voltage signal / second secondary voltage signal acquired by the FPGA.

[0034] The FPGA is used to calculate the difference and ratio of the first secondary voltage signal and the second secondary voltage signal to obtain the LVDT displacement.

[0035] Optionally, an isolated differential push-pull output circuit applies two sine waves with a phase difference of 180° to the primary terminals of multiple LVDT sensors via a first isolation output circuit and a second isolation output circuit, respectively.

[0036] Beneficial effects:

[0037] To address the shortcomings of traditional LVDT (Low-Low Temperature Detection) methods, this invention proposes an LVDT detection circuit for aircraft braking and steering control systems. This circuit innovatively introduces an isolated primary-side differential excitation output, which also features an excitation output self-test function. The circuit eliminates the need for a ground return wire at the excitation end, improving noise immunity in electric / magnetic field environments. This significantly enhances the system's anti-interference capability. Furthermore, the output excitation voltage is only half that of a single-ended excitation output, reducing coil current by 50% and lowering system power consumption. The differential output format saves approximately 30% of the total aircraft cabling. The isolated differential output also increases the maximum transmission distance within the aircraft, facilitating better onboard wiring. The demodulation circuit utilizes an anti-RFI filter and instrumentation amplifier with differential sampling, providing better immunity to common-mode and differential-mode noise. Combined with a high-precision AD converter and acquisition algorithm, the system's demodulation accuracy is improved to ±0.1%FS, several orders of magnitude higher than the traditional ±0.5%FS. This method features redundant backup schemes, enhancing overall system reliability. Furthermore, it is highly scalable; adjusting the resistors in the differential push-pull amplifier circuit can increase the system's output capability, meeting the detection needs of more LVDT sensors. Modifying the FPGA output counter frequency can also accommodate LVDT detection with a wider bandwidth. Therefore, this invention possesses high reliability, anti-interference capabilities, and accuracy. It also saves power and weight, making it highly valuable for engineering applications and significant for wider adoption. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a block diagram of the LVDT detection circuit.

[0040] Figure 2 This is the primary-side excitation generation circuit for the LVDT;

[0041] Figure 3 This is a differential push-pull output circuit with primary-sideband isolation for LVDT.

[0042] Figure 4This is the secondary demodulation circuit for an LVDT. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] The features and illustrative embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific setups and methods set forth below, but covers any improvements, substitutions, and modifications to structures, methods, and devices without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description to avoid unnecessarily obscuring the invention.

[0045] In the description of this invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing and simplifying the invention, and should not be construed as limiting the invention. Furthermore, the use of ordinal numbers (e.g., "first and second," etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0046] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly, encompassing both direct connection and indirect connection via an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0047] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other, and the various embodiments can be referenced and cited in each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0049] This invention provides an LVDT detection circuit for an aircraft braking and steering control system, comprising: an FPGA, a primary-side excitation generation circuit, and an isolated differential push-pull output circuit;

[0050] The primary-side excitation generation circuit includes: a counter, an analog switch, a low-pass filter, and a proportional amplifier;

[0051] The counter is used to receive the clock signal output by the FPGA. Each time a rising / falling edge of the clock is detected, the N-bit binary counter is incremented by 1, resulting in a cyclic count of 2. N A digital signal;

[0052] The analog switch has one output and two... N One voltage input; the analog switch operates according to a 2-cycle provided by the counter. N A digital signal is used to cyclically open the corresponding channel, so that the output of the analog switch forms a periodic stepped square wave, which is then passed through a low-pass filter and a proportional amplifier to obtain a sine wave.

[0053] The isolated differential push-pull output circuit includes: a first phase adjustment circuit, a second phase adjustment circuit, a first isolated output circuit, and a second isolated output circuit;

[0054] The first phase adjustment circuit and the second phase adjustment circuit are used to adjust the sine wave into two sine waves with a phase difference of 180°, and apply them to the two ends of the primary side of the LVDT sensor through the first isolation output circuit and the second isolation output circuit, respectively.

[0055] Optionally, the operational amplifiers of the first phase adjustment circuit and the second phase adjustment circuit use different input terminals to receive sine waves.

[0056] Optionally, the maximum voltage input of the analog switch is half the voltage required for detection by the LVDT sensor.

[0057] Optionally, the low-pass filter includes: a first second-order low-pass filter and a second second-order low-pass filter;

[0058] The first and second-order low-pass filters are used to filter out low-frequency noise, and the second and second-order low-pass filters are used to filter out high-frequency noise.

[0059] Optionally, the isolated differential push-pull output circuit may also include: an excitation differential retrieval circuit;

[0060] The excitation differential sampling circuit includes: a proportional subtraction circuit, a precision full-wave rectifier circuit, a filter circuit, and an ADC;

[0061] The two input terminals of the proportional subtraction circuit are respectively connected to two sine waves with a phase difference of 180° provided by the first phase adjustment circuit and the second phase adjustment circuit, and the output terminal is connected to the rectifier circuit to provide the subtracted sine wave.

[0062] The rectifier circuit is used to rectify the subtracted sine wave into a DC signal and provide it to the filter circuit;

[0063] The filter circuit is used to filter out noise in the DC signal and provide it to the ADC;

[0064] The ADC is used to convert DC signals into digital signals and provide them to the FPGA;

[0065] The FPGA is used to perform self-testing of the excitation applied to both ends of the primary side of the LVDT sensor based on the voltage value of the received digital signal.

[0066] Optionally, the rectifier circuit includes: operational amplifier A8B, operational amplifier A7A, diode V6, and diode V7;

[0067] The non-inverting input of op-amp A8B is connected to the output of the proportional subtraction circuit, the inverting input is connected to the output via diode V6, and the output is connected to the non-inverting input of op-amp A7A via diode V7.

[0068] The inverting input of op-amp A7A is connected to the inverting input of op-amp A8B via a rectifier resistor, and the output is connected to the filter circuit.

[0069] Optionally, the LVDT detection circuit of the aircraft braking and steering control system may also include: LVDT secondary-side demodulation circuit;

[0070] The LVDT secondary-side demodulation circuit includes: two RFI-resistant filters, an instrumentation amplifier, a rectifier circuit, a filter circuit, and an AD converter;

[0071] Each anti-RFI filter includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a third capacitor;

[0072] One end of the first resistor is connected to the common terminal of the secondary side of the LVDT sensor, and the other end is connected to the inverting input terminal of the instrumentation amplifier. One end of the second resistor is connected to the first or second acquisition terminal of the secondary side of the LVDT sensor, and the other end is connected to the non-inverting input terminal of the instrumentation amplifier.

[0073] The third resistor and the first capacitor are connected in parallel, with their two ends connected to the non-inverting input and the inverting input of the instrumentation amplifier, respectively.

[0074] One end of the fourth resistor and the second capacitor are respectively connected to the two ends of the first resistor, and the other end is grounded;

[0075] One end of the fifth resistor and one end of the third capacitor are connected to the two ends of the second resistor, respectively, and the other end is grounded;

[0076] The output of the instrumentation amplifier is connected in sequence to the rectifier circuit, the filter circuit and the AD converter, and provides the first secondary voltage signal / second secondary voltage signal acquired by the FPGA.

[0077] The FPGA is used to calculate the difference and ratio of the first secondary voltage signal and the second secondary voltage signal to obtain the LVDT displacement.

[0078] Optionally, an isolated differential push-pull output circuit applies two sine waves with a phase difference of 180° to the primary terminals of multiple LVDT sensors via a first isolation output circuit and a second isolation output circuit, respectively.

[0079] To address the aforementioned technical problems, this invention provides a novel LVDT detection circuit for an aircraft braking and steering control system. The core logic of this circuit is... Figure 1 The principle block diagram of the LVDT detection system, as follows: Figure 1When the system detects that a specific LVDT sensor signal from the aircraft braking and steering system needs to be detected, a set of two LVDT sensors serve as redundancy backups. For example, when the LVDT sensor managing the braking system needs to be detected, the CPU+FPGA in the Braking and Steering Control Unit (CPM board) outputs the counter clock signal required by the LVDT primary-side excitation generation circuit. The clock frequency is approximately 24kHz. The counter output is connected to a sine wave generator, which converts the input stepped square wave signal into a sine wave signal. The output of the sine wave generator is then filtered by a second-order low-pass filter to generate the amplitude and sum of the signals. A periodically stable sine wave is generated. The first second-order low-pass filter primarily filters out high-frequency signals, while the second second-order low-pass filter filters out relatively low-frequency signals. After passing through the low-frequency filter, the amplitude of the sine wave is further amplified by a proportional amplifier circuit. The amplified sine signal is then output to a differential push-pull amplifier circuit. The push-pull circuit innovatively utilizes parallel operation amplifier outputs to enhance the overall circuit's output capability. The system's maximum output excitation current is approximately 60mA, which can simultaneously meet the primary-side excitation current requirements of three types of LVDT sensor signals. The sine signal output from the proportional amplifier circuit is simultaneously supplied to two sets of phase... By adjusting the non-inverting and inverting terminals of the operational amplifiers, the outputs of the two operational amplifiers become a set of sinusoidal signals with equal amplitude and a 180° phase difference. The RMS effective value of the sinusoidal voltage output from the proportional amplifier circuit to the non-inverting terminal of the operational amplifier is 3.5V, and the RMS effective value of the sinusoidal voltage output from the proportional amplifier circuit to the inverting terminal of the operational amplifier is also 3.5V, with a 180° phase difference. Thus, the output of the differential push-pull amplifier circuit is a set of differential sinusoidal signals with an RMS effective value of 3.5V, a 180° phase difference, and a magnetizing current of approximately 60mA. The output of the differential push-pull amplifier circuit is fed to the differential isolation input. The differential isolation circuit utilizes the isolation characteristics of the opto-MOS to achieve the primary-side excitation output of the LVDT and the isolation between the excitation output signal and the control signal of the CPU+FPGA control output, effectively ensuring the safety of the CPU+FPGA. When the CPU+FPGA outputs a high-level control signal to the excitation output control circuit, the opto-MOS is turned on, and the differential isolation output circuit outputs a set of sinusoidal AC signals to the LVDT sensors S1 and S2 at the electromechanical system accessory end. The effective value of the primary-side excitation differential voltage RMS of the LVDT sensor will be 7V, with a frequency of 3kHz. To check if the primary excitation signal of the LVDT is normal, an output self-test is required. A set of differential signals amplified by differential push-pull is used to achieve excitation output BIT self-test through the excitation differential retrieval circuit. The excitation differential retrieval circuit mainly consists of an equal proportional difference operation circuit, a full-wave precision rectifier circuit, a second-order low-pass filter circuit, and a high-precision AD conversion circuit. When the effective value of the excitation signal output by the CPU+FPGA self-test meets 3.5V±5%, the excitation signal of the system is considered normal. In this way, the excitation output and retrieval self-test logic of the LVDT is completed.

[0080] Next, the system executes the demodulation logic of the LVDT sensor's secondary side. LVDT demodulation mainly determines the LVDT sensor's position by calculating the difference and ratio of the secondary side voltages. The secondary side demodulation circuits of the two LVDT sensors are identical. Taking the first one as an example, it detects the voltage of the sensor's secondary side S1_PHASE_A to COM1. The sinusoidal signal at the A terminal of the secondary side is filtered by an anti-RFI filter to reduce common-mode and differential-mode interference in the circuit, effectively reducing radio frequency interference and improving the system's acquisition accuracy. The output of the anti-RFI filter is given to the differential input of the instrumentation amplifier. After proportional amplification, the instrumentation amplifier outputs the sinusoidal signal at the A terminal of the secondary side proportionally. The purpose of using an instrumentation amplifier is to leverage its characteristics in differential detection, such as ultra-high common-mode rejection, high-precision gain control, ultra-high input impedance, ultra-low noise, and offset voltage, to greatly improve the accuracy and reliability of the demodulation circuit. The output of the instrumentation amplifier is rectified by a precision full-wave rectifier to convert a sine wave to a full-wave positive value. The output of the precision full-wave rectifier circuit is then converted from AC value to average value by a second-order low-pass filter circuit. The output of the second-order low-pass filter is then sent to a high-precision AD converter circuit to convert analog quantity to digital quantity. Finally, the high-precision AD output is sent to the FPGA. The FPGA internally processes the data using a logic algorithm to calculate the voltage at terminal A, thus completing the acquisition of the voltage at terminal A. Similarly, after completing the voltage acquisition at terminal B of LVDT sensor S1 through the above steps, and after the voltage acquisition at terminals A and B of LVDT sensor S1 is completed, the difference and ratio are calculated inside the FPGA to complete the LVDT sensor position demodulation. The CPU+FPGA uses the demodulated data and the output excitation self-test data to complete the fault detection and position demodulation of LVDT sensor, such as short circuit and open circuit. LVDT sensor S2 is a redundant backup for the aircraft braking and steering system. When sensor 1 fails, sensor 2 serves as its backup. At the same time, if the difference between the demodulated values ​​of sensor 1 and 2 is too large, The aircraft braking and steering system will downgrade or discard the data from this set of sensors because the numerical values ​​demodulated from the LVDT sensor position can be used to calculate the displacement length of the brake actuator. The displacement length of the brake actuator is proportional to the brake pressure. By judging the brake pressure and wheel speed of the left and right landing gear S1 and S2 and other related sensor signals, the aircraft braking system can achieve precise braking control and anti-skid effect. If the data difference between the left and right landing gear wheels is too large, the aircraft is at risk of skidding and loss of control. Therefore, the sensors of the aircraft braking and steering system must be paired up as backups for each other to ensure the safety of the aircraft.

[0081] The other two LVDT sensors in the aircraft braking and steering system operate on the same principle as the LVDT sensor in the brake. The steering input LVDT is mainly used to provide the pilot with steering commands. The braking and steering system combines the commands and other data to calculate the correct command position of the steering servo valve. The LVDT sensor inside the steering servo valve mainly provides feedback on the position of the valve core to ensure high-precision valve control. The hardware detection methods of these three LVDT sensors in the aircraft braking and steering system are basically the same, and they are all redundant backups, which greatly improves the safety and reliability of the system.

[0082] like Figure 1 The principle block diagram of the LVDT testing system has already been introduced in the previous section, explaining how the LVDT testing method for aircraft braking and steering systems works. The following section mainly focuses on... Figures 2-4 The present invention will be described in detail in terms of how it is specifically implemented.

[0083] like Figure 2 This is the primary-side excitation generation circuit for the LVDT. The circuit mainly consists of counter U3, analog switch U4, operational amplifiers A5B, A4B, and A4A, resistors, capacitors, and a power supply. Counter U3 primarily converts the LVDT_CLK clock signal output from the FPGA into a digital signal ranging from 000 to 111. Analog switch U4 sequentially opens the analog switch paths of channels S1-S8 according to the digital conversion signal from the counter. Thus, the output of analog switch U4 is sequentially 0, -3V, -5V, -3V, 0V, +3V, +5V, +3V, with each channel having a frequency interval of approximately 24kHz. This cycle continues, resulting in a stepped square wave with a peak-to-peak value of 10V and a period of approximately 3kHz. This stepped square wave output from the analog switch is converted into a sine wave after passing through a second-order low-pass filter composed of A5B. However, this sine wave signal still has considerable noise and glitches. The first second-order low-pass filter primarily filters out high-frequency signals, and its cutoff frequency is... The output of the first second-order low-pass filter is fed into a second second-order low-pass filter composed of A1B, with a cutoff frequency of approximately 600kHz. The frequency is approximately 3.5kHz. After passing through the second second-order low-pass filter, the amplitude and accuracy of the sinusoidal signal output are quite stable. The output of the second second-order low-pass filter is fed to a proportional amplifier circuit composed of A4A amplifiers. The proportional amplifier circuit mainly amplifies the output sinusoidal signal effectively as a whole. The output signal REFAC_SINE of the A4A amplifier is a sinusoidal signal with stable amplitude. This REFAC_SINE signal is given to... Figure 3 LVDT primary-side isolated differential push-pull output circuit.

[0084] Figure 3 The primary-sideband isolated differential push-pull output circuit of the LVDT mainly consists of operational amplifiers A6A, A6B, A9A, and A9B, opto-MOS relays U5A and U5B, as well as resistors, capacitors, and diodes. Operational amplifiers A6A and A6B form a proportional push-pull amplifier circuit, primarily amplifying the input REFAC_SINE signal in an inverting proportional push-pull manner. The amplified sine wave signal has an effective RMS value of approximately 3.5V, and the signal is REFAC_SINE_N. R42 and R48 are the main components that increase the push-pull output current capability, with an excitation current value of approximately 60mA. A single op-amp A6A provides a proportional push-pull capability of approximately 30mA. Two op-amps connected in parallel increase the output capability. Op-amps A9A and A9B form a positive proportional push-pull amplifier circuit, primarily amplifying the input REFAC_SINE signal in a positive proportional push-pull manner. The amplified sine wave signal has an effective RMS value of approximately 3.5V, and the signal is REFAC_SINE_P. R52 and R66 are the main components that increase the push-pull output current capability, with an excitation current of approximately 60mA. A single op-amp A9A provides a proportional push-pull capability of approximately 30mA, and two op-amps connected in parallel increase the output capability. Thus, two sets of... Combining proportional push-pull amplifier circuits forms a differential push-pull amplifier circuit. The output differential signals REFAC_SINE_P and REFAC_SINE_N of the differential push-pull amplifier circuit are a set of sinusoidal signals with equal amplitude and a 180° phase difference. The effective value (RMS) of the REFAC_SINE_P signal is 3.5V, and the effective value (RMS) of the REFAC_SINE_N signal is 3.5V, but with a 180° phase difference compared to REFAC_SINE_P. This set of differential excitation signals is output to the differential isolation output circuit of the opto-MOS relay composed of U5A and U5B. When the LVDT_CMD signal at the control terminal of the OS relay is high, it indicates that the FPGA outputs an excitation control command, transistor Q1 is turned on, and subsequently the primary diodes of opto-MOS relays U5A and U5B are turned on, as are the secondary diodes of opto-MOS relays U5A and U5B. The differential excitation signal is output to the primary coil of the LVDT sensor via the opto-MOS relay. The differential isolation output signals are EXC_LVDT_L and EXC_LVDT_H. The effective value (RMS) of this differential signal is 3.5V, the phase difference is 180°, and the frequency is 3kHz.

[0085] Figure 3In the LVDT primary-side isolated differential push-pull output circuit, one set of excitation differential signals is output to the primary coil of the LVDT sensor via an opto-MOS relay. Another set of REFAC_SINE_P and REFAC_SINE_N differential signals undergo a bit-test of the output excitation signal via an excitation differential retrieval circuit. This circuit mainly consists of operational amplifiers A8A, A8B, A7A, and A7B, a high-precision ADC IC2, resistors, capacitors, and diodes. A proportional subtraction circuit composed of operational amplifiers A8A performs the self-test of the output REFAC_SINE_P and REFAC_SINE_N differential signals. The output of the proportional subtraction circuit is fed to a precision full-wave rectifier circuit composed of operational amplifiers A8B and A7A, diodes V6 and V7. The output of the precision full-wave rectifier circuit is a sinusoidal signal waveform with a positive full-wave amplitude. This output is then converted from a sinusoidal AC signal to an average-valued DC signal via a second-order low-pass filter circuit composed of A7B. The output LVDT_MUX signal of op-amp A7B is a DC signal with an average value of 3.5V. The LVDT_MUX signal is sent to IC2 high-precision ADC. IC2 realizes the conversion of analog to digital signal. The output of IC2 high-precision ADC is a set of SPI signals. The output signal of IC2 high-precision ADC is sent to FPGA. FPGA completes the self-test of primary-side excitation output voltage according to internal high-precision ADC analog signal acquisition algorithm. When the detected voltage exceeds 3.5V by more than 5±%, it is considered that the excitation output voltage is unstable and the excitation voltage reliability is insufficient.

[0086] Figure 4 The secondary-side demodulation circuit of the LVDT mainly consists of instrumentation amplifiers U1 and U2, operational amplifiers A1B, A2A, A1A, A3B, A3A, and A2B, a high-precision ADC IC1, resistors, capacitors, and diodes. When detecting the voltage at terminal A of the secondary side of the LVDT sensor, the S1_PHASE_A signal and COM1 signal output by the secondary-side sensor are passed through an anti-RFI filter and then output to the differential input terminal of instrumentation amplifier U1. Instrumentation amplifier U1 only performs proportional amplification. Instrumentation amplifiers are basically a must-have in the field of differential signal acquisition.

[0087] The advantages of instrumentation amplifiers are that their ultra-high common-mode rejection, high-precision gain control, ultra-high input impedance, ultra-low noise, and ultra-low offset voltage in differential detection greatly improve the accuracy and reliability of demodulation circuits. The output of the instrumentation amplifier is fed to the subsequent precision full-wave rectifier circuit. The input sinusoidal signal is converted into a positive full-wave signal after passing through the precision full-wave rectifier circuit composed of operational amplifiers A1B, operational amplifiers A2A, diodes V1 and V2, etc. The output of the precision full-wave rectifier circuit is fed to the second-order low-pass filter circuit composed of A1A. The second-order low-pass filter circuit realizes the conversion of the sinusoidal AC signal to the average DC signal. The converted signal LVDT_S1_PHASE_A_MUX voltage is a DC signal. The LVDT_S1_PHASE_A_MUX signal is fed to the IC1 high-precision ADC. IC1 realizes the conversion of analog to digital. The output of the IC1 high-precision ADC is a set of SPI signals. The output signal of the IC1 high-precision ADC is fed to the FPGA. The FPGA completes the calculation of the demodulation voltage output at the secondary A end according to the internal high-precision ADC analog signal acquisition algorithm.

[0088] Similarly, when detecting the voltage at terminal B of the secondary side of the LVDT sensor, the S1_PHASE_B signal and COM1 signal output by the secondary side sensor are passed through an anti-RFI filter and then output to the differential input of instrumentation amplifier U2. Instrumentation amplifier U2 only performs proportional amplification. Instrumentation amplifiers are basically a must-have in the field of differential signal acquisition. The advantages of instrumentation amplifiers are that their ultra-high common-mode rejection, high-precision gain control, ultra-high input impedance, ultra-low noise, and ultra-low offset voltage in differential detection greatly improve the accuracy and reliability of the demodulation circuit. The output of the instrumentation amplifier is then fed to the subsequent precision full-wave rectifier circuit. The input sine wave signal is rectified by a precision full-wave rectifier circuit composed of operational amplifier A3B, operational amplifier A3A, diode V3, diode V4, etc. After being rectified by the full-wave rectifier circuit, the signal becomes a positive full-wave signal. The output of the precision full-wave rectifier circuit is fed to the second-order low-pass filter circuit composed of A2B. The second-order low-pass filter circuit realizes the conversion of the sinusoidal AC signal to the average value DC signal. The converted signal LVDT_S1_PHASE_B_MUX is a DC signal. The LVDT_S1_PHASE_B_MUX signal is fed to the IC1 high-precision ADC. IC1 realizes the conversion of analog to digital. The output of IC1 high-precision ADC is a set of SPI signals. The output signal of IC1 high-precision ADC is fed to the FPGA. The FPGA completes the calculation of the demodulation voltage output at the secondary side B terminal according to the internal high-precision ADC analog signal acquisition algorithm, with a detection accuracy of ±0.1%FS.

[0089] After the voltages at terminals A and B of LVDT sensors S1 and S2 are acquired, the difference and ratio are calculated within the FPGA to demodulate the LVDT sensor position. The CPU and FPGA then use the demodulated data and output excitation self-test data to perform fault detection and position demodulation of the LVDT sensors. LVDT sensor S2 serves as a redundant backup for the aircraft braking and steering system. Its LVDT detection method is consistent with that of LVDT sensor S1. When sensor 1 fails, sensor 2 acts as a backup. Furthermore, if the difference between the demodulated values ​​of sensor 1 and sensor 2 is too large... When the pressure is high, the aircraft braking and steering system will downgrade or discard the data from this set of sensors. This is because the system can calculate the displacement length of the brake actuator by demodulating the position of the LVDT sensor. The displacement length of the brake actuator is proportional to the brake pressure. By judging the brake pressure and wheel speed of the left and right landing gear S1 and S2 and other related sensor signals, the aircraft braking system can achieve precise braking control and anti-skid effect. If the data difference between the left and right landing gear wheels is too large, the aircraft is at risk of skidding and loss of control. Therefore, the sensors of the aircraft braking and steering system must be paired up as backups for each other to ensure the safety of the aircraft.

[0090] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. An LVDT detection circuit for an aircraft braking and steering control system, characterized in that, include: FPGA, primary-side excitation generation circuit, and isolated differential push-pull output circuit; The primary-side excitation generation circuit includes: a counter, an analog switch, a low-pass filter, and a proportional amplifier; The counter is used to receive the clock signal output by the FPGA. Each time a rising / falling edge of the clock is detected, the N-bit binary counter is incremented by 1 to obtain 2N cyclic digital signals. The analog switch has one output and 2N voltage inputs; the analog switch cyclically opens the corresponding channel according to the 2N digital signals provided by the counter, so that the output of the analog switch forms a periodic stepped square wave, which is then passed through a low-pass filter and a proportional amplifier to obtain a sine wave; The isolated differential push-pull output circuit includes: a first phase adjustment circuit, a second phase adjustment circuit, a first isolated output circuit, and a second isolated output circuit; The first phase adjustment circuit and the second phase adjustment circuit are used to adjust the sine wave into two sine waves with a phase difference of 180°, and apply them to the two ends of the primary side of the LVDT sensor through the first isolation output circuit and the second isolation output circuit, respectively. The isolated differential push-pull output circuit also includes: an excitation differential retrieval circuit; The excitation differential sampling circuit includes: a proportional subtraction circuit, a precision full-wave rectifier circuit, a filter circuit, and an ADC; The two input terminals of the proportional subtraction circuit are respectively connected to two sine waves with a phase difference of 180° provided by the first phase adjustment circuit and the second phase adjustment circuit, and the output terminal is connected to the rectifier circuit to provide the subtracted sine wave. The rectifier circuit is used to rectify the subtracted sine wave into a DC signal and provide it to the filter circuit; The filter circuit is used to filter out noise in the DC signal and provide it to the ADC; The ADC is used to convert DC signals into digital signals and provide them to the FPGA; The FPGA is used to perform self-testing of the excitation applied to both ends of the primary side of the LVDT sensor based on the voltage value of the received digital signal.

2. The LVDT detection circuit of the aircraft braking and steering control system according to claim 1, characterized in that, The operational amplifiers in the first phase adjustment circuit and the second phase adjustment circuit use different input terminals to receive sine waves.

3. The LVDT detection circuit of the aircraft braking and steering control system according to claim 1, characterized in that, The maximum voltage input of the analog switch is half the voltage required for detection by the LVDT sensor.

4. The LVDT detection circuit of the aircraft braking and steering control system according to claim 1, characterized in that, Low-pass filters include: first-order and second-order low-pass filters; The first and second-order low-pass filters are used to filter out low-frequency noise, and the second and second-order low-pass filters are used to filter out high-frequency noise.

5. The LVDT detection circuit of the aircraft braking and steering control system according to claim 1, characterized in that, The rectifier circuit includes: operational amplifier A8B, operational amplifier A7A, diode V6, and diode V7; The non-inverting input of op-amp A8B is connected to the output of the proportional subtraction circuit, the inverting input is connected to the output via diode V6, and the output is connected to the non-inverting input of op-amp A7A via diode V7. The inverting input of op-amp A7A is connected to the inverting input of op-amp A8B via a rectifier resistor, and the output is connected to the filter circuit.

6. The LVDT detection circuit of the aircraft braking and steering control system according to claim 1, characterized in that, Also includes: LVDT secondary-side demodulation circuit; The LVDT secondary-side demodulation circuit includes: two RFI-resistant filters, an instrumentation amplifier, a rectifier circuit, a filter circuit, and an AD converter; Each anti-RFI filter includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a third capacitor; One end of the first resistor is connected to the common terminal of the secondary side of the LVDT sensor, and the other end is connected to the inverting input terminal of the instrumentation amplifier. One end of the second resistor is connected to the first or second acquisition terminal of the secondary side of the LVDT sensor, and the other end is connected to the non-inverting input terminal of the instrumentation amplifier. The third resistor and the first capacitor are connected in parallel, with their two ends connected to the non-inverting input and the inverting input of the instrumentation amplifier, respectively. One end of the fourth resistor and the second capacitor are respectively connected to the two ends of the first resistor, and the other end is grounded; One end of the fifth resistor and one end of the third capacitor are connected to the two ends of the second resistor, respectively, and the other end is grounded; The output of the instrumentation amplifier is connected in sequence to the rectifier circuit, the filter circuit and the AD converter, and provides the first secondary voltage signal / second secondary voltage signal acquired by the FPGA. The FPGA is used to calculate the difference and ratio of the first secondary voltage signal and the second secondary voltage signal to obtain the LVDT displacement.

7. The LVDT detection circuit of the aircraft braking and steering control system according to claim 1, characterized in that, The isolated differential push-pull output circuit applies two sine waves with a phase difference of 180° to the primary terminals of multiple LVDT sensors via the first isolation output circuit and the second isolation output circuit, respectively.

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