A wide-voltage, low-power enable reference voltage generation circuit

Abstract

This invention relates to the field of power management chip technology in analog integrated circuits, aiming to solve the problems of high power consumption due to the bandgap reference still operating when turned off in traditional circuits, complex circuitry required for wide voltage adaptation, and the contradiction between accuracy and power consumption. The solution includes: a startup bias module, a reference voltage difference generation module, a current mirror and current distribution module, a reference voltage output module, a filter stabilization module, and an enable comparison control module; it eliminates the need for a complex secondary buck circuit, controlling the start and stop of subsequent circuits (including the bandgap reference) by comparing a local reference voltage with an external enable signal. The circuit has a wide input voltage range of 10V~100V, a shutdown current of less than 1μA, and a reference voltage temperature drift of less than 30ppm / ℃, simplifying the structure while achieving low power consumption and high accuracy, meeting the requirements of high reliability and low energy loss for power management chips.

Description

Technical Field

[0001] This invention relates to the field of power management chip technology in analog integrated circuits, and in particular to a wide-voltage, low-power enable reference voltage generation circuit. Background Technology

[0002] With the continuous improvement of power system reliability and energy efficiency requirements in fields such as automotive electronics and industrial control, the power supply bus voltage of power management chips is upgrading from the traditional 12V to 48V and even higher levels. Wide voltage (e.g., 10V~100V) input has become one of the core technical requirements of power management chips. As a key core module of power management chips, the performance of the reference voltage generation circuit directly determines the start-stop control accuracy and overall power consumption level of subsequent circuits (such as bandgap references and power drive circuits). A high-quality enable reference voltage not only needs to remain stable over a wide voltage range, but also needs to be designed with low power consumption to meet the energy efficiency standards of scenarios such as automotive electronics and portable devices. Therefore, the development of a wide voltage adaptability, low power consumption, and high precision enable reference voltage generation circuit is of great practical significance for promoting the development of power management chips towards high reliability and low energy loss.

[0003] Currently, in the industry, the enable reference voltage of traditional power management chips mostly relies on bandgap reference circuits for generation. The bandgap reference achieves high-precision voltage output through a temperature compensation mechanism, but as an independent module, it still needs to operate to continuously provide the reference voltage even when the chip is enabled and disabled, resulting in high turn-off power consumption. Existing 100V-class wide-voltage power management chips generally have turn-off currents exceeding 10μA, which is insufficient for low-power scenarios. To reduce turn-off power consumption, some solutions attempt to optimize by reducing the operating current of the bandgap reference. However, this approach disrupts the current balance within the bandgap reference, leading to decreased reference voltage accuracy (such as increased temperature drift), creating a contradiction between "power reduction" and "accuracy assurance." Simultaneously, traditional wide-voltage input chips require complex startup circuits and secondary buck modules to stabilize the internal bias in order to adapt to high input voltages. This not only increases the chip's design complexity and area cost but may also introduce additional noise interference, affecting the stability of the reference voltage. Summary of the Invention

[0004] To address the problems existing in the background art, the present invention provides a wide voltage and low power enable reference voltage generation circuit, including: a startup bias module, a reference voltage difference generation module, a current mirror and current distribution module, a reference voltage output module, a filter stabilization module, and an enable comparison control module.

[0005] The startup bias module is used to provide the initial bias current for the reference differential pressure generation module, and at the same time, it works with the current mirror and current distribution module to establish the initial working state.

[0006] The reference voltage difference generation module is used to generate a stable emitter voltage difference ΔVBE and generate a reference current based on the emitter voltage difference ΔVBE.

[0007] The current mirror and current distribution module are used to mirror the reference current generated by the reference voltage difference generation module in a 1:1:1 ratio, output a stable mirror current IO, and transmit its own bias node voltage to the filter stabilization module.

[0008] The reference voltage output module generates an initial reference voltage VOUT based on the mirror current IO output by the current mirror and the current distribution module, and transmits the initial reference voltage VOUT to the filter stabilization module.

[0009] The filtering and stabilization module is used to filter and reduce noise on the bias node voltage and initial reference voltage VOUT of the current mirror and current distribution module, feed back the stabilized bias node voltage to the current mirror and current distribution module, and transmit the stabilized initial reference voltage VOUT to the enable comparison control module.

[0010] The enable comparator control module receives the external enable signal EN and the stabilized initial reference voltage VOUT, and controls the on / off state of the subsequent circuitry by comparing and outputting the control signal EN_DRIVER.

[0011] The present invention has at least the following beneficial effects

[0012] This invention precisely addresses the core requirement of automotive electronics and other fields for power management chips with a wide input voltage range of 10V to 100V. By simplifying the startup bias module structure and eliminating the complex secondary buck circuit of traditional wide-voltage chips, it reduces design complexity and area cost. Furthermore, it overcomes the limitation of traditional solutions where the bandgap reference continues to operate even when it is off—through a novel architecture of "local reference voltage generation + enable comparison control," it can completely shut down subsequent circuits (including the bandgap reference) when the chip is off, thus completely solving the problem of high power consumption during shutdown in traditional solutions. Simultaneously, through the collaborative design of the reference voltage difference generation module and the filter stabilization module, it effectively avoids the industry contradiction of "reducing power consumption at the expense of accuracy." Ultimately, it achieves multiple technical advantages of wide voltage adaptation, low power consumption, high accuracy, and structural simplification, meeting the application requirements of power management chips in high-reliability, low-energy-loss scenarios. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the circuit structure of the present invention;

[0014] Figure 2 This is a schematic diagram of the shut-off current after the application of the present invention;

[0015] Figure 3This is a schematic diagram illustrating the enable / disable reference voltage accuracy of the present invention. Detailed Implementation

[0016] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0017] Please see Figure 1 The present invention provides a wide voltage and low power enable reference voltage generation circuit, including: a start-up bias module, a reference voltage difference generation module, a current mirror and current distribution module, a reference voltage output module, a filter stabilization module, and an enable comparison control module.

[0018] The startup bias module is used to provide the initial bias current for the reference differential pressure generation module, and at the same time, it works with the current mirror and current distribution module to establish the initial working state.

[0019] The reference voltage difference generation module is used to generate a stable emitter voltage difference ΔVBE and generate a reference current based on the emitter voltage difference ΔVBE.

[0020] The current mirror and current distribution module are used to mirror the reference current generated by the reference voltage difference generation module in a 1:1:1 ratio, output a stable mirror current IO, and transmit its own bias node voltage to the filter stabilization module.

[0021] The reference voltage output module generates an initial reference voltage VOUT based on the mirror current IO output by the current mirror and the current distribution module, and transmits the initial reference voltage VOUT to the filter stabilization module.

[0022] The filtering and stabilization module is used to filter and reduce noise on the bias node voltage and initial reference voltage VOUT of the current mirror and current distribution module, feed back the stabilized bias node voltage to the current mirror and current distribution module, and transmit the stabilized initial reference voltage VOUT to the enable comparison control module.

[0023] The enable comparator control module receives the external enable signal EN and the stabilized initial reference voltage VOUT, and controls the opening or closing of the subsequent circuitry of the chip by comparing and outputting the control signal EN_DRIVER.

[0024] Preferably, the startup bias module includes: NFET transistors MN1 and MN2, PFET transistors MP1 and MP2, and resistor R1;

[0025] The gate of MN1 is connected to SGND, the drain of MN1 is connected to the signal input terminal VIN, and the source of MN1 is electrically connected to one end of R1.

[0026] The other end of R1 is electrically connected to the source of MP1 and the source of MP2, respectively.

[0027] The gates of MP1 and MP2 are both connected to SGND. The drains of MP1 and MP2 together form the output terminal of the startup bias module, which is electrically connected to the input terminal of the reference voltage difference generation module.

[0028] The gate of MN2 is connected to SGND, the drain of MN2 is electrically connected to the control terminal of the current mirror and current distribution module, and the source of MN2 is electrically connected to the intermediate node of the reference voltage difference generation module.

[0029] Preferably, the reference differential pressure generating module includes: transistors N1, N2 and N3, and resistors R2 and R3;

[0030] After the collector and base of N1 are connected together, they are electrically connected to the drain of MP1 and the base of N2, respectively.

[0031] The emitter of N1 is electrically connected to the emitter of N3, one end of R3, and the first controlled terminal of the current mirror and current distribution module, respectively.

[0032] The collector of N2 is electrically connected to the drain of MP2 and the base of N3, respectively, and the emitter of N2 is electrically connected to one end of R2.

[0033] The other end of R2 and the other end of R3 are both connected to SGND; the collector of N3 is electrically connected to the source of MN2;

[0034] The upper end of R3 constitutes the first output terminal of the reference voltage difference generation module, which is used to output the emitter voltage difference ΔVBE;

[0035] The emitter of N3 forms the second output terminal of the reference differential voltage generation module, which is used to output the reference current.

[0036] Preferably, the area ratio of N1 to N2 is 4:1.

[0037] Preferably, the current mirror and current distribution module includes: PFET transistors MP3, MP4, MP5, MP6, MP7 and MP8;

[0038] The gates of MP3, MP4, MP6, MP7, MP8, MP5, and the drain of MP5 are connected together and then electrically connected to the drain of MN2 and the first input terminal of the filter stabilization module, respectively.

[0039] The source terminals of MP3, MP4, and MP7 are all connected to the signal input terminal VIN.

[0040] The drain of MP3 is electrically connected to the source of MP5; the drain of MP4 is electrically connected to the source of MP6.

[0041] The drain of MP6 is electrically connected to the emitter of N1; the drain of MP7 is electrically connected to the source of MP8.

[0042] The drain of the MP8 forms the output terminal of the current mirror and current distribution module, and is electrically connected to the input terminal of the reference voltage output module.

[0043] Preferably, the reference voltage output module includes a transistor N4 and a resistor R4;

[0044] The base and collector of N4 are connected together and then electrically connected to one end of R4.

[0045] The other end of R4 is electrically connected to the drain of MP8, the second input terminal of the filter stabilization module, and the VOUT port, respectively.

[0046] The emitter of N4 is connected to SGND.

[0047] Preferably, the filter stabilization module includes capacitor C1 and capacitor C2;

[0048] One end of C1 is connected to the signal input terminal VIN, and the other end of C1 is electrically connected to the gate of MP3; one end of C2 is electrically connected to the upper end of R4, and the other end of C2 is connected to SGND.

[0049] Preferably, the enable comparison control module includes a comparator AMP;

[0050] The positive input terminal of the comparator AMP is used to receive the external enable signal EN; the negative input terminal of the comparator AMP is electrically connected to one end of C2; and the output terminal of the comparator AMP is used to output the control signal EN_DRIVER.

[0051] To illustrate the present invention in more detail, the present invention provides the following specific embodiment: a wide-voltage, low-power enable reference voltage generation circuit, comprising: NFET transistors MN1 and MN2; PFET transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8; transistors N1, N2, N3, and N4; resistors R1, R2, R3, and R4; capacitors C1 and C2; and a comparator AMP;

[0052] The drain of MN1 is connected to VIN; the gate of MN1 is connected to SGND; the source of MN1 is connected to one end of resistor R1; the other end of resistor R1 is connected to the source of MP1 and the source of MP2 respectively; the gates of MP1 and MP2 are connected to SGND; the drain of MP1 is connected to the collector of N1, the base of N1, and the base of N2 respectively; the drain of MP2 is connected to the collector of N2 and the base of N3; the emitter of N2 is connected to one end of resistor R2; the emitter of N1 is connected to one end of resistor R3, the emitter of N3, and the drain of MP6 respectively; the collector of N3 is connected to the source of MN2; the gate of MN2 is connected to SGND; the drain of MN2 is connected to the drain of MP5, the gate of MP5, the PVB0 terminal, the gate of MP3, and capacitor C respectively. One end of 1, the gates of MP4, MP6, MP7, and MP8; the source of MP3, the source of MP4, the source of MP7, and the other end of capacitor C1 are connected to VIN; the drain of MP4 is connected to the source of MP6; the drain of MP7 is connected to the source of MP8; the drain of MP8, one end of resistor R4, one end of capacitor C2, and the negative terminal of comparator AMP are connected to VOUT; the positive terminal of comparator AMP is connected to the external enable terminal EN; the output terminal of comparator AMP is connected to the EN_DRIVER port; the other end of resistor R4, the collector of N4, and the base of N4 are connected; the other end of resistor R2, the other end of resistor R3, the emitter of N4, and the other end of capacitor C2 are connected to SGND.

[0053] In this embodiment, the voltage generation startup circuit consists of MN1, MN2, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, N1, N2, N3, N4, R1, R2, R3, R4, C1, and C1. It employs a mature structure, selecting threshold voltages for MP1 and MP2 that are greater than the base-emitter voltage VCE of N1 and N2. The gates of MP1 and MP2 are connected to SGND, thus MP1 and MP2 operate in saturation. Therefore, the mirror current I... D_MP1 =I D_MP2 =I,I D_MP1 I represents the drain current of MP1. D_MP2 This represents the drain current of MP2. Because the base current of the transistor is I... B <<Collector current I C Then the base current IB If we ignore it, we get The relationship with I:

[0054]

[0055] in, This represents the emitter voltage of the transistor, corresponding to the emitter voltages of N1, N2, and N4 in the circuit. This represents the collector current of the transistor, corresponding to the bias current output by MP1 and MP2. This represents the reverse saturation current of a transistor (proportional to the area of ​​the transistor's emitter region; the larger the area, the higher the saturation current). The larger ( This is the thermal voltage, approximately 26mV at room temperature. This is the reverse saturation current, proportional to the area. The voltage difference VBE between the two tubes can be obtained as:

[0056]

[0057] in, This represents the difference in emitter voltage between N1 and N2. This represents the emitter voltage of N1. This represents the emitter voltage of N2; because the area ratio of N1 to N2 is 4:1, therefore : =4: and These are the reverse saturation currents of N1 and N2, respectively. Because V B1 =V B2 V B1 and V B2 V represents the base voltage of transistors N1 and N2, therefore V E1 V E2 high voltage, V E1 and V E2 This represents the emitter voltage of transistors N1 and N2. A voltage is applied across R3, therefore the current flowing through R3 is:

[0058]

[0059] The current mirror structure is composed of MP3, MP4, MP5, MP6, MP7, and MP8. The current in the branch representing the emitter of N1 is given by a mirror ratio of 1:1:1, thus yielding I. D_MP3 ,5=I D_MP4 ,6=I D_MP7,8 I D_MP3 ,5 represents the drain current of MP3 and MP5; I D_MP4,6 represents the drain current of MP4 and MP6, I D_MP7,8 Let MP7 and MP8 represent the drain currents, then the current in each branch is;

[0060]

[0061] The reference voltage VOUT can be obtained as follows:

[0062]

[0063] Where VOUT is used as the reference voltage input enable circuit This represents the mirrored steady current output by the current mirror. The EN signal represents the emitter-junction voltage of transistor N4. By comparing it with the EN signal, the generated EN_DRIVER signal can shut down all circuits, including the bandgap reference, greatly reducing the chip's power consumption.

[0064] Please see Figure 2 and Figure 3 ,exist Figure 2 The diagram in the middle shows the turn-off current characteristics of the circuit proposed in this invention within a wide voltage input range of 10V to 100V. The horizontal axis represents the circuit's input voltage VIN, with a value range covering 10V to 100V, and the vertical axis represents the current value in the circuit's turn-off state. Figure 2 It can be clearly seen that within the full input voltage range of 10V to 100V, the circuit's shutdown current is always below 1μA, which is far superior to the power consumption level of traditional 100V-level power management chips (whose shutdown current is generally >10μA). Figure 3 This is a schematic diagram illustrating the temperature drift characteristics of the enable / disable reference voltage (VOUT) output by the circuit proposed in this invention. The horizontal axis represents the operating temperature range of the circuit, and the vertical axis represents the temperature drift coefficient of the reference voltage VOUT. Figure 3 It can be observed that the temperature drift coefficient of the reference voltage VOUT is consistently below 30ppm / ℃, which is at the level of high-precision reference voltage in the industry.

[0065] Therefore, in summary, this invention not only precisely meets the core requirement of the automotive electronics and other fields for power management chips with a wide voltage input of 10V~100V, but also reduces design complexity and area cost by simplifying the startup bias module structure and eliminating the complex secondary buck circuit of traditional wide-voltage chips. Furthermore, it overcomes the limitation of traditional solutions where the bandgap reference continues to operate even when it is off—by employing a novel architecture of "local reference voltage generation + enable comparison control," it can completely shut down the subsequent circuits (including the bandgap reference) when the chip is off, thus completely solving the problem of high power consumption during shutdown in traditional solutions. Simultaneously, through the collaborative design of the reference voltage difference generation module and the filter stabilization module, it effectively avoids the industry contradiction of "reducing power consumption at the expense of accuracy," ultimately achieving multiple technical advantages of wide voltage adaptation, low power consumption, high accuracy, and structural simplification, meeting the application requirements of power management chips in high-reliability, low-energy-loss scenarios.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A circuit for generating a wide-voltage, low-power enable reference voltage, characterized in that, include: The module includes a bias start-up module, a reference differential voltage generation module, a current mirror and current distribution module, a reference voltage output module, a filter stabilization module, and an enable comparison control module. The startup bias module is used to provide the initial bias current for the reference differential pressure generation module, and at the same time, it works with the current mirror and current distribution module to establish the initial working state. The reference voltage difference generation module is used to generate a stable emitter voltage difference ΔVBE and generate a reference current based on the emitter voltage difference ΔVBE. The current mirror and current distribution module are used to mirror the reference current generated by the reference voltage difference generation module in a 1:1:1 ratio, output a stable mirror current IO, and transmit its own bias node voltage to the filter stabilization module. The reference voltage output module generates an initial reference voltage VOUT based on the mirror current IO output by the current mirror and the current distribution module, and transmits the initial reference voltage VOUT to the filter stabilization module. The filtering and stabilization module is used to filter and reduce noise on the bias node voltage and initial reference voltage VOUT of the current mirror and current distribution module, feed back the stabilized bias node voltage to the current mirror and current distribution module, and transmit the stabilized initial reference voltage VOUT to the enable comparison control module. The enable comparator control module is used to receive the external enable signal EN and the stabilized initial reference voltage VOUT, and to control the opening or closing of the subsequent circuitry of the chip by comparing and outputting the control signal EN_DRIVER. The startup bias module includes: NFET transistors MN1 and MN2, PFET transistors MP1 and MP2, and resistor R1; The gate of MN1 is connected to SGND, the drain of MN1 is connected to the signal input terminal VIN, and the source of MN1 is electrically connected to one end of R1. The other end of R1 is electrically connected to the source of MP1 and the source of MP2, respectively. The gates of MP1 and MP2 are both connected to SGND. The drains of MP1 and MP2 together form the output terminal of the startup bias module, which is electrically connected to the input terminal of the reference voltage difference generation module. The gate of MN2 is connected to SGND, the drain of MN2 is electrically connected to the control terminal of the current mirror and current distribution module, and the source of MN2 is electrically connected to the intermediate node of the reference voltage difference generation module.

2. The wide-voltage, low-power enable reference voltage generation circuit according to claim 1, characterized in that, The reference differential pressure generation module includes: transistors N1, N2 and N3, and resistors R2 and R3; After the collector and base of N1 are connected together, they are electrically connected to the drain of MP1 and the base of N2, respectively. The emitter of N1 is electrically connected to the emitter of N3, one end of R3, and the first controlled terminal of the current mirror and current distribution module, respectively. The collector of N2 is electrically connected to the drain of MP2 and the base of N3, respectively, and the emitter of N2 is electrically connected to one end of R2. The other end of R2 and the other end of R3 are both connected to SGND; the collector of N3 is electrically connected to the source of MN2; The upper end of R3 constitutes the first output terminal of the reference voltage difference generation module, which is used to output the emitter voltage difference ΔVBE; The emitter of N3 forms the second output terminal of the reference differential voltage generation module, which is used to output the reference current.

3. The wide-voltage, low-power enable reference voltage generation circuit according to claim 2, characterized in that, The area ratio of N1 to N2 is 4:

1.

4. The wide-voltage, low-power enable reference voltage generation circuit according to claim 2, characterized in that, The current mirror and current distribution module includes: PFET transistors MP3, MP4, MP5, MP6, MP7 and MP8; The gates of MP3, MP4, MP6, MP7, MP8, MP5, and the drain of MP5 are connected together and then electrically connected to the drain of MN2 and the first input terminal of the filter stabilization module, respectively. The source terminals of MP3, MP4, and MP7 are all connected to the signal input terminal VIN. The drain of MP3 is electrically connected to the source of MP5; the drain of MP4 is electrically connected to the source of MP6. The drain of MP6 is electrically connected to the emitter of N1; the drain of MP7 is electrically connected to the source of MP8. The drain of the MP8 forms the output terminal of the current mirror and current distribution module, and is electrically connected to the input terminal of the reference voltage output module.

5. The wide-voltage, low-power enable reference voltage generation circuit according to claim 4, characterized in that, The reference voltage output module includes a transistor N4 and a resistor R4; The base and collector of N4 are connected together and then electrically connected to one end of R4. The other end of R4 is electrically connected to the drain of MP8, the second input terminal of the filter stabilization module, and the VOUT port, respectively. The emitter of N4 is connected to SGND.

6. The wide-voltage, low-power enable reference voltage generation circuit according to claim 5, characterized in that, The filter stabilization module includes capacitor C1 and capacitor C2; One end of C1 is connected to the signal input terminal VIN, and the other end of C1 is electrically connected to the gate of MP3; one end of C2 is electrically connected to the upper end of R4, and the other end of C2 is connected to SGND.

7. The wide-voltage, low-power enable reference voltage generation circuit according to claim 6, characterized in that, The enable comparison control module includes a comparator AMP; The positive input terminal of the comparator AMP is used to receive the external enable signal EN; the negative input terminal of the comparator AMP is electrically connected to one end of C2; and the output terminal of the comparator AMP is used to output the control signal EN_DRIVER.

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