Delay compensation method, device, chip, network interface card, equipment, medium and program product

Abstract

The application relates to a delay compensation method, device, chip, network interface card, equipment, medium and program product. The method comprises the following steps: when each link data packet processing of a target link is completed, the sending time of a traffic control update data packet corresponding to the link data packet is delayed, wherein the target link is a link with a first real-time delay time which is not the longest among at least two links, and the traffic control update data packet is used for returning a credit for sending a control link data packet. By using the method, the delay time of each link can be balanced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a delay compensation method, apparatus, chip, network interface card, device, medium, and program product. Background Technology

[0002] Data Processing Units (DPUs) have become critical components in modern data centers, offloading networking, storage, and security tasks. To maximize resource utilization, a single DPU typically needs to support flexible and diverse connectivity topologies. One such technique, PCIe link bifurcation, allows a high-speed PCIe x16 interface to be split into multiple x8 or x4 interfaces to serve different purposes. This gives rise to two typical connectivity scenarios:

[0003] In a single-host, multi-slot connection scenario, a DPU's PCIe x16 interface is split into two x8 interfaces, each connected to a different physical slot on the same host. Due to differences in physical paths such as motherboard cabling and whether or not a PCIe expansion card (riser card) is used, the inherent latency of these two links may differ significantly.

[0004] Dual-host / quad-host independent connection scenario: One PCIe x16 interface of the DPU is split into two x8 interfaces or four x4 interfaces, which are connected to two or four independent hosts respectively. In this scenario, although the hosts do not communicate directly with each other, the DPU needs to provide services to two or four different physical servers.

[0005] However, when the DPU is connected to the same host via both direct connection and expansion card, the PCIe expansion card introduces additional transmission and processing latency, resulting in inconsistent latency characteristics between different slots, which causes serious performance and fairness issues for the business. Summary of the Invention

[0006] Therefore, it is necessary to provide a delay compensation method, device, chip, network interface card, equipment, medium, and program product that can balance the delay time of each link to address the above-mentioned technical problems.

[0007] In a first aspect, this application provides a delay compensation method applied at a receiving end, the method comprising:

[0008] When each link data packet of the target link is processed, the transmission time of the flow control update data packet corresponding to the link data packet is delayed, wherein the target link is the link with the longest first real-time delay among at least two links, and wherein the flow control update data packet is used to return credit to the sender to control the transmission of the link data packet.

[0009] In one embodiment, the method further includes:

[0010] Measure the first real-time delay time of each of the aforementioned links;

[0011] Based on the first real-time delay time of each of the links, and taking the maximum first real-time delay time as a benchmark, the compensation delay time of each of the target links is calculated.

[0012] The step of delaying the transmission time of the flow control update data packet corresponding to the link data packet includes:

[0013] The transmission time of the flow control update data packet corresponding to the link data packet is delayed by the compensation delay time.

[0014] In one embodiment, measuring the first real-time latency of each of the links includes:

[0015] Generate a real-time probe packet and embed a sending timestamp into the real-time probe packet;

[0016] Simultaneously, the generated real-time probe packets are sent to each of the aforementioned links;

[0017] For each of the links, the receiving timestamp of the acknowledgment packet of each real-time probe packet is obtained, and the first real-time delay time of the link is obtained based on the sending timestamp and the receiving timestamp.

[0018] In one embodiment, after calculating the compensation delay time for each of the target links, the method further includes:

[0019] If the compensation delay time is greater than or equal to the delay threshold, continue to execute the step of delaying the compensation delay time by sending the flow control update data packet corresponding to the link data packet at the same time.

[0020] If the compensation delay time is less than the delay threshold, the flow control update data packet is sent according to the default sending time of the flow control update data packet corresponding to the link data packet.

[0021] In one embodiment, delaying the transmission time of the flow control update data packet corresponding to the link data packet includes:

[0022] The second real-time delay time of each link is measured. The second real-time delay time of each link is obtained based on the sending timestamp of the probe packet resent to the link and the receiving timestamp of the acknowledgment packet corresponding to the probe packet after delaying the sending time of the flow control update data packet.

[0023] Based on the second real-time delay time of each link, it is detected whether the delay time of each link is balanced. If the difference duration corresponding to each link whose second real-time delay time is not the longest is less than the delay threshold, it is determined that the delay time of each link is balanced. The difference duration is the difference between the maximum second real-time delay time and the second real-time delay time that is not the longest.

[0024] In cases where the delay times of the various links are uneven, the compensation delay time of each target link is re-determined.

[0025] In one embodiment, after redetermining the compensation delay time for each of the target links, the process includes:

[0026] The third real-time delay time of each of the links is measured. The third real-time delay time of each link is obtained based on the sending timestamp of the probe packet sent to the link again and the receiving timestamp of the acknowledgment packet corresponding to the probe packet, when it is determined that the delay times of the links are unbalanced.

[0027] Based on the third real-time delay time of each link, detect whether the delay time of each link is balanced;

[0028] In the case of uneven delay times across the links, update the number of iterations for redetermining the compensation delay time;

[0029] Before redetermining the compensation delay time for each of the target links, the method further includes:

[0030] If the number of iterations is less than the threshold, the step of redetermining the compensation delay time for each target link continues.

[0031] If the number of iterations is greater than or equal to the threshold number, an alarm message indicating compensation failure will be output.

[0032] Secondly, this application also provides a delay compensation device applied at a receiving end, the device comprising:

[0033] The sending module is used to delay the sending time of the flow control update data packet corresponding to the link data packet when the processing of each link data packet of the target link is completed, wherein the target link is the link with the longest first real-time delay time among at least two links, and wherein the flow control update data packet is used to return credit to the sending end for controlling the sending of the link data packet.

[0034] Thirdly, this application also provides a chip including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0035] Fourthly, this application also provides a network interface card, including the chip and multiple interfaces as described in any of the above embodiments.

[0036] The chip processes data or communicates with the outside world through the interface.

[0037] Fifthly, this application also provides a computer device including a network interface card in any of the above embodiments, the network interface card being used for processing data or external communication.

[0038] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0039] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0040] The aforementioned delay compensation methods, devices, chips, network interface cards, equipment, media, and program products delay the transmission time of the flow control update data packet corresponding to each link data packet when the processing of each link data packet of the target link is completed. The target link is the link with the first real-time delay time that is not the longest among at least two links. By delaying the transmission time of the link with the non-longest delay time, the delay time of each link is ensured to be the same, that is, the delay characteristics between different slots are kept consistent, thereby ensuring that the service brings significant performance and fairness. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1A This is a schematic diagram of a first connection scenario in which the DPU connects to the host via a PCIe slot in one embodiment;

[0043] Figure 1B This is a schematic diagram of a second connection scenario in one embodiment, where the DPU connects to the host via a PCIe slot;

[0044] Figure 1C This is a schematic diagram of a third connection scenario in one embodiment, where the DPU connects to the host via a PCIe slot;

[0045] Figure 2 This is a flowchart illustrating a delay compensation method in one embodiment;

[0046] Figure 3 This is an architecture diagram of a delay compensation system in one embodiment;

[0047] Figure 4 Here is a flowchart of a delay compensation method in another embodiment;

[0048] Figure 5A This is a timing diagram of delay compensation in one embodiment;

[0049] Figure 5B This is a timing diagram for delay compensation in another embodiment;

[0050] Figure 6 This is a structural block diagram of a delay compensation device in one embodiment;

[0051] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0054] For ease of understanding, combined with Figures 1A to 1C The figures show various connection scenarios where the DPU connects to the host via a PCIe slot. Figure 1A Within the host system, a unified CPU, memory, and PCIe root interface are integrated. One of the DPU's PCIe x16 physical ports is split into two logical x8 interfaces, connected to two separate PCIe slots on the host via bifurcation technology. The latency difference primarily stems from the different physical cabling paths; for example, "path A-2," due to its route via a PCIe expansion card (RiserCard), inherently has a higher latency than the directly connected "path A-1."

[0055] Scenario 1 (Single-host non-NUMA) data flow path:

[0056] 1. MemoryRead path: CPU → Memory Controller → System Memory → PCIeRC → PCIe Slot → DPU:

[0057] a) Path A-1 (direct connection): CPU→RC→Slot1→DPU.

[0058] b) Path A-2 (Expansion Card): CPU→RC→Slot2→RiserCard→DPU.

[0059] 2. MemoryWrite path: DPU → PCIe slot → PCIe root union → memory controller → system memory:

[0060] a) Path A-1 (direct connection): DPU→Slot1→RC→Memory.

[0061] b) Path A-2 (Expansion Card): DPU→RiserCard→Slot2→RC→Memory.

[0062] Figure 1B The middle section uses a NUMA (Non-Uniform Memory Access) architecture, where the host contains two NUMA nodes, each with its own independent CPU, memory, and PCIe root union. This architecture introduces more complex sources of latency:

[0063] 1) Differences in PCIe physical paths, such as path B-2 passing through an expansion card.

[0064] 2) Cross-NUMA node access overhead: When a CPU needs to access the memory of another node or its directly connected PCIe device, additional latency is incurred. Therefore, the latency difference between paths B-1 and B-2 is the result of the combination of these two factors.

[0065] Scenario 2 (Single-host NUMA) Data Flow Path:

[0066] 1. MemoryRead path:

[0067] a) Local NUMA node: CPU0 → Local memory 0 → RC0 → Slot1 → DPU.

[0068] b) Across NUMA nodes: CPU1 → Cross-node memory access → Memory 0 → RC0 → Slot1 → DPU.

[0069] c) Expansion card path: CPU1 → Local memory 1 → RC1 → Slot2 → Riser → DPU.

[0070] 2. MemoryWrite path:

[0071] a) Local write-back: DPU→Slot1→RC0→Local memory 0.

[0072] b) Cross-node write-back: DPU→Slot1→RC0→Cross-node access→Memory1.

[0073] Figure 1C This demonstrates a scenario where the DPU serves two independent hosts. The DPU's PCIe x16 port is split into two independent x8 interfaces, connected to host C and host D respectively. Since the hardware configurations, motherboard wiring, operating systems, etc. of the two hosts may differ, there will almost always be a latency difference in the PCIe links (path C-1 and path C-2) from the DPU to the two hosts.

[0074] Scenario 3 (Multi-host Connection) Data Flow Path:

[0075] Host AMemoryRead: CPU_A→Memory_A→PCIe_A→DPU_Port1.

[0076] Host BMemoryRead: CPU_B→Memory_B→PCIe_B→DPU_Port2.

[0077] Host CMemoryRead: CPU_C→Memory_C→PCIe_C→DPU_Port3.

[0078] Host DMemoryRead: CPU_D→Memory_D→PCIe_D→DPU_Port4.

[0079] The write-back path (memory write path) of each host is the reverse of the read path, and the latency characteristics are similar. The fundamental reasons (main reasons) for the latency differences in the host-DPU connection system path include:

[0080] 1. Physical distance difference: The physical distance from different PCIe slots to the CPU is different.

[0081] 2. PCIe expansion card: Riser Card adds additional signal propagation delay.

[0082] 3. NUMA cross-node access: Memory access across NUMA nodes requires additional interconnect latency.

[0083] 4. Differences in host hardware: Differences in CPU performance, memory speed, and motherboard design between different hosts.

[0084] 5. Impact of link width: Differences in bandwidth and latency characteristics between x8 and x4 links.

[0085] The terms "path" and "link" in this application have the same meaning. To address the aforementioned technical problems, in an exemplary embodiment, such as... Figure 2 As shown, a delay compensation method is provided, which is applied to... Figures 1A-1C Taking the DPU (i.e., the receiver) as an example, the explanation includes the following steps 202: Wherein:

[0086] S202: When each link data packet of the target link is processed, the sending time of the flow control update data packet corresponding to the link data packet is delayed, wherein the target link is the link with the longest first real-time delay among at least two links, and the flow control update data packet is used to return the credit of controlling the sending of the link data packet to the sender.

[0087] For ease of understanding, the communication method between the host (sender) and the DPU (receiver) is explained. This communication method is a credit-based flow control mechanism to prevent buffer overflow at the receiver. Specifically, during the link initialization phase, the receiver informs the sender of the size of its internal receive buffer, which is measured in "credit units." One credit unit typically corresponds to one TLP data packet. The sender maintains a credit counter. Each time a data packet is sent, a corresponding amount of credit is consumed. If the credit is insufficient, the sender must pause sending until it receives credit returned by the receiver. After processing the data packet and releasing its occupied buffer, the receiver returns credit to the sender by sending a specific type of data link layer packet, DLLP, i.e., UpdateFC (Flow Control Update). This credit is used by the sender to control the transmission of link data packets.

[0088] In this application, in order to balance the latency of each link, the timing of sending update data packets is controlled by controlling the flow control to ensure the balance of latency of each link.

[0089] In a standard PCIe link, flow control update packets are sent as soon as the buffer is released to maximize link throughput. In the compensation mechanism of this application, the DPU, as the receiver, can intentionally delay the time it returns credit to the host (sender), that is, delay the sending time of the flow control update packets.

[0090] In order to balance the latency of each link, the link with the longest real-time latency among at least two links is selected as the target link, which means that the sending time of its flow control update data packet needs to be delayed.

[0091] Optionally, in this application, the transmission time of the flow control update data packet of the link with the first real-time delay time that is not the longest can be delayed. The compensation delay time can be fixed or determined based on the real-time link, and no specific limitation is made here.

[0092] Optionally, a timer can be introduced to delay the transmission of flow control update data packets. Specifically, after the corresponding link data packet processing is complete, the corresponding buffer is released, and the timer is started. The timer controls the transmission timing of the flow control update data packets. When the timer reaches its set time, the flow control update data packets are transmitted. The set time is determined based on the compensation delay time of the flow control update data packets.

[0093] When the DPU needs to access a low-latency link (e.g.) Figure 1A When an artificial delay is applied to "path A-1" in the DPU, after processing packets from that link, it does not immediately return credits. Instead, it starts a timer to temporarily suspend the transmission of flow control update packets. During this suspension period, the host may be unable to send new packets due to credit exhaustion; these packets will simply wait in the host's send buffer. When the preset delay time is reached, the DPU then sends flow control update packets to return credits, and the host immediately resumes data transmission.

[0094] By actively pausing at the receiving end and passively waiting at the sending end, the data packets remain in the sending end's buffer for an additional period of time, effectively increasing the end-to-end latency of this low-latency link.

[0095] The aforementioned delay compensation method delays the transmission time of the flow control update data packet corresponding to each link data packet when the processing of each link data packet of the target link is completed. The target link is the link whose first real-time delay time is not the longest among at least two links. By delaying the transmission time of the link whose delay time is not the longest, it ensures that the delay time of each link is the same, that is, the delay characteristics between different slots are consistent, thereby ensuring that the service brings significant performance and fairness.

[0096] In some optional embodiments, the method further includes: measuring the first real-time delay time of each link; calculating the compensation delay time of each target link based on the first real-time delay time of each link, with the maximum first real-time delay time as a benchmark; delaying the transmission time of the flow control update data packet corresponding to the link data packet, including: delaying the transmission time of the flow control update data packet corresponding to the link data packet by the compensation delay time.

[0097] The compensation delay time can be determined based on the first real-time delay time measured in real time. In order to ensure the accuracy of the test, the real-time delay time of each link can be measured multiple times. For example, each link sends multiple probe packets, and then calculates the corresponding real-time delay time for different probe packets. Subsequently, the first real-time delay time of the link can be determined based on the real-time delay time measured multiple times.

[0098] Each link can be assigned a path identifier, thus maintaining an independent RTT calculation channel for each PCIe physical path. Then, the complete round-trip time from sending to receiving acknowledgment for each probe packet, i.e., the real-time delay, is accurately calculated. Statistical indicators are calculated on the obtained real-time delay, such as minimum, maximum, average, and variance. Then, based on the statistical indicators, abnormal delay values ​​are automatically identified and filtered. For example, abnormal points exceeding 3σ are deleted. Finally, the first real-time delay is calculated based on the remaining real-time delay.

[0099] Each real-time delay can be cached, for example, in a circular buffer, such as a high-speed SRAM-implemented circular buffer, which can store the most recent 10,000 real-time delays. In other embodiments, the number of real-time delays in the buffer can be other values. In some optional embodiments, the data can be compressed, for example, using incremental coding and timing compression algorithms to improve storage efficiency. Subsequently, the collected real-time delays can be reported to the control plane in real time, for example, at an update frequency of 100Hz, so that the control plane can calculate the first real-time delay corresponding to each link based on the reported real-time delays.

[0100] Then, the maximum first real-time delay is determined from the first real-time delay times of each link. The difference between the first real-time delay times of other links and the maximum first real-time delay time is then calculated; this difference is the compensation delay time for the corresponding link. For example... Figure 1A The first real-time delay time corresponding to path A-1 is less than the first real-time delay time corresponding to path A-2. Therefore, the first real-time delay time corresponding to path A-2 is the maximum real-time delay time. Then, the difference between the first real-time delay time of path A-1 and the first real-time delay time of path A-2 is calculated as the compensation delay time of path A-1.

[0101] After calculating the compensation delay time for the target path, when the target link needs to send a flow control update data packet, the compensation delay time is delayed before sending it, so that the delay time of each link is balanced in real time.

[0102] In the above embodiments, the compensation delay time of each link is calculated in real time, ensuring accuracy.

[0103] In some optional embodiments, measuring the first real-time delay time of each link includes: generating a real-time probe packet and embedding a sending timestamp in the real-time probe packet; simultaneously sending the generated real-time probe packet to each link; for each link, obtaining the receiving timestamp of the acknowledgment packet of each real-time probe packet, and obtaining the first real-time delay time of the link based on the sending timestamp and the receiving timestamp.

[0104] The probe packets are generated when the first real-time delay of each link needs to be detected. Each link corresponds to multiple probe packets, which are sent sequentially. Optionally, the probe packets can be standard PCIe TLP (Transaction Layer Packet) probe packets, and their size is configurable, for example, 64B-256B. To accurately detect the first real-time delay, a transmission timestamp can be embedded in each probe packet. To improve detection accuracy, a high-precision hardware timestamp (nanosecond-level accuracy) can be embedded in the probe packets.

[0105] To ensure data synchronization, this application simultaneously sends generated real-time probe packets to each link. Furthermore, to distinguish multiple probe packets within a single link, a unique sequence number can be assigned to each probe packet to guarantee the accuracy of the first real-time delay calculation. The test for measuring the first real-time delay can be pre-set, for example, per TestNum delay measurements, where per TestNum is the pre-set number of real-time delay measurements.

[0106] To facilitate understanding of the calculation of the first real-time latency, this embodiment provides a complete implementation. Firstly, an independent RTT calculation channel is maintained for each PCIe physical path. The calculation of the first real-time latency for each link is independent of each other. For each link, several probe packets are generated. The number of test packets can be equal to the number of real-time latency measurements, i.e., per... TestNum, each probe packet has a unique sequence number. Probe packets are sent sequentially, each carrying a sending timestamp. Then, it waits for the corresponding acknowledgment packet, and determines the corresponding probe packet based on the sequence number in the acknowledgment packet. Based on the receiving timestamp in the acknowledgment packet and the sending timestamp in the determined probe packet, the real-time delay time corresponding to the probe packet is calculated. The real-time delay time corresponding to the probe packet can be stored in a circular buffer, and each real-time delay time is reported periodically. After each real-time delay time corresponding to the probe packet is reported, the corresponding buffer can store the real-time delay time corresponding to the new probe packet. By statistically analyzing the reported real-time delay times corresponding to each probe packet, anomaly filtering is performed on the real-time delay times corresponding to each probe packet, and the first real-time delay time is obtained based on the filtered real-time delay times. For example, the average real-time delay time is calculated as the first real-time delay time.

[0107] The accuracy of the timestamps for sending the probe packets and receiving the acknowledgment packets can be pre-configured, and the accuracy of the corresponding timestamps is determined based on the configured delay measurement accuracy level.

[0108] In some optional embodiments, after calculating the compensation delay time for each target link, the method further includes: if the compensation delay time is greater than or equal to a delay threshold, continuing to execute the step of delaying the compensation delay time by setting the sending time of the flow control update data packet corresponding to the link data packet; if the compensation delay time is less than the delay threshold, sending the flow control update data packet according to the default sending time of the flow control update data packet corresponding to the link data packet.

[0109] The latency threshold, latencyThreshold, is also preset. This threshold represents the tolerable latency difference between various links. If the compensation latency time is greater than or equal to the latency threshold (i.e., the latency between two links is greater than or equal to the latency threshold), latency compensation is required. Therefore, the sending time of the flow control update data packet corresponding to the target link is delayed by the compensation latency time. If the compensation latency time is less than the latency threshold (i.e., the latency between links is tolerable), the flow control update data packet can be sent according to the default sending time of the current flow control update data packet for that link.

[0110] In the above embodiments, balancing is not required for every calculation, which can reduce the amount of data processing.

[0111] In some optional embodiments, after delaying the transmission time of the flow control update data packet corresponding to the link data packet, the method includes: measuring the second real-time delay time of each link, wherein the second real-time delay time of each link is obtained after delaying the transmission time of the flow control update data packet based on the transmission timestamp of the probe packet retransmitted to the link and the reception timestamp of the acknowledgment packet corresponding to the probe packet; detecting whether the delay time of each link is balanced based on the second real-time delay time of each link, wherein if the difference duration corresponding to each link whose second real-time delay time is not the longest is less than the delay threshold, it is determined that the delay time of each link is balanced, and the difference duration is the difference between the maximum second real-time delay time and the non-longest second real-time delay time; and re-determining the compensation delay time of each target link if the delay time of each link is unbalanced.

[0112] In this application, after delaying the transmission time of each target link, it is also necessary to verify the compensation of each link. In this embodiment, probe packets can be sent again to measure the second real-time delay time of each link. The number of measurements of the second real-time delay time can also be per TestNum. Based on the second real-time delay time of each link, it is detected whether the delay time of each link is balanced. For example, based on the maximum second real-time delay time, the difference duration corresponding to the link with the shorter second real-time delay time (i.e., not the longest) is calculated. If at least one of the difference durations corresponding to the links with shorter second real-time delay times is greater than or equal to the delay threshold (i.e., the delay threshold latencyThreshold mentioned above), it indicates that there is an imbalance. The method of obtaining the second real-time delay time is the same as the method of obtaining the first real-time delay time, and will not be described in detail here.

[0113] If the delay time of each target link is still uneven after delaying the transmission time of each target link, the compensation delay time of each target link needs to be redetermined. The redetermined compensation delay time of each target link is the same as the first determination of the compensation delay time of each target link. Optionally, the difference time corresponding to the link with the second real-time delay time that is not the longest calculated by the probe packet during the verification process can be directly used as the new compensation delay time to reduce the amount of data processing.

[0114] Furthermore, it should be noted that after recalculating the new compensation delay time, this new compensation delay time can be verified, for example, by using historical data. This historical data includes the historical delay time and historical compensation delay time of the link. Statistical values ​​of each historical delay time and mathematical statistical values ​​of the historical compensation delay time are calculated. These mathematical statistical values ​​can be averages, etc. Then, the calculated new compensation delay time is compared with the calculated average of historical compensation delay times. The second real-time delay time measured in this instance is also compared with the average of historical delay times. If the differences between the two comparisons are within a reasonable range, the new compensation delay time is deemed to have passed verification. Therefore, the sending time of flow control update data packets can be adjusted based on the new compensation delay time.

[0115] In some optional embodiments, after redetermining the compensation delay time of each target link, the process includes: measuring the third real-time delay time of each link, wherein the third real-time delay time of each link is obtained based on the sending timestamp of the probe packet sent to the link again and the receiving timestamp of the acknowledgment packet corresponding to the probe packet when it is determined that the delay times of each link are unbalanced; detecting whether the delay times of each link are balanced based on the third real-time delay time of each link; updating the iteration number when the delay times of each link are unbalanced; and before redetermining the compensation delay time of each target link, the process further includes: continuing to perform the step of redetermining the compensation delay time of each target link if the number of iterations for redetermining the compensation delay time is less than a threshold number; and outputting an alarm message of compensation failure if the number of iterations is greater than or equal to the threshold number.

[0116] Each time the compensation delay time is updated, verification is required, which involves measuring the current real-time delay time of the link, referred to as the third real-time delay time in this embodiment. Based on the third real-time delay time of each link, it is determined whether the delay times of each link are balanced. The determination of the third real-time delay time can be found in the determination of the first and second real-time delay times mentioned above. The specific method for determining whether they are balanced can be found in the above text and will not be repeated here.

[0117] In addition, this application sets the number of iterations, which is the number of times the compensation delay time is re-determined. The number of iterations threshold, iterationAttempts, is pre-configured, which is the maximum number of adjustment iterations, and its value is generally between 1 and 10, without specific limitation here.

[0118] If the number of iterations is less than the threshold, the compensation delay time can continue to be updated. If the number of iterations is greater than or equal to the threshold, an alarm message is output. After the alarm message is output, data can be transmitted in a normal manner, and the alarm message is stored in the log for subsequent debugging.

[0119] For ease of understanding, combined with Figure 3 As shown, Figure 3 The diagram below shows the architecture of a delay compensation system in one embodiment. In this embodiment, the DPU includes a DPU BMC management plane for configuring delay compensation parameters, a control plane for calculating the compensation delay time of each target link, and a data plane for measuring the real-time delay time of each link and performing delay compensation on each target link.

[0120] The management plane includes a configuration entry point. The configuration management module can configure latency compensation parameters through the DPU BMC (DPU Management Plane) medium. The configuration management module is responsible for receiving the latency compensation parameters configured in the configuration entry point and storing the user's configuration. The core configuration item is the "latency compensation function switch" (enabled / disabled).

[0121] The Configuration Entry Point can provide various user interaction interfaces, such as: a command-line tool (CLI) to provide a complete set of commands and support configuration query, modification and other operations; a RESTful API for a programmatic interface based on HTTP / HTTPS that supports configuration operations in JSON format; and a web management page for users to complete parameter configuration through a GUI interface.

[0122] The delay compensation parameters include: a global switch for the delay equalization function (enable_balancer: enabled / disabled), a delay threshold setting (latency_threshold: 10-2000 ns, default 100 ns), a maximum number of adjustment iterations (max_adjust_iterations: 1-10 times, default 3 times), a verification measurement sampling count (verify_sample_count: 5-50 times, default 10 times), a delay measurement accuracy level (precision_level: 10ns / 50ns / 100ns, default 100ns), and a successive count of successful compensation determinations (success_consecutive_count: 1-10 times, default 3 times). The value ranges of each parameter given in this embodiment are for illustrative purposes only, and those skilled in the art can set them as needed.

[0123] The control plane includes a scene recognizer, used to identify the connection scenarios between the DPU and the host. Specific connection scenarios can be found in [reference needed]. Figures 1A to 1CThe system consists of a delay control engine and a delay calculation engine. The delay control engine interacts with the backend delay measurement module through the MHU channel to configure delay measurement parameters. The delay calculation engine calculates the compensation delay time required for each link based on the real-time delay time returned by the backend, decides whether to compensate the target link, and continuously iterates and optimizes based on the compensation effect. Finally, it sends compensation instructions to the backend delay compensation module through the MHU channel.

[0124] In the data plane, which corresponds to the hardware / firmware level, the data plane includes the PCIe interface controller group, the latency measurement module, and the latency compensation module, among which:

[0125] The PCIe interface controller group manages data transmission on the PCIe link. A key feature is that the credit management unit can be software-programmable to precisely delay the timing of flow control credit (UpdateFC packet) return. The PCIe x16 DPU can be configured as two PCIe x8 modules or four PCIe x4 modules.

[0126] The latency measurement module performs high-precision, real-time latency measurements on all PCIe links, providing an accurate data foundation for latency compensation. This module includes a probe packet generator, an RTT calculation unit, and a latency data cache unit. The probe packet generator generates standard PCIe TLP probe packets; specific limitations are detailed above. The RTT calculation unit calculates the real-time latency for each link, and the latency data cache stores the real-time latency for each link.

[0127] The delay compensation module is responsible for performing precise delay compensation, achieving delay balancing by controlling the timing of PCIe flow control credit return. This module includes a credit management unit, a hardware timer, and a compensation execution engine. The credit management unit supports a multi-channel architecture, with multiple independent credit management channels, each corresponding to a PCIe link. Each channel can perform the following: compensation instruction reception (receiving compensation duration instructions (Δt value) from the control plane), credit status tracking (real-time tracking of the flow control credit status and usage of each link), UpdateFC control (precisely controlling the timing of UpdateFC (flow control update) packet transmission), and compensation execution (delaying the normal credit return time (i.e., the transmission time of the flow control update data packet) by an additional Δt time before sending the UpdateFC packet). The hardware timer is used for high-precision timing, specifically a hardware timer based on a high-frequency clock source with an accuracy of 10 nanoseconds. It supports multiplexing, meaning it can simultaneously provide independent timing services for multiple links. Interrupt-driven timing, based on hardware interrupts, avoids software polling overhead and supports a timing range from 1 nanosecond to 100 microseconds, with timing errors controlled within ±50 nanoseconds. The Compensation Execution Engine is used for instruction parsing, i.e., parsing compensation instructions from the control plane, extracting the target link and compensation duration. State machine control is used, for example, a finite state machine can be used to manage the entire compensation execution process. Concurrent execution is supported, for example, supporting concurrent execution of compensation operations for multiple links without interference. Exception handling handles various abnormal situations during compensation execution. Execution feedback provides feedback on the compensation execution status and results to the control plane.

[0128] In this application, the delay compensation method may include the following steps:

[0129] Configuration check steps: Before processing any data stream, the system first checks whether the "Delay Compensation Function" has been enabled by the user through the "Configuration Management Module". If it is not enabled, all compensation logic is bypassed and data is processed in standard mode; if it is enabled, proceed to the next step.

[0130] Delay measurement steps: Periodically measure the round-trip time (RTT) of all active PCIe links using the "Delay Measurement Module" to establish a real-time delay baseline for each link.

[0131] Delay compensation calculation steps: The "delay calculation engine" uses the maximum delay among all active links as a benchmark to calculate the compensation time required for other links with lower delays: Δt = Max_Latency - Current_Path_Latency.

[0132] Flow control credit compensation implementation steps: For low-latency links requiring compensation, the scheduler instructs its corresponding "PCIe interface controller" to delay the return of flow control credits. After receiving data and releasing the buffer, the controller does not immediately return the credits, but waits for a period determined by the compensation duration before returning the credits to the sender (host). This causes the data to wait additionally in the sender's buffer, thereby increasing the total latency of the link and achieving a balancing effect.

[0133] For ease of understanding, combined with Figure 4 As shown, Figure 4 The flowchart below shows a delay compensation method in another embodiment. In this embodiment, the entire process is divided into four core stages: configuration check, delay measurement and compensation, effect verification, and feedback optimization, forming a complete closed-loop control system. This closed-loop control process demonstrates the system's adaptability and reliability. Key steps are as follows:

[0134] The configuration check process includes: after the system starts, checking the user configuration, including the compensation switch / compensation parameters (as shown below), to determine whether the delay compensation function is enabled / whether the parameter configuration is correct. If enabled, the complete compensation process will begin.

[0135] The latency measurement and compensation process includes: Initiating latency measurement: Real-time latency measurement is performed on all PCIe links, compensation values ​​are calculated, and the compensation latency time is calculated using the formula Δt = Max_Latency - Current_Path_Latency. Determining whether compensation is needed: Checking if the latency difference exceeds the latency_threshold threshold. PCIe flow control credits are returned for low-latency links.

[0136] The effect verification loop includes: verify_sample_count consecutive delay measurements to provide statistical reliability. If the difference in delay after verification and comparison is less than the latency_threshold threshold, then normal data processing begins; otherwise, the feedback control mechanism is activated.

[0137] The feedback optimization process includes: analyzing the reasons for compensation failure (measurement error / load change / hardware anomaly) and recalibrating, calculating new compensation parameters, and then re-entering the compensation process (limiting the adjustment to a maximum of max_adjust_iterations to prevent infinite loops), measuring the adjustment effect, and determining whether it meets the target.

[0138] The result processing includes: If compensation is successful: update the compensation baseline and enter maintenance mode. If compensation fails: trigger an alarm, log the event, and perform a downgrade.

[0139] Specifically, the delay compensation method includes a closed loop of compensation verification and feedback control. At the beginning of the process, the user configuration parameters are checked, that is, the delay compensation parameters configured above are checked. If the delay compensation mode is enabled, the delay compensation method in this application is executed; otherwise, the standard mode is followed and no compensation is required.

[0140] After enabling compensation mode, the first real-time delay time of all active links is measured. To improve accuracy, each link can be measured multiple times. Then, using the maximum first real-time delay time as a benchmark, the difference between the first real-time delay time of other links and the maximum first real-time delay time is calculated as the compensation delay time. Next, it is determined whether this compensation delay time is greater than a delay threshold. If not, the delay compensation mode is exited; otherwise, compensation is applied to the target link by delaying the transmission time of the flow control update data packet. The compensation effect is then verified by continuously measuring the second real-time delay time of each link multiple times and determining whether the links are balanced based on this second real-time delay time. If balanced, the delay compensation mode is exited; otherwise, feedback control is initiated. Optionally, the cause of failure can be analyzed and recorded for subsequent recalibration. The number of iterations is also checked. If the number of iterations is less than a threshold, the compensation delay time can continue to be updated. If the number of iterations is greater than or equal to the threshold, an alarm message is output. After outputting the alarm message, data can be transmitted using normal methods, and the alarm message is stored in the log for subsequent debugging.

[0141] For ease of understanding, combined with Figure 5A and Figure 5B As shown, Figure 5A This is a timing diagram of delay compensation in one embodiment. Figure 5B Here is a timing diagram for delay compensation in another embodiment, wherein Figure 5A and 5B This document demonstrates the complete process of using the PCIe protocol's built-in flow control credit mechanism to achieve latency compensation, including compensation verification and feedback mechanisms. In the normal path, the DPU returns a credit (UpdateFC) to the host immediately after consuming a data packet. In the path requiring compensation (i.e., the low-latency path), the DPU intentionally delays returning the flow control credit, causing the host to suspend transmission. Specifically, this includes:

[0142] Phase 1: Implementation of Basic Compensation (S1-S8):

[0143] S1: The Host sends a data packet (TLP) to the DPU, and the sender's buffer has data to be sent.

[0144] S2: The DPU receives and consumes data packets and releases the receive buffer.

[0145] S3: The DPU processes the data packet and prepares to return the flow control credit.

[0146] S4: For the normal path (high-latency path), the DPU immediately returns the UpdateFC packet.

[0147] S5: After the Host obtains the credit, it continues to send the next data packet.

[0148] S6: For the path that needs compensation (low-latency path), the DPU does not return the flow control credit temporarily.

[0149] S7: The Host suspends sending due to exhausted credit, and the data packet waits in the sending buffer for the compensation duration Δt.

[0150] S8: After the compensation time arrives, the DPU returns the UpdateFC packet and the Host resumes sending.

[0151] Phase II: Compensation effect verification (S9 - S12):

[0152] S9: The DPU triggers the compensation effect verification module to start the verification process.

[0153] S10: The verification module performs continuous latency measurements for verify_sample_count times to collect statistical samples.

[0154] S11: Calculate the statistical value of the latency difference for all links and compare it with the latency_threshold threshold.

[0155] S12: Determine the verification result: success (latency difference < latency_threshold) or failure (latency difference ≥ latency_threshold).

[0156] Phase III: Verification success path (S13):

[0157] S13: If the verification is successful, the DPU enters the maintenance mode and continues normal data processing.

[0158] Phase IV: Feedback control and parameter adjustment (S14 - S17):

[0159] S14: If the verification fails, start the feedback control module to analyze the cause of failure.

[0160] S15: According to the cause of failure: such as measurement error, load change or hardware anomaly, then recalibrate.

[0161] S16: Calculate the new compensation parameter Δt_new, considering the error and historical data.

[0162] S17: Send the adjusted compensation parameters to the DPU compensation execution engine and proceed to S18.

[0163] Phase 5: Adjusted and Recompensated (S18-S22):

[0164] S18: Based on the adjustments made in stage S17, the second stage of compensation begins.

[0165] S19: The Host sends a data packet, and the DPU performs compensation using the new parameter Δt_new.

[0166] S20: DPU delayed return of flow control credits (using adjusted duration).

[0167] S21: After the compensation time expires, an UpdateFC packet is returned, and the Host resumes sending.

[0168] S22: The DPU triggers the verification module again to verify the effect of the adjusted compensation.

[0169] Phase Six: Iterative Optimization and Result Processing (S23-S25):

[0170] S23: Verify the module to remeasure and determine the effect of the adjustment.

[0171] S24: If the adjustment is successful, the compensation process is complete; if further adjustment is still needed, check the number of iterations.

[0172] S25: The system will perform a maximum of max_adjust_iterations iterations of adjustment. If the limit is exceeded, an alarm and degradation processing will be triggered.

[0173] The above embodiments can simultaneously cover two mainstream complex scenarios: single-host, multi-slot, and dual-host, independent connection, providing a scalable technical foundation for more connection modes in the future. Relying solely on software control of the native PCIe flow control mechanism, without the need for additional fine-grained latency compensation hardware, it significantly reduces design complexity and hardware costs, making this technology highly promising for industrialization. Administrators can enable or disable the latency compensation function at any time through configuration switches according to actual business needs (such as performance testing, specific application compatibility, and regulatory requirements), providing deployment flexibility. When the compensation function is disabled, the system operates in a standard mode with zero overhead, without affecting the maximum throughput of the link, ensuring optimal performance in scenarios where latency equalization is not required.

[0174] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0175] Based on the same inventive concept, this application also provides a delay compensation device for implementing the delay compensation method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more delay compensation device embodiments provided below can be found in the limitations of the delay compensation method described above, and will not be repeated here.

[0176] In one exemplary embodiment, such as Figure 6 As shown, a delay compensation device is provided, including: a transmission module 601, wherein:

[0177] The sending module 601 is used to delay the sending time of the flow control update data packet corresponding to the link data packet when the processing of each link data packet of the target link is completed, wherein the target link is the link with the longest first real-time delay time among at least two links, and the flow control update data packet is used to return the credit of controlling the sending of the link data packet to the sending end.

[0178] In some optional embodiments, the above apparatus further includes: a compensation delay time determination module, used to measure the first real-time delay time of each link; and to calculate the compensation delay time of each target link based on the first real-time delay time of each link, with the maximum first real-time delay time as a reference.

[0179] The sending module 601 is specifically used to send the flow control update data packet corresponding to the link data packet at the specified time and to compensate for the delay time.

[0180] In some optional embodiments, the above-mentioned compensation delay time determination module is further used to generate real-time probe packets and embed a sending timestamp in the real-time probe packets; at the same time, send the generated real-time probe packets to each link; for each link, obtain the receiving timestamp of the acknowledgment packet of each real-time probe packet, and obtain the first real-time delay time of the link based on the sending timestamp and the receiving timestamp.

[0181] In some optional embodiments, the above apparatus further includes: a judgment module, configured to continue executing the step of delaying the compensation delay time by sending the flow control update data packet corresponding to the link data packet when the compensation delay time is greater than or equal to the delay threshold; and to send the flow control update data packet according to the default sending time of the flow control update data packet corresponding to the link data packet when the compensation delay time is less than the delay threshold.

[0182] In some optional embodiments, the above apparatus further includes: a verification module, configured to measure the second real-time delay time of each link; based on the second real-time delay time of each link, wherein the second real-time delay time of each link is obtained by delaying the transmission time of the flow control update data packet and based on the transmission timestamp of the probe packet retransmitted to the link and the reception timestamp of the acknowledgment packet corresponding to the probe packet, detecting whether the delay times of each link are balanced, wherein if the difference duration corresponding to each link whose second real-time delay time is not the longest is less than the delay threshold, it is determined that the delay times of each link are balanced, wherein the difference duration is the difference between the maximum second real-time delay time and the non-longest second real-time delay time; and if the delay times of each link are not balanced, redetermining the compensation delay time of each target link.

[0183] In some optional embodiments, the above apparatus further includes: an iteration module for measuring the third real-time delay time of each link; detecting whether the delay times of each link are balanced based on the third real-time delay time of each link, wherein the third real-time delay time of each link is obtained by determining that the delay times of each link are unbalanced, based on the sending timestamp of the probe packet sent to the link again and the receiving timestamp of the acknowledgment packet corresponding to the probe packet; updating the number of iterations for redetermining the compensation delay time when the delay times of each link are unbalanced; continuing to execute the step of redetermining the compensation delay time of each target link when the number of iterations is less than a threshold; and outputting an alarm message of compensation failure when the number of iterations is greater than or equal to the threshold.

[0184] Each module in the aforementioned delay compensation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0185] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface (e.g., a network interface card) is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. The computer program, when executed by the processor, implements a latency compensation method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0186] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0187] In one exemplary embodiment, a chip is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0188] In one exemplary embodiment, a network interface card is provided, including a chip as described in any of the above embodiments and multiple interfaces, through which the chip processes data or communicates externally.

[0189] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0190] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0191] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0192] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0193] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0194] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A delay compensation method, characterized in that, Applied to the receiving end, the method includes: When each link data packet of the target link is processed, the sending time of the flow control update data packet corresponding to the link data packet is delayed to balance the delay time of each link. The target link is the link with the longest first real-time delay among at least two links. The flow control update data packet is used to return credit to the sending end for controlling the sending of the link data packet. The second real-time delay time of each link is measured. The second real-time delay time of each link is obtained based on the sending timestamp of the probe packet resent to the link and the receiving timestamp of the acknowledgment packet corresponding to the probe packet after delaying the sending time of the flow control update data packet. Based on the second real-time delay time of each link, it is detected whether the delay time of each link is balanced. If the difference duration corresponding to each link whose second real-time delay time is not the longest is less than the delay threshold, it is determined that the delay time of each link is balanced. The difference duration is the difference between the maximum second real-time delay time and the second real-time delay time that is not the longest. In cases where the delay times of the various links are uneven, the compensation delay time of each target link is re-determined.

2. The method according to claim 1, characterized in that, The method further includes: Measure the first real-time delay time of each of the aforementioned links; Based on the first real-time delay time of each of the links, and taking the maximum first real-time delay time as a benchmark, the compensation delay time of each of the target links is calculated. The step of delaying the transmission time of the flow control update data packet corresponding to the link data packet includes: The transmission time of the flow control update data packet corresponding to the link data packet is delayed by the compensation delay time.

3. The method according to claim 2, characterized in that, The measurement of the first real-time delay time of each of the links includes: Generate a real-time probe packet and embed a sending timestamp into the real-time probe packet; Simultaneously, the generated real-time probe packets are sent to each of the aforementioned links; For each of the links, the receiving timestamp of the acknowledgment packet of each real-time probe packet is obtained, and the first real-time delay time of the link is obtained based on the sending timestamp and the receiving timestamp.

4. The method according to claim 2, characterized in that, After calculating the compensation delay time for each of the target links, the method further includes: If the compensation delay time is greater than or equal to the delay threshold, continue to execute the step of delaying the compensation delay time by sending the flow control update data packet corresponding to the link data packet at the same time. If the compensation delay time is less than the delay threshold, the flow control update data packet is sent according to the default sending time of the flow control update data packet corresponding to the link data packet.

5. The method according to claim 1, characterized in that, After redetermining the compensation delay time for each of the target links, the process includes: The third real-time delay time of each of the links is measured. The third real-time delay time of each link is obtained based on the sending timestamp of the probe packet sent to the link again and the receiving timestamp of the acknowledgment packet corresponding to the probe packet, when it is determined that the delay times of the links are unbalanced. Based on the third real-time delay time of each link, detect whether the delay time of each link is balanced; In the case of uneven delay times across the links, update the number of iterations for redetermining the compensation delay time; Before redetermining the compensation delay time for each of the target links, the method further includes: If the number of iterations is less than the threshold, the step of redetermining the compensation delay time for each target link continues. If the number of iterations is greater than or equal to the threshold number, an alarm message indicating compensation failure will be output.

6. A delay compensation device, characterized in that, Applied to the receiving end, the device includes: The sending module is used to delay the sending time of the flow control update data packet corresponding to the link data packet when the processing of each link data packet of the target link is completed, so as to balance the delay time of each link. The target link is the link with the longest first real-time delay among at least two links. The flow control update data packet is used to return the credit for controlling the sending of the link data packet to the sending end. The verification module is used to measure the second real-time delay time of each of the links. The second real-time delay time of each link is obtained by delaying the transmission time of the flow control update data packet, based on the transmission timestamp of the probe packet retransmitted to the link and the reception timestamp of the acknowledgment packet corresponding to the probe packet. Based on the second real-time delay time of each link, the module detects whether the delay times of each link are balanced. If the difference duration corresponding to each link with a non-longest second real-time delay time is less than the delay threshold, the delay times of each link are determined to be balanced. The difference duration is the difference between the maximum second real-time delay time and the non-longest second real-time delay time. If the delay times of each link are unbalanced, the compensation delay time of each target link is re-determined.

7. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A network interface card, characterized in that, Includes the chip as described in claim 7 and multiple interfaces. The chip processes data or communicates with the outside world through the interface.

9. A computer device, characterized in that, Includes the network interface card as described in claim 8, wherein the network interface card is used for processing data or external communication.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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