A high-speed interface control circuit for inter-core particle interconnection

Abstract

The application discloses a high-speed interface control circuit for core-particle interconnection, and is used for solving the problem of data transmission between multi-core-particle system chips. Based on a fine-grained flow control mechanism, by defining a flow control packet and a segmented data packet structure, the problem of transmission delay caused by the coarse granularity of the traditional interface flow control is solved, accurate control of single transmission is realized, and transmission delay is reduced. Based on a lightweight fault-tolerant mechanism, by combining the header, tail key information and CRC-3 check data load of the Hamming code protection packet, the problem of excessive resource consumption of the traditional error correction mechanism is solved, hierarchical protection of control information and data load is realized, and fault-tolerant overhead is reduced.

Description

Technical Field

[0001] This invention belongs to the field of chip-based circuit technology, and in particular relates to a high-speed interface control circuit for inter-chip interconnection. Background Technology

[0002] As Moore's Law slows down, chip interconnect technology has become a crucial way to overcome the limitations of chip manufacturing area. Current mainstream chip interconnect technologies face the following bottlenecks: in terms of interconnect methods, protocols such as CXL and CCIX do not fully consider the ultra-short distance characteristics of inter-chip interfaces; in terms of data transmission, interfaces such as SRIO and PCIe suffer from high resource overhead and long transmission latency. These factors collectively restrict the performance improvement of chip interconnect systems.

[0003] Existing technologies suffer from two main problems: First, the flow control mechanism is too coarse-grained. Inter-chip data transmission requires lower transmission latency, but traditional chip-to-chip interconnect solutions (such as SRIO and PCIe) employ coarse-grained flow control mechanisms ranging from 256B to 4096B. This coarse-grained control introduces significant delays in data packaging / parsing and verification processes, severely limiting the efficiency of high-real-time data transmission. Second, the fault tolerance mechanism is inefficient. Compared to traditional PCB-level transmission, inter-chip data transmission channels have lower bit error rates and better signal-to-noise ratios. However, traditional chip-to-chip interconnect solutions still rely on PCB-level fault tolerance, employing complex error correction mechanisms such as multi-level error detection, error registration, and transmission, resulting in unnecessary resource waste. Summary of the Invention

[0004] To meet the low-overhead, low-latency communication requirements of inter-chip data transmission, it is necessary to develop a high-speed inter-chip interface control circuit for multi-chip interconnection, employing fine-grained flow control and lightweight fault-tolerant methods to improve interconnection data transmission efficiency and enhance system performance.

[0005] This application provides a high-speed interface control circuit for inter-chip interconnection. The data flow path includes a packet control module, a data packet buffer module, a data stream sending module, a data packet receiving module, a data flow control module, and an unpacking control module. The packet control module, data packet buffer module, and data packet sending module are connected in sequence. The data stream receiving module, data packet buffer module, and unpacking control module are connected in sequence. The data flow control module is connected to other modules to control the overall flow.

[0006] Furthermore, the high-speed interface control circuit internally transmits two types of packets: data packets and flow control packets. The data packets carry AXI bus data transmitted externally to the high-speed interface encoding circuit; the flow control packets carry flow control information and dedicated packet transmission status from within the high-speed interface encoding circuit.

[0007] Furthermore, the data packet includes a data packet header, a data packet payload, and a data packet trailer. The data packet header and the data packet trailer carry control and fault tolerance information, while the data packet payload contains data payload and verification information. The flow control packet includes a double word containing fault tolerance information and the transmission status of data packets transmitted over a period of time.

[0008] Furthermore, both data packets and flow control packets are sent via a high-speed interface. The data packet receiving module distinguishes between flow control packets and data packets. The received data packets are buffered in the data packet buffer, and the received flow control packets are used for flow control.

[0009] Furthermore, the sending end's data packet buffer only releases its corresponding space after the data packet is successfully transmitted from the sending end's data packet buffer to the receiving end's data packet buffer module; and the data packets in the receiving end's data packet buffer module are only transmitted to the next stage after the transmission order conditions are met.

[0010] Furthermore, error correction codes are added to the packet header, packet trailer, and flow control packet as a whole, and error detection codes are added to the packet body. Fault tolerance strategies such as packet retransmission and flow control packet error correction are also used.

[0011] Compared with the prior art, the significant advancements of this invention are: (1) Through a fine-grained flow control mechanism, customized flow control packets and data packets are designed to achieve a bandwidth utilization rate of approximately 92.5%. Compared with the 82%~89% bandwidth utilization rate of traditional PCIe, SRIO, etc., the transmission efficiency is superior. In terms of transmission latency, compared with the existing SRIO3.0 IP, the latency of the designed high-speed interface controller using the FPGA platform is reduced by 32.1%.

[0012] (2) By using a lightweight fault-tolerant mechanism, a fault-tolerant method combining error correction and error detection is designed. Compared with existing PCIe3.0 and SRIO3.0 IPs, the logic resources of the designed high-speed interface controller are reduced by 87.2% using an FPGA platform.

[0013] To more clearly illustrate the functional characteristics and structural parameters of the present invention, further explanation is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall structure provided in this application;

[0015] Figure 2 This is a diagram of the flow control package format provided in this application;

[0016] Figure 3 This is a complete lifecycle diagram of a flow control package provided in this application;

[0017] Figure 4 This is a diagram of the data packet organization format provided in this application;

[0018] Figure 5 This is a diagram of the data packet payload format provided in this application;

[0019] Figure 6 This is a complete lifecycle diagram of the data packet provided in this application;

[0020] Figure 7 This is a schematic diagram of the state transition of the data packet provided in this application. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention designs a high-speed interface control circuit for inter-chip interconnection, which achieves low-overhead and low-latency inter-chip data transmission through fine-grained flow control mechanism and lightweight fault tolerance mechanism.

[0023] High-speed interface control circuit, such as Figure 1 As shown, the system includes input and output directions. The input direction receives output channels from the AXI master interface and slave interface (AW, W, and AR channels of the AXI master interface, and B and R channels of the AXI slave interface), packages them into defined data packets, and transmits them to the high-speed interface output channel. The output direction receives defined data packets from the high-speed interface input channel, unpacks them into input channels from the AXI master interface and slave interface (B and R channels of the AXI master interface, and AW, W, and AR channels of the AXI slave interface). The high-speed interface control circuit is also used to generate, send, receive, and parse defined flow control packets to achieve flow control at both ends of the link. The data flow path includes a packetization control module, a data packet buffering module, a data stream sending module, a data packet receiving module, a data flow control module, and an unpacking control module. The packetization control module, data packet buffering module, and data packet sending module are connected sequentially; the data stream receiving module, data packet buffering module, and unpacking control module are connected sequentially; the data flow control module is connected to other modules to control the overall flow.

[0024] Data transmitted from the AXI interface is first processed by packet control, with flow control and verification information added to generate data packets, which are then stored in the data packet buffer. The data stream sending module reads the data packets from the data packet buffer according to the order of data packet transmission and sends them to the high-speed interface to complete the data transmission.

[0025] Data transmitted from the high-speed interface is first received by the data stream, parsed into flow control information and sent to the data flow control, or restored into data packets and stored in the buffer. Finally, the unpacking control reads the data packets from the buffer, parses the data payload, performs verification, and outputs the data to complete the data reception.

[0026] Fine-grained flow control mechanism:

[0027] Flow control mechanisms are used to ensure the stability and efficiency of data transmission, preventing data loss or overflow due to mismatched transmission rates between the receiving and sending ends. High-speed interfaces exchange packets, which are categorized into flow control packets and data packets based on their format. Flow control packets, based on a credit authorization mechanism, manage the data transmission rates of the sending and receiving ends. Credit authorization information is exchanged between the sending and receiving ends, and the sending end adjusts the speed of sending data packets according to this information to match the processing capacity of the receiving end.

[0028] The flow control packet and data packet will be described in detail below.

[0029] Flow control package:

[0030] The flow control packet is a double-word 64-byte packet, containing the packet type (TYPE), error correction code (FEC), and flow control information (ACK, ACK_S). The packet type is an identifier used by the high-speed interface circuit to recognize and parse load control information. The flow control information is the control information carried in the flow control packet. The error correction code applies to the entire flow control packet and is used to correct possible errors during transmission. Figure 2 As shown:

[0031] The flow control information includes two types: ACK_S for flow control packets and ACK for flow control packets. Each flow control packet records the reception status of 16 data packets and the reception status of 2 flow control packets. The reception status of data packets and flow control packets is shown in Table 1.

[0032] Flow control packet transmission mechanism:

[0033] The flow control packet carries the data packet reception status of the receiving end since the last flow control packet was sent. For example... Figure 3 As shown, from the receiver's perspective, the flow control packet undergoes two checks before finally recovering the flow control information from the data stream and handing it over to subsequent processing. In the diagram, A and B are two transmission ports of a cross-coupled high-speed interface controller; A is either the sender or receiver, while B is the other. Assuming the flow control packet is generated at port A, the complete lifecycle of a flow control packet is as follows:

[0034] a) Based on the data packets and flow control packets received from B since the last flow control packet was generated, A generates a flow control packet.

[0035] b) The flow control packet is transmitted to terminal B via a high-speed interface.

[0036] c) The B-end performs a two-step verification on the data from the high-speed interface: the first step is to confirm whether it is a flow control packet based on the MAGIC_NUM and TYPE fields; the second step is to confirm the transmission status of the flow control packet based on the FEC field; if both verifications pass, that is, the second verification and error correction is successful, and the information carried in the ACK field is processed; otherwise, the corresponding flow control packet is discarded.

[0037] d) End B generates and sends a flow control packet. After End A receives the flow control packet, it performs two-step verification. Based on the ACK_S field, if the transmission fails, the previously sent ACK field is merged with the ACK generated this time; if the transmission is successful, only the ACK field of this time is transmitted.

[0038] Data packets:

[0039] Data packets carry the data payload sent in the preceding interconnect structure and constitute the main part of the traffic during transmission. The sequence maintenance and transmission queue management of data transmission described herein both target data packets; a data packet consists of a packet header, packet payload, and packet trailer, defining the information required for flow control; the packet header and packet trailer contain control, checksum, and padding bit information for this data packet; the data payload is the transmission load information. For example... Figure 4 As shown, a data packet contains a packet header, a packet trailer, and several packet payloads.

[0040]

[0041] like Figure 5 As shown, the packetization logic subdivides the information transmitted by the interconnect structure into "transmissions" and packages them into units of one transmission, adding a checksum. Specifically, in the AXI protocol, the payload of one transmission is all the data payload when data is valid on a certain channel (AW, AR, W, R, or B channel).

[0042] In addition, the entire data packet payload length is aligned to double words (64 bits), so alignment bits are added to the end of the data packet payload.

[0043] The packet trailer contains the packet payload size, special characters, and corresponding error correction codes, as shown in Table 4.

[0044] Data packet transmission mechanism:

[0045] The data packet has two flags: ID and ORDER. ID is used to distinguish the data packet's identity, for retransmission after a transmission error, and for buffer release after successful transmission. ORDER maintains the transmission order and is used by the receiving end to select the data packet when multiple data packets are ready for unpacking during the unpacking process. When a data packet is generated, the value of the ID field is determined by the current request queue, with the data flow control module allocating free IDs in the request queue. The value of the ORDER field is determined by the ORDER field of the previously generated data packet, and is the ORDER of the previously generated data packet + 1; if it overflows, it returns to 0. Figure 6 As shown, the sending and receiving ends of a pair of extended interfaces are interconnected, and the complete lifecycle of a data packet from generation to release is as follows:

[0046] a) Data packets are generated by the sender and temporarily stored in a buffer;

[0047] b) The data packet is sent for the first time, and then enters the buffer at the receiving end via the high-speed interface;

[0048] c) Based on the sequence number contained in the data packet, after the data packets preceding the data packet sequence have been completely transmitted, the data packets are read from the receiving end buffer and transmitted sequentially for unpacking and verification.

[0049] d) The verification result will be sent to the sender via the high-speed interface; if the verification passes completely, the sender will release the corresponding buffer; the receiver will advance the transmission sequence; if the verification fails, the sender will retransmit the data packet, and the receiver's transmission sequence will remain unchanged.

[0050] This application establishes a lightweight fault-tolerant mechanism.

[0051] Fault tolerance mechanisms are used to ensure the integrity and reliability of data transmission, preventing information transmission errors caused by data rollover in noisy channels. These mechanisms are based on retransmission and manage data matching between the sender and receiver. Retransmission employs an acknowledgment mechanism; after sending a data frame, the sender waits for an acknowledgment from the receiver. If the sender does not receive an acknowledgment within a certain time, it considers the data frame lost and retransmits it. Upon receiving the data frame, the receiver checks the data; if an error is found, it sends a negative acknowledgment requesting the sender to retransmit the data frame.

[0052] 1) Error Detection and Correction

[0053] In the defined packets, the FEC fields used in the packet header, packet trailer, and flow control packet payload are all FEC forward error correction codes, used to protect the critical information in the packet header and to correct errors using error correction methods; the CHK field in each transmission of the packet header is a CRC error detection code, used to verify the data information and to correct errors using retransmission methods.

[0054] 2) Packet retransmission and release strategy

[0055] During transmission, the high-speed interface control circuit buffers data packets in the data packet buffer module. The data packet buffer module can buffer multiple data packets. Only after confirming that a data packet has been successfully transmitted can the data packet buffer module release the storage space occupied by the corresponding data packet for use by the next data packet.

[0056] a) Data packet retransmission and release strategy at the sending end

[0057] The data packets are configured with four states: Notyet, Okey, Fail, and Stored. The sending end obtains the transmission status of data packets sent within a certain period by receiving and parsing the flow control packets from the receiving end, and confirms whether the data packets are discarded, retained, or retransmitted. The state transitions of the data packets are as follows: Figure 7 As shown, when a data packet is received, it transitions from the Notyet state to the Stored state. Subsequently, based on the verification result, it is converted to Fail or Okey, and returns to Notyet after notifying the sender of the verification result. Furthermore, when the receiver's buffer space is insufficient, the data packet will directly transition from the Notyet state to the Fail state.

[0058] After receiving the flow control packet, the sending end will release the data packets with a reception status of "Okey" or "Stored" and retransmit the data packets with a "Fail" status. If the data packets already cached in the data packet buffer module are returned to the "Notyet" status by the other end multiple times, the corresponding data packets will be considered lost and retransmitted. Otherwise, the corresponding data packets will be retained.

[0059] b) Receiver packet release strategy

[0060] The receiving end data packet buffer module determines whether to retain or transmit a data packet based on the "ORDER" in the data packet. It ensures that the "ORDER" of the data packets output to the subsequent load parsing module is always continuous. If the data packet buffer module does not temporarily store the next data packet with a continuous "ORDER", the data packet buffer module will stop transmitting data packets to the load parsing module and wait for the expected data packet.

[0061] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-speed interface control circuit for inter-chip interconnection, characterized in that, The high-speed interface control circuit includes two directions: input and output. The data flow path includes a packet control module, a data packet buffer module, a data stream sending module, a data stream receiving module, a data stream control module, and an unpacking control module. The packet control module, data packet buffer module, and data stream sending module are connected in sequence; the data stream receiving module, data packet buffer module, and unpacking control module are connected in sequence; the data stream control module is connected to other modules to control the overall flow. The input direction receives the AXI main interface and the output channels of the slave interface, namely the AW channel, W channel, and AR channel of the AXI main interface and the B channel and R channel of the AXI slave interface, and packages them into defined data packets for transmission to the high-speed interface output channel. The output direction receives the defined data packets from the high-speed interface input channel and unpacks them into the AXI main interface and slave interface input channels, namely the B channel and R channel of the AXI main interface and the AW channel, W channel and AR channel of the AXI slave interface. The high-speed interface control circuit is also used to generate, send, receive, and parse defined flow control packets to achieve flow control at both ends of the link; The data packet carries the payload of the data packets sent in the front-end interconnection structure; the data packet includes a data packet header, a data packet payload, and a data packet trailer, which define the information required in the flow control process; the data packet header and data packet trailer contain the control, check, and padding bit information of this data packet; the data packet payload is the transmission load information; a data packet contains one data packet header, one data packet trailer, and several data packet payloads; The data packet header is encoded as follows: the TYPE field indicates the type of packet, which is divided into retransmitted data packets and data packets transmitted for the first time; the ID field indicates the ID number of the data packet, which is used for maintaining the request queue. The ORDER field represents the sequence number of the data packet, used for maintaining data dependencies; the FEC field represents the error correction code, which applies to the entire header. The packetization logic breaks down the information transmitted by the interconnect structure into "transmissions" and packages them into units of one transmission, adding a checksum; specifically for the AXI protocol, the payload of one transmission is the payload of all data packets when a certain channel's data is valid; The entire data packet payload length is aligned to double words, with alignment bits added at the end of the data packet payload; The packet trailer contains the packet payload size, special characters, and the corresponding error correction code; The data packet has two flags: ID and ORDER. ID is used to distinguish the identity of the data packet, for retransmission after transmission errors, and for buffer release after successful transmission. ORDER maintains the transmission order and is used by the receiving end to select the data packet when multiple data packets are ready to be unpacked during the unpacking process. When a data packet is generated, the value of the ID field is determined by the current request queue, and the data flow control module allocates free IDs from the request queue; the value of the ORDER field is determined by the ORDER field of the previously generated data packet, and is the ORDER of the previously generated data packet + 1. If overflow occurs, it returns to 0; the sending and receiving ends of a pair of extended interfaces are interconnected, and the complete lifecycle of a data packet from generation to release is as follows: Step 71: The data packet is generated by the sending end and temporarily stored in the buffer; Step 72: The data packet is sent for the first time, passing through the high-speed interface and entering the buffer at the receiving end; Step 73: Based on the sequence number contained in the data packet, after the data packets preceding the data packet sequence have been completely transmitted, the data packets are read from the receiving end buffer and transmitted sequentially for unpacking and verification. Step 74: The verification result will be sent to the sending end through the high-speed interface; if the verification passes completely, the sending end will release the corresponding buffer; the receiving end will advance the transmission sequence; if the verification fails, the sending end will retransmit the data packet, and the receiving end's transmission sequence will remain unchanged.

2. The high-speed interface control circuit according to claim 1, characterized in that, Data transmitted from the AXI interface first passes through the packet control module, which adds flow control information and verification information to generate data packets, which are then stored in the data packet buffer. The data stream sending module reads the data packets from the data packet buffer according to the order of data packet transmission and sends them to the high-speed interface to complete the data transmission. Data transmitted from the high-speed interface first passes through the data stream receiving module, where it is parsed into flow control information and sent to the data flow control or restored as data packets and stored in the buffer. Finally, the unpacking control reads the data packets from the buffer, parses the data packet payload, verifies it, and outputs it to complete the data reception.

3. The high-speed interface control circuit according to claim 2, characterized in that, High-speed interfaces exchange packets, which are categorized into flow control packets and data packets based on their format. The flow control packet is based on a credit authorization mechanism and is used to manage the data transmission rate of the sending and receiving ends; The sending and receiving ends exchange credit authorization information. The sending end adjusts the speed of sending data packets according to the credit authorization information to match the processing capacity of the receiving end.

4. The high-speed interface control circuit according to claim 3, characterized in that, The flow control packet is a double word 64B in length, containing the packet type TYPE, error correction code FEC, and flow control information ACK and ACK_S. The packet type is an identifier for high-speed interface circuit identification and parsing of load control information; the flow control information is the control information carried by the flow control packet; the error correction code has the scope of the entire flow control packet and is used to correct possible errors during the transmission of the flow control packet. The flow control information includes two types: ACK_S for flow control packets and ACK for flow control packets. Each flow control packet records the reception status of 16 data packets and the reception status of 2 flow control packets. The reception status of data packets and flow control packets is as follows: The ACK status of the data packet flow control information includes Okey, Notyet, Fail, and Stored. Among them, Okey indicates that the verification passed and the buffer was released; Notyet indicates that the data packet with the corresponding ID was not received; Fail indicates that the data packet with the corresponding ID was received, but the transmission was incorrect or the buffer was full; Stored indicates that the data packet with the corresponding ID was received, but it has not yet been unpacked and verified. The status of the flow control information ACK_S in the flow control packet includes Okey and Fail; where Okey indicates that the received flow control packet was error-free; Fail indicates that the received data packet was error-free.

5. The high-speed interface control circuit according to claim 4, characterized in that, The flow control packet carries the data packet reception status of the receiving end since the last flow control packet was sent. From the receiving end's perspective, the flow control packet undergoes two-step verification, ultimately recovering the flow control information from the data stream and handing it over to subsequent processing. End A and End B are two transmission ports of a cross-coupled high-speed interface controller; where End A is either the sending end or the receiving end, and End B is the other end. Assuming that the flow control packet is generated starting from End A, the complete lifecycle of a flow control packet is as follows: Step 51: Based on the data packets and flow control packets received from B since the last flow control packet was generated, A generates a flow control packet. Step 52: The flow control packet is transmitted to the B end via the high-speed interface; Step 53: The B-end performs a two-step verification on the data from the high-speed interface: the first step is to confirm whether it is a flow control packet based on the MAGIC_NUM and TYPE fields; the second step is to confirm the transmission status of the flow control packet based on the FEC field; if both verifications pass, that is, the second verification and error correction is successful, and the information carried in the ACK field is processed; otherwise, the corresponding flow control packet is discarded. Step 54: End B generates and sends a flow control packet. After End A receives the flow control packet, it performs two verification steps. Based on the ACK_S field, if the transmission fails, the previously sent ACK field is merged with the ACK generated this time; if the transmission is successful, only the ACK field of this time is transmitted.

6. The high-speed interface control circuit according to claim 5, characterized in that, The data packets employ a fault-tolerance mechanism, which is based on retransmission and used to manage data matching between the sender and receiver; retransmission uses an acknowledgment mechanism. After sending a data frame, the sender waits for an acknowledgment from the receiver. If the sender does not receive an acknowledgment within a certain time, it assumes that the data frame is lost and retransmits it. After receiving the data frame, the receiver will check the data. If an error is found, it will send a negative acknowledgment and request the sender to retransmit the data frame. The FEC fields used in the packet header, packet trailer, and flow control packet payload are all FEC forward error correction codes, used to protect critical information in the packet header and correct errors using error correction methods. The CHK field in each transmission of the packet header is a CRC error detection code, used to verify data information and correct errors using retransmission methods.

7. The high-speed interface control circuit according to claim 6, characterized in that, During transmission, the high-speed interface control circuit buffers data packets in the data packet buffer module. The data packet buffer module can buffer multiple data packets. Only after confirming that a data packet has been successfully transmitted can the data packet buffer module release the storage space occupied by the corresponding data packet for use by the next data packet. The retransmission and release strategies for data packets at the sending end are as follows: The data packets are configured with four states: Notyet, Okey, Fail, and Stored. The sending end obtains the transmission status of the data packets sent within a certain period by receiving and parsing the flow control packets from the receiving end, and confirms whether the data packets are dropped, retained, or retransmitted. When a data packet is received, it jumps from the Notyet state to the Stored state, and is subsequently converted to Fail or Okey according to the verification result. After notifying the sending end of the verification result, it returns to Notyet. In addition, when the receiving end's buffer space is insufficient, the data packet will directly jump from the Notyet state to the Fail state. After receiving the flow control packet, the sending end will release the data packets with a reception status of "Okey" or "Stored" and retransmit the data packets with a "Fail" status. If the data packets already cached in the data packet buffer module are returned "Notyet" by the other end multiple times, the corresponding data packets will be considered lost and retransmitted. Otherwise, the corresponding data packets will be retained. The receiving end's data packet release strategy is as follows: The receiving end packet buffer module determines whether to retain or transmit a packet based on the "ORDER" in the packet. It ensures that the "ORDER" of the packets output to the subsequent load parsing module is always continuous. If the packet buffer module does not temporarily store the next packet with a continuous "ORDER", the packet buffer module will stop transmitting packets to the load parsing module and wait for the expected packet.

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