Intelligent wiring method and system in chip detection

Abstract

The application discloses a kind of intelligent wiring method and system in chip detection, method contains the following steps: based on instance segmentation model, the input chip image is identified inference, obtains the polygon coordinate information of all soldering line area;To each soldering line area obtained, the following steps are executed: region repair: the soldering line area is carried out morphological dilation processing, repair the area missing or micro-fracture caused by noise or model error in this area;Template matching: in the soldering line area image after repair, using the pre-established solder point template library, template matching is carried out through NCC normalization cross-correlation algorithm, and the position of solder point is positioned;Center extraction: the center coordinates of the area corresponding to the template matched successfully are extracted as the center coordinates of solder point: based on the center coordinates of the extracted solder point, generate soldering line detection result.The application solves the problem that the existing semiconductor AOI equipment visual formula establishment depends on manual wiring, and the efficiency is low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an intelligent wiring method and system for chip inspection. Background Technology

[0002] As the semiconductor industry continues to advance towards smaller nodes, higher densities, and higher yields, higher demands are being placed on quality inspection during the chip packaging stage. AOI (Automated Optical Inspection), as a key means of achieving non-contact and non-destructive inspection, has been widely applied in the inspection of chip wire bonding, wafer bonding, and packaging defects.

[0003] Currently, when creating visual inspection recipes, especially in the wiring stage (guiding AI to identify the direction of solder wires and the location of solder joints), AOI systems still mainly rely on manual marking and drawing of solder wire paths. This process is not only complex but also inefficient, severely hindering the automation of the entire production line.

[0004] With the development of artificial intelligence, image recognition, and machine learning, researchers have attempted to introduce deep learning technology into AOI systems to achieve automated wiring and automated recipe construction, thereby reducing manual intervention and improving system configuration efficiency. However, current technologies generally suffer from problems such as insufficient model generalization ability, unstable wire bonding features, algorithm accuracy relying on a single deep learning model, and low inference efficiency.

[0005] Therefore, developing an AI-based automatic wiring method that combines high efficiency, high precision, and high robustness to significantly shorten the visual recipe creation time is a key path to improving the intelligence level of semiconductor testing systems. Summary of the Invention

[0006] According to a first aspect of the present invention, a smart wiring method for chip inspection is provided, comprising the steps of: The instance segmentation model is used to identify and reason about the input chip image to obtain the polygon coordinate information of all bonding areas. For each obtained bonding wire area, perform the following steps: Region Repair: Morphological expansion is performed on the bonding wire area to repair the region missing or micro-fracture caused by noise or model error; Template matching: Within the repaired solder wire area image, a pre-established solder joint template library is used to perform template matching through the NCC normalized cross-correlation algorithm to locate the solder joint position; Center Extraction: Extract the center coordinates of the corresponding area of ​​the successfully matched template as the center coordinates of the solder joint. Based on the extracted center coordinates of the solder joint, the solder joint detection results are generated.

[0007] Furthermore, the process of training the instance segmentation model includes the following steps: Collect chip bonding wire images from multiple angles and under multiple operating conditions as training samples; Polygonal annotations are applied to the weld line regions in the training samples; Data augmentation is performed on the labeled training samples; The instance segmentation model is trained using the enhanced training sample set.

[0008] Furthermore, data augmentation processing includes one or more combinations of rotation, scaling, and brightness perturbation.

[0009] Furthermore, the formula for morphological dilation is: ; Where A is the original image of the bonding wire area, B is the structuring element, and Z is the image pixel position (X,Y). The size of the structuring element B is configured according to the physical size of the bonding wire.

[0010] Furthermore, the formula for the NCC normalized cross-correlation algorithm is as follows: ; in, As a template, The template mean. The region to be matched. This is the mean of the current matches.

[0011] Furthermore, the specific steps for generating the wire bonding inspection result are as follows: for a single wire bonding, the center coordinates of its two corresponding solder joints are connected, and this connection is used as the final inspection result of the wire bonding.

[0012] According to a second aspect of the present invention, a smart wiring system for chip inspection is provided, comprising: The coarse localization module is used to perform recognition and reasoning on the input chip image based on the instance segmentation model to obtain the polygon coordinate information of all bonding wire regions; The fine positioning module performs the following steps for each obtained bonding wire area: Region Repair: Morphological expansion is performed on the bonding wire area to repair the region missing or micro-fracture caused by noise or model error; Template matching: Within the repaired solder wire area image, a pre-established solder joint template library is used to perform template matching through the NCC normalized cross-correlation algorithm to locate the solder joint position; Center Extraction: Extract the center coordinates of the corresponding area of ​​the successfully matched template as the center coordinates of the solder joint. The result generation module is used to generate weld line inspection results based on the extracted weld point center coordinates.

[0013] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor executes the computer program to perform a smart wiring method for chip detection according to the first aspect.

[0014] According to a fourth aspect of the present invention, a readable medium having processor-executable non-volatile program code is provided, the program code causing the processor to run a smart wiring method for base chip detection according to a first aspect.

[0015] A smart wiring method for chip testing according to an embodiment of the present invention has the following beneficial effects: 1. Overcome the bottleneck of manual wiring efficiency and achieve intelligent and rapid deployment of visual recipes. An innovative automatic wiring method combining deep learning and traditional image processing is proposed, which significantly improves the efficiency of chip bonding area extraction and solder joint positioning. It solves the problem of low efficiency in existing semiconductor AOI equipment that relies on manual wiring for visual recipe establishment, which is conducive to the promotion and application of this type of system in actual industrial production.

[0016] 2. The model is lightweight, the algorithm is efficient, and it is compatible with a variety of industrial equipment platforms. The YOLOv11 instance segmentation model used has the advantages of being lightweight, highly adaptive, and having good recognition effect on small targets. Combined with the self-developed solder joint precise positioning algorithm, it can be flexibly deployed on different computing power platforms, supports multi-model parallel inference, and meets the needs of high-speed wiring.

[0017] 3. Standardized architecture design, adaptable to various chip packaging types. By training data and templates for different types of chips, the wire bonding model becomes more versatile and can be quickly adapted to different types of chips and different wire bonding arrangements. The system is highly reusable and has low deployment and maintenance costs in the later stages.

[0018] 4. High accuracy of automatic wiring, with robustness and interpretability. By introducing morphological structure repair and NCC template matching strategies, the AI ​​output results are corrected for errors and strengthened for boundaries. This effectively avoids problems such as false segmentation and breakage at the edge of the solder line, ensuring that the solder joint positioning meets high-precision requirements and has excellent stability and interpretability.

[0019] 5. Modular algorithm design, easy for engineering integration and expansion. The overall algorithm process is built in a modular fashion. AI models, image processing modules, inference engines, etc. can all be debugged and reused independently. It can be quickly integrated into various existing AOI systems and can also be used in other vision scenarios (such as solder joint consistency detection, chip surface foreign object detection, etc.), with good versatility and scalability.

[0020] 6. A wiring algorithm structure combining deep learning and traditional image processing is proposed. For the first time, the YOLOv11 instance segmentation model was introduced into the wire bonding and routing task for fast coarse extraction of the wire bonding region. Combined with morphological processing and normalized cross-correlation (NCC) template matching algorithm, the solder joints were accurately located, ensuring the integrity of the routing logic and the rationality of the path.

[0021] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0022] Figure 1 This is a flowchart illustrating the steps of an intelligent wiring method for chip testing according to an embodiment of the present invention.

[0023] Figure 2 This is a block diagram illustrating the principle of an intelligent wiring method for chip testing according to an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the polygonal coordinate information of the bonding area in a smart wiring method for chip inspection according to an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the wire bonding detection results in the bonding area of ​​a smart wiring method for chip testing according to an embodiment of the present invention.

[0026] Figure 5 This is a structural diagram of an intelligent wiring system for chip testing according to an embodiment of the present invention.

[0027] Figure 6 This is a structural diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0028] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, further illustrating the present invention.

[0029] First, combine Figures 1-4 This invention describes an intelligent routing method for chip inspection according to an embodiment of the present invention, which is used for chip routing and has a wide range of applications.

[0030] like Figures 1-4 As shown, an intelligent wiring method for chip testing according to an embodiment of the present invention includes the following steps: like Figure 1 , 3 As shown, in S1, the input chip image is identified and reasoned based on the instance segmentation model to obtain the polygon coordinate information of all bonding wire regions.

[0031] Furthermore, the process of training the instance segmentation model includes the following steps: High-resolution industrial cameras are used to capture images of the chip bonding area from multiple angles and under multiple conditions, which are then used as training samples. Polygonal annotations are applied to the weld line regions in the training samples; Data augmentation is performed on the labeled training samples. Data augmentation includes one or more combinations of rotation, scaling, and brightness perturbation. The instance segmentation model was trained using an enhanced training sample set. The instance segmentation model was trained using the YOLOv11 instance segmentation model, which offers the following advantages: Dynamic Convolution: Adaptively generates convolution kernels based on input features, improving fine-grained feature extraction capabilities; Self-Attention module: Enhances global contextual information fusion, improving wire bonding segmentation in complex backgrounds; Lightweight backbone network: Significantly reduces computational cost while maintaining high accuracy, making it suitable for real-time industrial deployment.

[0032] like Figure 1 As shown, in S2, for each obtained bonding wire region, the following sub-steps are performed: S21, Region Repair: Morphological expansion is applied to the bonding wire region to repair missing or micro-fractured areas caused by noise or model errors. The formula for morphological expansion is: ; Where A is the original image of the bonding wire area, B is the structuring element, and Z is the image pixel position (X,Y). The size of the structuring element B is configured according to the physical size (i.e., thickness) of the bonding wire.

[0033] S22, Template Matching: Within the repaired solder joint area image, a pre-established solder joint template library is used to perform template matching via the NCC (Normalized Cross-Correlation) algorithm to locate the solder joint position. Compared to the traditional method of locating the solder joint center using circle fitting, NCC template matching for solder joint location has advantages such as high tolerance for shape deviations (unlike circle fitting which requires a standard circle, the template can learn various actual solder joint shapes), greater robustness to changes in lighting contrast, and no need for precise edge extraction (direct matching using grayscale information avoids the edge extraction step that has extremely high image quality requirements, making it more stable and reliable). The formula for the NCC normalized cross-correlation algorithm is: ; in, As a template, The template mean. The region to be matched. This is the mean of the current matches.

[0034] S23, Center Extraction: Extract the center coordinates of the corresponding region of the successfully matched template as the center coordinates of the solder joint. like Figure 1 , 4 As shown, in S3, the weld line detection result is generated based on the extracted solder joint center coordinates. Specifically, generating the weld line detection result involves connecting the center coordinates of the two corresponding solder joints for each weld line, and using this connection line as the final detection result for the weld line.

[0035] A smart wiring method for chip testing according to an embodiment of the present invention has the following beneficial effects: 1. Overcome the bottleneck of manual wiring efficiency and achieve intelligent and rapid deployment of visual recipes. An innovative automatic wiring method combining deep learning and traditional image processing is proposed, which significantly improves the efficiency of chip bonding area extraction and solder joint positioning. It solves the problem of low efficiency in existing semiconductor AOI equipment that relies on manual wiring for visual recipe establishment, which is conducive to the promotion and application of this type of system in actual industrial production.

[0036] 2. The model is lightweight, the algorithm is efficient, and it is compatible with a variety of industrial equipment platforms. The YOLOv11 instance segmentation model used has the advantages of being lightweight, highly adaptive, and having good recognition effect on small targets. Combined with the self-developed solder joint precise positioning algorithm, it can be flexibly deployed on different computing power platforms, supports multi-model parallel inference, and meets the needs of high-speed wiring.

[0037] 3. Standardized architecture design, adaptable to various chip packaging types. By training data and templates for different types of chips, the wire bonding model becomes more versatile and can be quickly adapted to different types of chips and different wire bonding arrangements. The system is highly reusable and has low deployment and maintenance costs in the later stages.

[0038] 4. High accuracy of automatic wiring, with robustness and interpretability. By introducing morphological structure repair and NCC template matching strategies, the AI ​​output results are corrected for errors and strengthened for boundaries. This effectively avoids problems such as false segmentation and breakage at the edge of the solder line, ensuring that the solder joint positioning meets high-precision requirements and has excellent stability and interpretability.

[0039] 5. Modular algorithm design, easy for engineering integration and expansion. The overall algorithm process is built in a modular fashion. AI models, image processing modules, inference engines, etc. can all be debugged and reused independently. It can be quickly integrated into various existing AOI systems and can also be used in other vision scenarios (such as solder joint consistency detection, chip surface foreign object detection, etc.), with good versatility and scalability.

[0040] 6. A wiring algorithm structure combining deep learning and traditional image processing is proposed. For the first time, the YOLOv11 instance segmentation model was introduced into the wire bonding and routing task for fast coarse extraction of the wire bonding region. Combined with morphological processing and normalized cross-correlation (NCC) template matching algorithm, the solder joints were accurately located, ensuring the integrity of the routing logic and the rationality of the path.

[0041] The above combined with the appendix Figures 1-4 A smart routing method for chip inspection according to an embodiment of the present invention is described. Furthermore, the present invention can also be applied to a smart routing system for chip inspection.

[0042] like Figure 5 As shown, according to a second aspect of the present invention, a smart wiring system for chip inspection is provided, comprising: The coarse localization module 100 is used to perform recognition and reasoning on the input chip image based on the instance segmentation model to obtain the polygon coordinate information of all bonding wire regions; The fine positioning module 200 is used to perform the following steps for each obtained bonding wire area: Region Repair: Morphological expansion is performed on the bonding wire area to repair the region missing or micro-fracture caused by noise or model error; Template matching: Within the repaired solder wire area image, a pre-established solder joint template library is used to perform template matching through the NCC normalized cross-correlation algorithm to locate the solder joint position; Center Extraction: Extract the center coordinates of the corresponding area of ​​the successfully matched template as the center coordinates of the solder joint. The result generation module 300 is used to generate weld line detection results based on the extracted weld point center coordinates.

[0043] The above combined with the appendix Figure 5 A smart wiring system for chip inspection according to an embodiment of the present invention is described. Furthermore, the present invention can also be applied to an electronic device.

[0044] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory 1, a processor 2, and a computer program 3, wherein the computer program 3 is stored in the memory 1, and the processor 2 executes the computer program 3 to perform a smart wiring method for chip detection according to the first aspect.

[0045] According to a fourth aspect of the present invention, a readable medium having processor-executable non-volatile program code is provided, the program code causing the processor to run a smart wiring method for base chip detection according to a first aspect.

[0046] The readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of a computer program from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the ASIC can reside within a device. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc. The present invention also provides a program product comprising executable instructions stored in the readable storage medium. At least one processor of the device can read the executable instructions from the readable storage medium, and the at least one processor executes the executable instructions to cause the device to implement the intelligent wiring method for chip inspection provided in the various embodiments described above. In the embodiments of the above-described device, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0047] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A smart wiring method for chip testing, characterized in that, Includes the following steps: The instance segmentation model is used to identify and reason about the input chip image to obtain the polygon coordinate information of all bonding areas. For each obtained bonding wire area, perform the following steps: Region Repair: Morphological expansion is performed on the bonding wire area to repair the region missing or micro-fracture caused by noise or model error; Template matching: Within the repaired solder wire area image, a pre-established solder joint template library is used to perform template matching through the NCC normalized cross-correlation algorithm to locate the solder joint position; Center Extraction: Extract the center coordinates of the corresponding area of ​​the successfully matched template as the center coordinates of the solder joint. Based on the extracted solder joint center coordinates, the solder joint detection results are generated; The process of training the instance segmentation model includes the following steps: Collect chip bonding wire images from multiple angles and under multiple operating conditions as training samples; Polygonal annotations are applied to the weld line regions in the training samples; Data augmentation is performed on the labeled training samples; The instance segmentation model is trained using the enhanced training sample set.

2. The intelligent wiring method for chip testing as described in claim 1, characterized in that, The data augmentation process includes one or more combinations of rotation, scaling, and brightness perturbation.

3. The intelligent wiring method for chip testing as described in claim 1, characterized in that, The formula for the morphological dilation process is: ； Where A is the original image of the bonding wire area, B is the structuring element, and Z is the image pixel position (X,Y). The size of the structuring element B is configured according to the physical size of the bonding wire.

4. The intelligent wiring method for chip testing as described in claim 1, characterized in that, The formula for the NCC normalized cross-correlation algorithm is as follows: ； in, As a template, The template mean. The region to be matched. This is the mean of the current matches.

5. The intelligent wiring method for chip testing as described in claim 1, characterized in that, The specific method for generating the weld wire detection result is as follows: for a single weld wire, the center coordinates of its two corresponding weld points are connected, and this connection is used as the final detection result of the weld wire.

6. An intelligent wiring system for chip testing, characterized in that, Include: The coarse localization module is used to perform recognition and reasoning on the input chip image based on the instance segmentation model to obtain the polygon coordinate information of all bonding wire regions; The fine positioning module performs the following steps for each obtained bonding wire area: Region Repair: Morphological expansion is performed on the bonding wire area to repair the region missing or micro-fracture caused by noise or model error; Template matching: Within the repaired solder wire area image, a pre-established solder joint template library is used to perform template matching through the NCC normalized cross-correlation algorithm to locate the solder joint position; Center Extraction: Extract the center coordinates of the corresponding area of ​​the successfully matched template as the center coordinates of the solder joint. The result generation module is used to generate weld line inspection results based on the extracted weld point center coordinates.

7. An electronic device, characterized in that, include: The device includes a memory, a processor, and a computer program, wherein the computer program is stored in the memory and the processor executes the computer program to perform the intelligent wiring method for chip detection as described in any one of claims 1 to 5.

8. A readable medium having processor-executable non-volatile program code, characterized in that, The program code causes the processor to run the intelligent wiring method for chip detection as described in any one of claims 1-5.

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