DDR reference voltage calibration method, system, device, and storage medium

Abstract

The application discloses a DDR reference voltage calibration method, system, device and storage medium, wherein the method comprises the following steps: based on the calibrated DQS sampling clock, moving a plurality of delay positions in the horizontal direction with fixed steps; traversing the reference voltage at each delay position to determine the corresponding upper limit value and lower limit value of the reference voltage when the data signal can be correctly sampled at the current delay position, and integrating all delay positions and the corresponding upper limit value and lower limit value of the reference voltage into a data set; screening out valid sampling points from the data set; determining the target reference voltage value according to the upper limit value and lower limit value of the reference voltage of all valid sampling points, and configuring the target reference voltage value as the optimal reference voltage of the DDR memory system; and the application can avoid calibration deviation when the reference voltage exceeds the adjustable range of the register, and ensure accurate positioning of the optimal reference voltage.

Description

Technical Field

[0001] This application belongs to the field of DDR technology, specifically relating to a DDR reference voltage calibration method, system, device, and storage medium. Background Technology

[0002] With the development of DDR4, LPDDR4 and LPDDR5 memory technologies, data transmission rates and bandwidth have been significantly improved, making the guarantee of system signal integrity particularly critical. The eye width and eye height of the signal eye diagram are key indicators for measuring the quality of high-speed signals, and their stability is directly related to the reliability and performance of the system.

[0003] The factors affecting eye diagram quality are quite extensive. In order to maintain sufficient timing margin and noise tolerance under high-speed operating conditions, the existing DDR memory system has introduced a Vref (reference voltage) calibration mechanism to improve the stability of the eye height direction while ensuring sufficient eye width.

[0004] Common calibration methods typically require acquiring characteristic data reflecting signal quality and calculating the reference voltage setting based on all the data. This method is effective when the reference voltage adjustment range can fully cover the eye diagram height, but when the actual eye diagram height is large, clipping occurs, making it impossible to accurately characterize the true signal characteristics.

[0005] If the above data processing method is still used, the final determined reference voltage value will deviate from its theoretical optimal position, resulting in inaccurate calibration results and ultimately reducing the system's signal tolerance. Summary of the Invention

[0006] This application provides a DDR reference voltage calibration method, system, device, and storage medium that can avoid calibration deviations when the reference voltage exceeds the adjustable range of the register, ensuring accurate positioning of the optimal reference voltage.

[0007] To address the aforementioned technical problems, in a first aspect, this application provides a DDR reference voltage calibration method, comprising the following steps: Based on the calibrated DQS sampling clock, multiple delay positions are set in the horizontal direction by moving in fixed steps. At each of the aforementioned delay positions, the reference voltage is traversed to determine the upper and lower limits of the reference voltage corresponding to the correct sampling of the data signal at the current delay position. All delay positions and their corresponding upper and lower limits of the reference voltage are then integrated into a dataset. Valid sampling points are selected from the dataset; wherein, the upper limit of the reference voltage of the valid sampling point is not greater than the preset maximum voltage value, and the lower limit of the reference voltage of the valid sampling point is not less than the preset minimum voltage value; The target reference voltage value is determined based on the upper and lower limits of the reference voltage for all valid sampling points, and the target reference voltage value is configured as the optimal reference voltage for the DDR memory system.

[0008] As a further improvement to this application, the method of setting multiple delay positions in a fixed step manner in the horizontal direction based on the calibrated DQS sampling clock includes: Starting from the reference point of the calibrated DQS sampling clock, multiple delay positions are formed by moving horizontally from left to right in fixed steps.

[0009] As a further improvement of this application, the fixed step is 1%-10% of the data transmission unit interval of the DDR memory system, and the value range of the fixed step is 5ps to 20ps.

[0010] As a further improvement of this application, the dataset is stored in the form of a two-dimensional array, and each row of the two-dimensional array corresponds to a sampling point; Each sampling point is composed of the current delay position, the upper limit of the reference voltage corresponding to the delay position, and the lower limit of the reference voltage corresponding to the delay position.

[0011] As a further improvement of this application, when the lower limit of the reference voltage corresponding to the sampling point is greater than or equal to the preset minimum voltage value, and the upper limit of the reference voltage is less than or equal to the preset maximum voltage value, the current sampling point is selected as a valid sampling point.

[0012] As a further improvement to this application, the step of determining the target reference voltage value based on the upper limit and lower limit of the reference voltage of all valid sampling points includes: Calculate the arithmetic mean of the upper and lower limits of the reference voltage for all valid sampling points; The arithmetic mean of the upper limit average of the reference voltage and the lower limit average of the reference voltage is used as the target reference voltage value.

[0013] As a further improvement to this application, the preset maximum value and preset minimum value of voltage are determined by the adjustable range of the reference voltage register in the DDR memory system.

[0014] Secondly, this application provides a DDR reference voltage calibration system, comprising: The setting unit is used to set multiple delay positions in a fixed step in the horizontal direction based on the calibrated DQS sampling clock. The traversal unit is used to traverse the reference voltage at each of the delay positions to determine the upper limit and lower limit of the reference voltage corresponding to the correct sampling of the data signal at the current delay position, and to integrate all delay positions and their corresponding upper limit and lower limit of the reference voltage into a dataset. A filtering unit is used to filter out valid sampling points from the dataset; wherein the upper limit of the reference voltage of the valid sampling point is not greater than the preset maximum voltage value, and the lower limit of the reference voltage of the valid sampling point is not less than the preset minimum voltage value. The calculation unit is used to determine the target reference voltage value based on the upper limit and lower limit of the reference voltage of all valid sampling points, and configure the target reference voltage value as the optimal reference voltage for the DDR memory system.

[0015] Thirdly, this application provides a computer device, the computer device including a processor and a memory coupled to the processor, the memory storing a computer program, which, when executed by the processor, causes the processor to perform the steps of the above-described DDR reference voltage calibration method.

[0016] Fourthly, this application provides a computer-readable storage medium storing a computer program that is executed by a processor to implement the above-described DDR reference voltage calibration method.

[0017] The DDR reference voltage calibration method, system, device, and storage medium provided in this application have the following beneficial effects: This application sets multiple delay positions in a fixed step in the horizontal direction based on the calibrated DQS sampling clock to avoid deviations caused by timing reference deviations or incomplete timing coverage. At each delay position, the reference voltage is traversed to determine the upper and lower limits of the reference voltage that can be correctly sampled, and these are integrated into a dataset. This captures the effective voltage window corresponding to each timing point. Valid sampling points with reference voltage upper and lower limits within a preset voltage range are selected from the dataset to exclude invalid data exceeding the adjustable range of the DDR memory system reference voltage register. This fundamentally avoids calibration deviation problems caused by invalid data participating in calculations. Finally, the target reference voltage value is determined based on the reference voltage upper and lower limits of all valid sampling points and configured as the optimal reference voltage for the system. This improves the signal tolerance of the DDR memory system, reduces the risk of bit errors during high-speed data transmission, and enhances the stability and reliability of the system during high-speed operation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application, and not all of the embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.

[0019] Figure 1 This is a flowchart of the DDR reference voltage calibration method provided in the embodiments of this application.

[0020] Figure 2 This is a flowchart illustrating the calculation of the target reference voltage value in the DDR reference voltage calibration method provided in this application embodiment.

[0021] Figure 3 This is a block diagram of the DDR reference voltage calibration system provided in the embodiments of this application.

[0022] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of this application.

[0023] Figure 5 This is a schematic diagram of the structure of the storage medium provided in the embodiments of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0025] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this application are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0027] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. Furthermore, the embodiments of this application and the features in the embodiments can be combined with each other without conflict.

[0028] With the development of DDR4 (Double Data Rate 4 Synchronous Dynamic Random-Access Memory), LPDDR4 (Low Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory), and LPDDR5 (Low Power Double Data Rate 5 Synchronous Dynamic Random-Access Memory) memory technologies, data transmission rates and bandwidths have significantly improved. Ensuring system signal integrity has become particularly critical. The eye width and eye height of the signal eye diagram are key indicators for measuring the quality of high-speed signals, and their stability directly affects the reliability and performance of the system.

[0029] The factors affecting eye diagram quality are quite extensive. In order to maintain sufficient timing margin and noise tolerance under high-speed operating conditions, the existing DDR memory system has introduced a Vref (reference voltage) calibration mechanism to improve the stability of the eye height direction while ensuring sufficient eye width.

[0030] Common calibration methods typically require acquiring characteristic data reflecting signal quality and calculating the reference voltage setting based on all the data. This method is effective when the reference voltage adjustment range can fully cover the eye diagram height, but when the actual eye diagram height is large, clipping occurs, making it impossible to accurately characterize the true signal characteristics.

[0031] If the above data processing method is still used, the final determined reference voltage value will deviate from its theoretical optimal position, resulting in inaccurate calibration results and ultimately reducing the system's signal tolerance.

[0032] In view of this, please refer to Figures 1-5 This application proposes a DDR reference voltage calibration method, system, device, and storage medium, which can avoid calibration deviations when the reference voltage exceeds the adjustable range of the register and ensure accurate positioning of the optimal reference voltage.

[0033] Please refer to Figure 1 Here is a flowchart of the DDR reference voltage calibration method provided in this application, which includes the following steps: Step S1: Based on the calibrated DQS sampling clock, set multiple delay positions in the horizontal direction with fixed steps; As an optional implementation, the method of setting multiple delay positions in a fixed step manner in the horizontal direction based on the calibrated DQS sampling clock includes: Starting from the reference point of the calibrated DQS sampling clock, multiple delay positions are formed by moving horizontally from left to right in fixed steps.

[0034] As an optional implementation, the fixed step is 1%-10% of the data transmission unit interval of the DDR memory system, and the value of the fixed step ranges from 5ps to 20ps.

[0035] Understandably, the DQS (Data Strobe Signal) is used in DDR (Double Data Rate) systems as a strobe signal to latch data and provide the receiver with a precise sampling clock reference.

[0036] Specifically, during data transmission, the DQS signal is sent along with the data signal. The receiving end uses the rising and falling edges of the DQS signal to determine the timing of data acquisition, thereby ensuring the accuracy of data sampling under high-speed transmission. Therefore, it is necessary to set the delay position based on the calibrated DQS sampling clock to avoid errors caused by timing deviations.

[0037] Furthermore, based on the calibrated DQS sampling clock, multiple delay positions are set in the horizontal direction with fixed steps. The horizontal direction can be understood as the time axis corresponding to signal transmission. This application determines multiple delay positions by moving from left to right with fixed step values. Essentially, it obtains multiple discrete sampling points on the time axis. Each delay position corresponds to a unique sampling point. Reference voltage data corresponding to different sampling points are obtained in order to comprehensively evaluate the voltage change of the signal in the entire timing window. At the same time, it is also necessary to avoid the occurrence of missed sampling points.

[0038] In this embodiment, since the smaller the step size, the higher the scanning resolution, but the longer the corresponding time, the setting of a fixed step size needs to strike a balance between calibration accuracy and calibration time.

[0039] In an optional embodiment, this application sets the fixed step size to 1%-10% of the data transfer unit interval of the DDR memory system. The fixed step size is associated with the UI (Unit Interval), which is the time width for data transfer within one clock cycle. Here, the 1%-10% UI percentage is an empirical range that can capture rapid changes in signal edges while avoiding redundant measurements caused by too small a step size.

[0040] Furthermore, this application limits the range of fixed step values ​​to 5ps to 20ps, which is compatible with mainstream DDR memory systems and ensures that the DDR reference voltage calibration method provided in this application can maintain sufficient timing resolution in many application scenarios, making it highly versatile.

[0041] Step S2: Traverse the reference voltage at each delay position to determine the upper limit and lower limit of the reference voltage corresponding to the correct sampling of the data signal at the current delay position, and integrate all delay positions and their corresponding upper limit and lower limit of reference voltage into a dataset; As an optional implementation, the dataset is stored in the form of a two-dimensional array, where each row of the two-dimensional array corresponds to a sampling point; Each sampling point is composed of the current delay position, the upper limit of the reference voltage corresponding to the delay position, and the lower limit of the reference voltage corresponding to the delay position.

[0042] In this embodiment of the application, it is necessary to perform reference voltage traversal on each delay position set in step S1 to determine the voltage boundary corresponding to the delay position, that is, the upper limit and lower limit of the reference voltage corresponding to the delay position when the data signal can be sampled normally.

[0043] Typically, the lower reference voltage limit refers to the highest voltage at which the data signal can be correctly identified as logic "0" at that delay position, while the upper reference voltage limit refers to the lowest voltage at which the data signal can be correctly identified as logic "1" at the same delay position. In other words, the voltage threshold at which the data signal can be correctly identified as logic 1 and logic 0 at that delay position. These two boundary values ​​together define the effective signal voltage range at that delay position. By associating all delay positions with their corresponding upper and lower reference voltage limits, a dataset is formed to characterize the signal eye diagram profile.

[0044] In an optional embodiment, the dataset is stored in the form of a two-dimensional array, where each row represents a sampling point. Specifically, the array includes the delay position corresponding to the sampling point, the upper limit of the reference voltage corresponding to the delay position, and the lower limit of the reference voltage corresponding to the delay position, which facilitates the subsequent direct selection of valid sampling points from the dataset.

[0045] For example, a two-dimensional array a[i][j] can be used for data storage and logical judgment, where i is the row index representing different sampling points and j is the column index used to locate the different types of data stored within each sampling point.

[0046] Specifically, the value of i ranges from 0 to (X-1), where X represents the total number of sampling points in the horizontal direction. When j=0, a[i][0] stores the horizontal delay value of the sampling point; when j=1, a[i][1] stores the lower limit of the reference voltage of the sampling point; and when j=2, a[i][2] stores the upper limit of the reference voltage of the sampling point.

[0047] In this way, by using a two-dimensional array to associate the sampling point, the delay position, the upper limit of the reference voltage corresponding to the delay position, and the lower limit of the reference voltage corresponding to the delay position, it is easier to perform subsequent traversal and filtering, thereby improving the efficiency and accuracy of data processing.

[0048] Step S3: Select valid sampling points from the dataset; wherein, the upper limit of the reference voltage of the valid sampling point is not greater than the preset maximum voltage value, and the lower limit of the reference voltage of the valid sampling point is not less than the preset minimum voltage value; As an optional implementation, when the lower limit of the reference voltage corresponding to the sampling point is greater than or equal to the preset minimum voltage value, and the upper limit of the reference voltage is less than or equal to the preset maximum voltage value, the current sampling point is selected as a valid sampling point.

[0049] As an optional implementation, the preset maximum voltage and preset minimum voltage are determined by the adjustable range of the reference voltage register in the DDR memory system.

[0050] It should be noted that the reference voltage register is a hardware module in the DDR memory system that directly outputs the reference voltage. Its adjustable range is a factory-defined parameter and cannot be set by software.

[0051] Based on this, since the adjustable range of the reference voltage register in the DDR memory system is limited, the preset maximum and minimum voltage values ​​represent the actual settable voltage range of the reference voltage register. If the upper limit of the reference voltage at a certain delay position is greater than the preset maximum voltage value, a clipping phenomenon will occur. If the lower limit of the reference voltage at a certain delay position is less than the preset minimum voltage value, a clipping phenomenon will occur. This indicates that the voltage window at that delay position exceeds the hardware's own adjustment capability. Including this sampling point in the calculation will cause the subsequent calculation of the optimal reference voltage to deviate from the actual usable range. Therefore, it is necessary to filter the sampling points in the dataset and exclude invalid data that exceeds the hardware adjustment range.

[0052] In an optional embodiment, this application limits the lower limit of the reference voltage corresponding to the sampling point to be greater than or equal to the preset minimum voltage value to avoid the clipping phenomenon. At the same time, the upper limit of the reference voltage corresponding to the sampling point should be less than or equal to the preset maximum voltage value to avoid the clipping phenomenon. Only when the above conditions are met simultaneously can it be ensured that the voltage window of the sampling point is completely within the adjustable range of the hardware.

[0053] Step S4: Determine the target reference voltage value based on the upper limit and lower limit of the reference voltage for all valid sampling points, and configure the target reference voltage value as the optimal reference voltage for the DDR memory system.

[0054] As an optional implementation method, please refer to Figure 2 This is a flowchart illustrating the calculation of the target reference voltage value in the DDR reference voltage calibration method provided in this application embodiment. The step of determining the target reference voltage value based on the upper and lower limits of the reference voltage at all valid sampling points includes: Calculate the arithmetic mean of the upper and lower limits of the reference voltage for all valid sampling points; The arithmetic mean of the upper limit average of the reference voltage and the lower limit average of the reference voltage is used as the target reference voltage value.

[0055] In this embodiment, since invalid sampling points have been eliminated, the voltage boundary values ​​of all valid sampling points together define the true eye height region in the signal eye diagram. At this time, the target reference voltage value can be determined by the upper limit and lower limit of the reference voltage of all valid sampling points. The target reference voltage value is configured as the optimal reference voltage of the DDR memory system, ensuring that the optimal reference voltage of the final output can maximize the voltage noise margin of the system, significantly reduce the bit error rate under high-speed data transmission, and thus improve the overall stability and reliability of the system.

[0056] In one specific embodiment, the upper limit average reference voltage can be obtained by averaging the upper limit reference voltage values ​​of all valid sampling points, and the lower limit average reference voltage can be obtained by averaging the lower limit reference voltage values ​​of all valid sampling points. The arithmetic mean of the upper limit average reference voltage value and the lower limit average reference voltage value is used as the target reference voltage value. That is, the center position of the eye diagram is determined as the target reference voltage value, ensuring that the target reference voltage has the maximum and balanced sampling margin at all valid timing points, thereby further improving the accuracy of the calibration results.

[0057] It should be noted that the arithmetic mean calculation method provided in the embodiments of this application is only an example to illustrate the target reference voltage value, and is not the only limitation on the specific calculation method.

[0058] In practical applications, other methods that can reasonably determine the global optimal reference voltage based on the upper and lower limits of the reference voltage at effective sampling points are also feasible. For example, the upper and lower limits of the reference voltage can be weighted and averaged according to the signal quality weights at different delay positions, or the median of the upper and lower limits of the reference voltage at all effective sampling points can be taken and the average can be calculated. This application does not impose any further limitations on these methods.

[0059] The DDR reference voltage calibration method provided in this application sets multiple delay positions in the horizontal direction with fixed steps based on the calibrated DQS sampling clock. This avoids deviations caused by timing reference deviations or incomplete timing coverage. The reference voltage is traversed at each delay position to determine the upper and lower limits of the reference voltage that can be correctly sampled, and these are integrated into a dataset. This captures the effective voltage window corresponding to each timing point. Valid sampling points with reference voltage upper and lower limits within a preset voltage range are selected from the dataset to exclude invalid data exceeding the adjustable range of the DDR memory system reference voltage register. This fundamentally avoids calibration deviations caused by invalid data participating in the calculation. Finally, the target reference voltage value is determined based on the upper and lower limits of the reference voltage of all valid sampling points and configured as the optimal reference voltage for the system. This improves the signal tolerance of the DDR memory system, reduces the risk of bit errors during high-speed data transmission, and enhances the stability and reliability of the system during high-speed operation.

[0060] Based on the above DDR reference voltage calibration method, this application also provides a DDR reference voltage calibration system, please refer to... Figure 3 The present application provides a block diagram of a DDR reference voltage calibration system, which includes: The setting unit is used to set multiple delay positions in a fixed step in the horizontal direction based on the calibrated DQS sampling clock. The traversal unit is used to traverse the reference voltage at each of the delay positions to determine the upper limit and lower limit of the reference voltage corresponding to the correct sampling of the data signal at the current delay position, and to integrate all delay positions and their corresponding upper limit and lower limit of the reference voltage into a dataset. A filtering unit is used to filter out valid sampling points from the dataset; wherein the upper limit of the reference voltage of the valid sampling point is not greater than the preset maximum voltage value, and the lower limit of the reference voltage of the valid sampling point is not less than the preset minimum voltage value. The calculation unit is used to determine the target reference voltage value based on the upper limit and lower limit of the reference voltage of all valid sampling points, and configure the target reference voltage value as the optimal reference voltage for the DDR memory system.

[0061] As an optional implementation, the method of setting multiple delay positions in a fixed step manner in the horizontal direction based on the calibrated DQS sampling clock includes: Starting from the reference point of the calibrated DQS sampling clock, multiple delay positions are formed by moving horizontally from left to right in fixed steps.

[0062] As an optional implementation, the fixed step is 1%-10% of the data transmission unit interval of the DDR memory system, and the value of the fixed step ranges from 5ps to 20ps.

[0063] As an optional implementation, the dataset is stored in the form of a two-dimensional array, where each row of the two-dimensional array corresponds to a sampling point; Each sampling point is composed of the current delay position, the upper limit of the reference voltage corresponding to the delay position, and the lower limit of the reference voltage corresponding to the delay position.

[0064] As an optional implementation, when the lower limit of the reference voltage corresponding to the sampling point is greater than or equal to the preset minimum voltage value, and the upper limit of the reference voltage is less than or equal to the preset maximum voltage value, the current sampling point is selected as a valid sampling point.

[0065] As an optional implementation, determining the target reference voltage value based on the upper and lower limits of the reference voltage at all valid sampling points includes: Calculate the arithmetic mean of the upper and lower limits of the reference voltage for all valid sampling points; The arithmetic mean of the upper limit average of the reference voltage and the lower limit average of the reference voltage is used as the target reference voltage value.

[0066] As an optional implementation, the preset maximum voltage and preset minimum voltage are determined by the adjustable range of the reference voltage register in the DDR memory system.

[0067] For other details regarding the implementation techniques of each unit in the DDR reference voltage calibration system provided in the above embodiments, please refer to the description in the DDR reference voltage calibration method in the above embodiments, which will not be repeated here.

[0068] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system-type embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0069] Please refer to Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. The computer device 40 includes a processor 41 and a memory 42 coupled to the processor 41.

[0070] The memory 42 stores a computer program, which, when executed by the processor 41, causes the processor 41 to perform the steps of the comprehensive testing method for the SSD system disk in the above embodiment.

[0071] The processor 41 can also be referred to as a CPU (Central Processing Unit). The processor 41 may be an integrated circuit chip with signal processing capabilities. The processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0072] Please refer to Figure 5This is a schematic diagram of the structure of the storage medium provided in the embodiments of this application. The computer-readable storage medium of this application embodiment stores a computer program 50. The computer program 50 is executed by a processor to implement the artificial intelligence-based actuarial analysis method in the above embodiments. The computer program 50 can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or computer devices such as computers, servers, mobile phones, and tablets. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0073] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other can be through some interfaces, or indirect coupling or communication connection between devices or units, and can be electrical, mechanical, or other forms.

[0074] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0075] For example, for various devices and products applied to or integrated into chips, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into chip modules, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0076] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0077] The above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this application; however, the embodiments of this application are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this application, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this application.

Claims

1. A method for calibrating a DDR reference voltage, characterized in that, Includes the following steps: Based on the calibrated DQS sampling clock, multiple delay positions are set by moving in fixed steps in the horizontal direction; wherein, the horizontal direction is the time axis of signal transmission, starting from the reference point of the calibrated DQS sampling clock, moving in fixed steps from left to right on the time axis to form multiple delay positions, and each delay position corresponds to a unique sampling point; At each of the aforementioned delay positions, the reference voltage is traversed to determine the upper and lower limits of the reference voltage corresponding to the correct sampling of the data signal at the current delay position. All delay positions and their corresponding upper and lower limits of the reference voltage are then integrated into a dataset. Valid sampling points are selected from the dataset; wherein the upper limit of the reference voltage of the valid sampling point is not greater than the preset maximum voltage, and the lower limit of the reference voltage of the valid sampling point is not less than the preset minimum voltage, and the preset maximum voltage and preset minimum voltage are determined by the adjustable range of the reference voltage register in the DDR memory system; The target reference voltage value is determined based on the upper and lower limits of the reference voltage for all valid sampling points, and the target reference voltage value is configured as the optimal reference voltage for the DDR memory system.

2. The DDR reference voltage calibration method as described in claim 1, characterized in that, The fixed step is 1%-10% of the data transmission unit interval of the DDR memory system, and the value of the fixed step ranges from 5ps to 20ps.

3. The DDR reference voltage calibration method as described in claim 1, characterized in that, The dataset is stored in the form of a two-dimensional array, where each row of the two-dimensional array corresponds to a sampling point; Each sampling point is composed of the current delay position, the upper limit of the reference voltage corresponding to the delay position, and the lower limit of the reference voltage corresponding to the delay position.

4. The DDR reference voltage calibration method as described in claim 3, characterized in that, When the lower limit of the reference voltage corresponding to the sampling point is greater than or equal to the preset minimum voltage value, and the upper limit of the reference voltage is less than or equal to the preset maximum voltage value, the current sampling point is selected as a valid sampling point.

5. The DDR reference voltage calibration method as described in claim 1, characterized in that, Determining the target reference voltage value based on the upper and lower limits of the reference voltage at all valid sampling points includes: Calculate the arithmetic mean of the upper and lower limits of the reference voltage for all valid sampling points; The arithmetic mean of the upper limit average of the reference voltage and the lower limit average of the reference voltage is used as the target reference voltage value.

6. A DDR reference voltage calibration system, characterized in that, include: The setting unit is used to set multiple delay positions by moving in fixed steps in the horizontal direction based on the calibrated DQS sampling clock; wherein, the horizontal direction is the time axis of signal transmission, starting from the reference point of the calibrated DQS sampling clock, and moving in fixed steps from left to right on the time axis to form multiple delay positions, each delay position corresponding to a unique sampling point; The traversal unit is used to traverse the reference voltage at each of the delay positions to determine the upper limit and lower limit of the reference voltage corresponding to the correct sampling of the data signal at the current delay position, and to integrate all delay positions and their corresponding upper limit and lower limit of the reference voltage into a dataset. A filtering unit is used to filter out valid sampling points from the dataset; wherein the upper limit of the reference voltage of the valid sampling point is not greater than the preset maximum voltage value, and the lower limit of the reference voltage of the valid sampling point is not less than the preset minimum voltage value, and the preset maximum voltage value and the preset minimum voltage value are determined by the adjustable range of the reference voltage register in the DDR memory system; The calculation unit is used to determine the target reference voltage value based on the upper limit and lower limit of the reference voltage of all valid sampling points, and configure the target reference voltage value as the optimal reference voltage for the DDR memory system.

7. A computer device, characterized in that, The computer device includes a processor and a memory coupled to the processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the DDR reference voltage calibration method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is executed by a processor to implement the DDR reference voltage calibration method as described in any one of claims 1-5.

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