Combination logic for multi-level memory cells

Abstract

The invention relates to combinatorial logic for multi-level memory cells. A memory device includes a first combinatorial logic configured to receive a multi-digit representation of a stored voltage value from each of N respective memory cells in a first memory array, and each of the memory cells is configured to store a charge having one of at least three different charge levels. The first combinatorial logic can provide a first multi-bit word based on a multi-digit representation of the received stored voltage value, where the number of bits in the first multi-bit word is greater than N.

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