Circuit for implementing multi-mode output of ADC

Abstract

The application provides an ADC circuit for realizing multi-mode output, comprising a sampling sub-circuit, which collects electric data signals of multiple ports; a time-division multiplexing cyclic sub-circuit, which cyclically obtains input signals from the electric data in sequence; an ADC, which is configured to convert the input signals into digital signals; and a digital processing sub-circuit, which is configured to process the digital signals according to a set output mode, obtain a calculation value, and output a PWM wave corresponding to the output mode after comparing the calculation value with a target configuration value, thereby solving the problems of single output mode, insufficient precision and poor anti-interference capability of the traditional scheme, and having the advantages of supporting multi-mode output, improving measurement precision, enhancing anti-interference capability and realizing efficient time-division multiplexing sampling.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, and more particularly to a circuit for an ADC to achieve multi-mode output. Background Technology

[0002] Pneumatic sensors play a crucial role in gas monitoring and control systems, converting non-electrical signals such as gas pressure, flow rate, and temperature into quantifiable voltage or current signals. These sensors are widely used in various chips and other devices.

[0003] In related technologies, the aforementioned output functions are mainly achieved through control circuits. However, these control circuits can only handle a single output mode. This limitation results in a lack of flexibility for users in practical applications, such as the inability to dynamically switch output characteristics according to environmental changes. Furthermore, existing solutions suffer from low output accuracy, leading to distortion of gas state monitoring data and hindering precise control.

[0004] Therefore, how to achieve flexible switching of ADC output in different modes and improve signal processing accuracy is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides a circuit for implementing multi-mode output of an ADC, which enables the ADC output to switch flexibly in different modes, thereby improving signal processing accuracy.

[0006] On one hand, the present invention provides a circuit for an ADC to achieve multi-mode output, comprising:

[0007] The sampling sub-circuit is configured to acquire electrical data signals from multiple ports; wherein the electrical data signals include voltage signals and / or current signals.

[0008] The time-division multiplexing loop sub-circuit is electrically connected to the sampling sub-circuit and is configured to sequentially and cyclically acquire input signals from the electrical data.

[0009] The ADC, electrically connected to the time-division multiplexing loop sub-circuit, is configured to convert the input signal into a digital signal;

[0010] A digital processing sub-circuit, electrically connected to the ADC, is configured to process the digital signal according to a set output mode, obtain a calculated value, compare the calculated value with a target configured value, and output a PWM wave corresponding to the output mode; wherein, the output mode includes an average value mode, an RMS value mode, or a constant power mode.

[0011] According to the present invention, an ADC circuit for implementing multi-mode output is provided.

[0012] The number of ports is 2; the sampling sub-circuit includes a current sampling to voltage conversion component; the current sampling to voltage conversion component includes a first current sampling transistor, a first power transistor, a first selector, a second current sampling transistor, a second power transistor, a second selector, a mirror transistor, an operational amplifier, a first transmission gate, a second transmission gate, a first push-pull drive component, a second push-pull drive component, and a first resistor;

[0013] The first input terminal of the first selector is connected to the output terminal of the first push-pull drive assembly; the second input terminal of the first selector is connected to the power supply; the control terminal of the first selector is used to receive the first control signal; and the output terminal of the first selector is connected to the gate of the first current sampling tube.

[0014] The source of the first current sampling transistor is connected to the power supply, and the drain of the first current sampling transistor is connected to the negative terminal of the operational amplifier and the source of the image transistor.

[0015] The gate of the first power transistor is connected to the output terminal of the first push-pull drive assembly, the source of the first power transistor is connected to the power supply, and the drain of the first power transistor serves as the first port and is connected to the input terminal of the first transmission gate.

[0016] The first input terminal of the second selector is connected to the output terminal of the second push-pull drive assembly; the second input terminal of the second selector is connected to the power supply; the control terminal of the second selector is used to receive the second control signal; and the output terminal of the second selector is connected to the gate of the second current sampling tube.

[0017] The source of the second current sampling transistor is connected to the power supply, and the drain of the second current sampling transistor is connected to the negative terminal of the operational amplifier and the drain of the image transistor.

[0018] The gate of the second power transistor is connected to the output terminal of the second push-pull drive assembly, the source of the second power transistor is connected to the power supply, and the drain of the second power transistor serves as a second port and is connected to the input terminal of the second transmission gate.

[0019] The gate of the image transistor is connected to the output terminal of the operational amplifier, and the drain of the image transistor is connected to the first terminal of the first resistor; the second terminal of the first resistor is grounded.

[0020] The output terminal of the first transmission gate is connected to the positive terminal of the operational amplifier, and the control terminal of the first transmission gate is used to receive the inverted signal of the first control signal.

[0021] The output terminal of the second transmission gate is connected to the positive terminal of the operational amplifier, and the control terminal of the second transmission gate is used to receive the inverted signal of the second control signal.

[0022] According to the present invention, the circuit for implementing multi-mode output of an ADC is provided, wherein the ratio between the width-to-length ratio of the first current sampling transistor and the width-to-length ratio of the first power transistor is 1:K; and the ratio between the width-to-length ratio of the second current sampling transistor and the width-to-length ratio of the second power transistor is 1:K.

[0023] When the first control signal is a first-level signal and the second control signal is a second-level signal, the first selector outputs the output voltage of the first push-pull drive component, turning on the first current sampling transistor and making it the same as the gate-source voltage of the first power transistor. The second selector outputs the power supply voltage, turning off the second current sampling transistor. Simultaneously, the first transmission gate opens and the second transmission gate closes. The positive terminal of the operational amplifier is connected to the output voltage of the first power transistor, and the negative terminal of the operational amplifier is connected to the output voltage of the first current sampling transistor. The output current of the first power transistor is the ratio of the first voltage at the first terminal of the first resistor to the first resistor, multiplied by K.

[0024] When the first control signal is a second-level signal and the second control signal is a first-level signal, the second selector outputs the output voltage of the second push-pull drive component, turning on the second current sampling transistor and making it the same as the gate-source voltage of the second power transistor. The first selector outputs the power supply voltage, turning off the first current sampling transistor. The first transmission gate is closed, the second transmission gate is open, the positive terminal of the operational amplifier is connected to the output voltage of the second power transistor, and the negative terminal of the operational amplifier is connected to the output voltage of the second current sampling transistor. The output current of the second power transistor is the ratio of the second voltage at the first terminal of the first resistor to the first resistor, multiplied by K.

[0025] According to the present invention, an ADC circuit for implementing multi-mode output is provided, wherein the first transmission gate and / or the second transmission gate includes an anti-backflow circuit, the anti-backflow circuit including a first PMOS transistor, a second PMOS transistor, an NMOS transistor, and a current-limiting resistor;

[0026] The source of the first PMOS transistor is connected to the first terminal of the current-limiting resistor, and the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the NMOS transistor.

[0027] The source of the second PMOS transistor is connected to the positive terminal of the operational amplifier;

[0028] The source of the NMOS transistor is grounded;

[0029] The gates of the first PMOS transistor, the second PMOS transistor, and the NMOS transistor are used to receive control signals; wherein the control signals include either the inverted signal of the first control signal or the inverted signal of the second control signal.

[0030] When the control signal is a first level signal, the first PMOS transistor and the second PMOS transistor are turned off, the NMOS transistor is turned on, the NMOS transistor pulls down the drain voltage of the second PMOS transistor to 0, and the current limiting resistor limits the current at the output terminal of the anti-backflow circuit.

[0031] When the control signal is a second level signal, the first PMOS transistor and the second PMOS transistor are turned on, and the NMOS transistor is turned off, so that the output voltage of the first power transistor or the output voltage of the second power transistor is connected to the positive terminal of the operational amplifier.

[0032] During the current sampling process, both the first power transistor and the second power transistor remain in the on state.

[0033] According to the present invention, an ADC circuit for implementing multi-mode output is provided, wherein the sampling sub-circuit includes a voltage sampling component;

[0034] The voltage sampling assembly includes a first voltage sampling tube, a second voltage sampling tube, a second resistor, and a third resistor;

[0035] The source of the first voltage sampling transistor is connected to the drain of the first power transistor, and the drain of the first voltage sampling transistor is connected to the first terminal of the second resistor; the gate of the first voltage sampling transistor is used to receive the inverted signal of the corresponding control signal of the first voltage sampling transistor.

[0036] The source of the second voltage sampling transistor is connected to the drain of the second power transistor, and the drain of the second voltage sampling transistor is connected to the first terminal of the second resistor; the gate of the second voltage sampling transistor is used to receive the inverted signal of the corresponding control signal of the second voltage sampling transistor.

[0037] The second terminal of the second resistor is connected to the first terminal of the third resistor;

[0038] The second terminal of the third resistor is grounded;

[0039] When the inverted signal of the corresponding control signal of the first voltage sampling tube is a first level signal and the inverted signal of the corresponding control signal of the second voltage sampling tube is a second level signal, the first voltage sampling tube is turned on and the second voltage sampling tube is turned off.

[0040] When the inverted signal of the corresponding control signal of the first voltage sampling tube is a second level signal and the inverted signal of the corresponding control signal of the second voltage sampling tube is a first level signal, the first voltage sampling tube is turned off and the second voltage sampling tube is turned on.

[0041] According to the present invention, an ADC circuit for implementing multi-mode output is provided, wherein the time-division multiplexing loop sub-circuit includes a periodic signal state machine and a voltage input selector;

[0042] The periodic signal state machine is electrically connected to the voltage input selector;

[0043] The periodic signal state machine is configured to: generate a channel selection instruction based on each acquisition channel of the electrical data signal, and switch the channel selection instruction according to a set period;

[0044] The voltage input selector is configured to select the signal corresponding to the current channel selection command from the electrical data signals as the input signal.

[0045] According to the present invention, an ADC circuit for implementing multi-mode output is provided, wherein the voltage input selector includes a decoder, a selection component, and a buffer;

[0046] The input of the decoder is connected to the periodic signal state machine;

[0047] The output of the decoder is connected to the input of the selection component;

[0048] The output of the selection component is connected to the input of the buffer;

[0049] The output of the buffer is connected to the ADC.

[0050] According to the present invention, an ADC circuit for implementing multi-mode output is provided, wherein the digital processing sub-circuit includes a multiplier, an accumulator, and a comparator;

[0051] The multiplier, connected to the ADC, is configured to perform a multiplication operation on the digital signal to obtain the product value corresponding to the digital signal.

[0052] The accumulator, connected to the multiplier, is configured to accumulate the product values ​​to obtain an accumulated value;

[0053] The comparator, connected to the accumulator, is configured to compare the accumulated value with a set target value, determine the signal state corresponding to the PWM signal to be output according to the comparison result and a preset state flipping strategy, and output the PWM signal in the output mode.

[0054] According to the present invention, an ADC circuit for implementing multi-mode output is provided, wherein the digital processing sub-circuit further includes an overflow clearer, a period configurator, and an MCU;

[0055] The overflow clearer, connected to the accumulator, is configured to trigger an accumulation reset action when the actual accumulation period reaches the preset target accumulation period during the accumulation of the product value of each path.

[0056] The period configurator, connected to the overflow clearer, is configured to set the target accumulation period;

[0057] The MCU, connected to the comparator, is configured to set the target value.

[0058] According to the present invention, an ADC circuit for implementing multi-mode output is provided. In the average value mode, the coefficient of the multiplier is set to 1. The multiplier multiplies the voltage value corresponding to the digital signal with the coefficient of the multiplier to obtain the voltage value. The accumulator performs an addition operation on the voltage value to obtain the accumulated voltage value.

[0059] In the effective value mode, the multiplier squares the voltage value corresponding to the digital signal to obtain a squared value; the accumulator adds the squared value to obtain the accumulated squared value.

[0060] In the constant power mode, the multiplier performs a multiplication operation on the voltage value and the current value corresponding to the digital signal to obtain the instantaneous power value; the accumulator performs an addition operation on the instantaneous power value to obtain the power accumulation value.

[0061] The ADC circuit provided by this invention, which enables multi-mode output, achieves efficient acquisition, time-division multiplexing conversion, and multi-mode PWM output of multiple signals through the coordinated operation of the sampling sub-circuit, the time-division multiplexing loop sub-circuit, the ADC, and the digital processing sub-circuit. It solves the problems of single output mode, insufficient accuracy, and poor anti-interference capability of traditional solutions, and has the advantages of supporting multi-mode output, improving measurement accuracy, enhancing anti-interference capability, and achieving efficient time-division multiplexing sampling. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0063] Figure 1This is a schematic diagram of the circuit structure for the ADC of this invention to achieve multi-mode output;

[0064] Figure 2 This is a schematic diagram of the circuit structure of the current sampling to voltage conversion component of the present invention;

[0065] Figure 3 This is a schematic diagram of the anti-backflow circuit structure of the present invention;

[0066] Figure 4 This is a schematic diagram of the circuit structure of the voltage sampling component of the present invention;

[0067] Figure 5 This is a schematic diagram of the circuit structure of the voltage input selector of the present invention;

[0068] Figure 6 This is a schematic diagram of the circuit structure of the ADC used in this invention. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0070] In traditional pneumatic sensor chip applications, existing technologies typically only achieve constant average or constant root-mean-square voltage output modes, failing to support dynamic switching between different modes. Research has revealed that the fundamental problem lies in the control circuit structure being designed solely for a single output characteristic, lacking the ability to collaboratively process multi-dimensional electrical data signals. This prevents the system from flexibly adjusting its output strategy according to actual application scenarios. The resulting signal processing limitations directly impact the adaptability and control accuracy of gas state monitoring, specifically manifesting as a loss of data continuity during output mode switching and increased sensitivity to PVT fluctuations, thereby weakening the reliability of gas parameter quantification.

[0071] If the aforementioned technical issues are not effectively resolved, pneumatic sensor chips will continue to face the problem of rigid signal processing mechanisms in multi-mode output scenarios. The resulting decrease in output accuracy will lead to distortion of gas state monitoring data, causing the control system to execute operations based on incorrect parameters, resulting in environmental parameters deviating from set thresholds. Furthermore, the sensitivity of PVT fluctuations (fluctuations or deviations in process, voltage, and temperature) to a single output mode will exacerbate system instability, making it impossible for the sensor to maintain output consistency under process deviations or temperature changes, ultimately affecting the reliability of overall monitoring and control functions.

[0072] Therefore, this invention proposes a circuit for an ADC to achieve multi-mode output, wherein, Figure 1 This is a schematic diagram of the circuit structure for the ADC of this invention to achieve multi-mode output, as shown below. Figure 1 As shown, the circuit for implementing multi-mode output of this ADC may include a sampling sub-circuit 1, a time-division multiplexing loop sub-circuit 2, an analog-to-digital converter (ADC) 3, and a digital processing sub-circuit. Among them, the sampling sub-circuit 1, parts of the time-division multiplexing loop sub-circuit 2, and ADC 3 constitute the analog processing sub-circuit.

[0073] Sampling sub-circuit 1 is configured to acquire electrical data signals from multiple ports; wherein the electrical data signals include voltage signals and / or current signals;

[0074] Time-division multiplexing loop sub-circuit 2 is electrically connected to sampling sub-circuit 1 and is configured to sequentially and cyclically acquire input signals from electrical data.

[0075] ADC3, electrically connected to time-division multiplexing loop sub-circuit 2, is configured to convert the input signal into a digital signal;

[0076] The digital processing sub-circuit, electrically connected to ADC3, is configured to process digital signals according to the set output mode, obtain calculated values, compare the calculated values ​​with the target configured values, and output the PWM wave corresponding to the set output mode; wherein, the output mode includes average value mode, RMS mode, or constant power mode.

[0077] In a specific implementation, sampling sub-circuit 1 refers to the hardware module used to acquire multi-port electrical signals. Specifically, it can be implemented using a composite circuit including a voltage sampling component and a current sampling-to-voltage component 11, directly acquiring port voltage and current information through physical connections. Time-division multiplexing loop sub-circuit 2 refers to the control module that implements sequential sampling of multiple signals. Specifically, it can be implemented using a combination of a periodic signal state machine 21 and a voltage selector, achieving automatic switching of signal channels through timing control. ADC3 refers to an analog-to-digital converter, specifically implemented using a successive approximation conversion structure, converting analog signals into digital signals for subsequent processing. Digital processing sub-circuit refers to a programmable computing module, specifically implemented using a digital logic circuit including a multiplier 41, an accumulator 42, and a comparator 43, achieving numerical calculations in different modes by configuring operational parameters. Output modes include average value mode, RMS value mode, and constant power mode, specifically implemented through preset algorithm parameters. For example, in average value mode, an arithmetic mean operation is performed; in RMS value mode, square root and sum of squares operations are performed; and in constant power mode, voltage and current product operations are performed.

[0078] Specifically, during operation, the sampling sub-circuit 1 simultaneously acquires voltage and current signals from multiple ports. The time-division multiplexing loop sub-circuit 2 sequentially selects signals from different ports as inputs according to a preset cycle; for example, it selects the voltage signal from the first port in the first cycle and the current signal from the first port in the second cycle. The ADC3 converts the selected analog signal into a digital signal and transmits it to the digital processing sub-circuit. The digital processing sub-circuit performs corresponding calculations based on the currently set output mode: in average value mode, it performs an arithmetic average of the voltage signal; in RMS mode, it performs a root mean square calculation of the voltage signal; and in constant power mode, it performs a product operation on the voltage and current signals. After comparing the calculation result with a preset target value, output control is achieved by adjusting the duty cycle of the PWM wave. The entire process uses digital signal processing to achieve mode switching, avoiding the structural limitations of traditional analog circuits.

[0079] This solution achieves multi-mode output functionality through the configurability of the digital processing module, enhancing system adaptability. Furthermore, the use of time-division multiplexing technology significantly reduces hardware resource consumption. In addition, digital signal processing improves anti-interference capabilities.

[0080] Through the above technical solutions, this invention achieves flexible switching between multiple output modes, simultaneously meeting the needs of average value, RMS value, and power monitoring. The use of digital processing improves calculation accuracy and reduces the impact of environmental factors on measurement results. The time-division multiplexing mechanism optimizes hardware resource allocation and reduces circuit complexity. The configurable output modes expand application scenarios, making it suitable for industrial automation systems, smart home devices, and other applications requiring comprehensive monitoring of multiple parameters.

[0081] It should be noted that a user interaction interface can be set, such as a physical button, touch screen, or host computer communication interface. Users input mode selection commands through this interface, such as pressing the corresponding mode button or sending a communication command containing a mode identifier. The interface signals are monitored in real time. When a user command is detected, it is decoded to identify its corresponding mode type (average value mode, RMS mode, or constant power mode). After parsing, the identified target operating mode information is written to a system register or a designated memory area as a reference for subsequent signal processing.

[0082] By directly responding to user commands, users can actively select the operating mode according to actual application needs (such as scenarios where voltage stability requirements focus on average value, root mean square value, or constant power), which improves the system's operational flexibility and scenario adaptability, ensuring that users can accurately control voltage regulation targets as needed.

[0083] A preset scene recognition parameter library can also be established, containing scene features adapted to average value mode, RMS mode, or constant power mode. The ADC3 collects key parameters of the current working scene in real time, including real-time input voltage fluctuation data, load impedance characteristics, and harmonic component ratios. The collected parameters are compared and matched with the preset scene recognition parameter library. If the parameters match the average value mode adaptation characteristics (e.g., smooth voltage fluctuations, purely resistive load), the target working mode is automatically determined to be average value mode. If the parameters match the root mean square (RMS) mode adaptation characteristics (e.g., voltage containing high-frequency harmonics, inductive or capacitive load), the target working mode is automatically determined to be RMS mode. If the parameters match the constant power mode (e.g., the load is a dynamically adjusted device such as a switching power supply VDD, and voltage and current show a significant negative correlation), the target working mode is automatically determined to be constant power mode. After determination, the mode information is written to the storage area for subsequent module calls.

[0084] By automatically collecting and intelligently matching scene parameters, the system can select the optimal working mode based on the actual working conditions without manual intervention, thereby improving the automation and intelligence level of the system, avoiding the decrease in control accuracy caused by manual selection deviation, and ensuring stable and accurate voltage regulation in complex or dynamically changing scenarios.

[0085] In some embodiments, the present invention further proposes a circuit for implementing multi-mode output of an ADC, including a sampling sub-circuit 1 configured to acquire electrical data signals from two ports, wherein the electrical data signals include voltage signals and current signals. The sampling sub-circuit 1 includes a current-to-voltage sampling component 11. Figure 2 This is a schematic diagram of the circuit structure of the current sampling to voltage conversion component of the present invention, as shown below. Figure 2As shown, the current sampling to voltage conversion component 11 includes a first current sampling transistor T1, a first power transistor T3, a first selector MUX1, a second current sampling transistor T2, a second power transistor T4, a second selector MUX2, a mirror transistor T5, an operational amplifier AMP, a first transmission gate TG1, a second transmission gate TG2, a first push-pull drive component 111, a second push-pull drive component 112, and a first resistor R1. The first input terminal of the first selector MUX1 is connected to the output terminal of the first push-pull drive component 111, the second input terminal is connected to the power supply VDD, the control terminal receives the first control signal iat1_en, and the output terminal is connected to the gate of the first current sampling transistor T1. The source of the first current sampling transistor T1 is connected to the power supply VDD, and the drain is connected to the negative terminal of the operational amplifier AMP and the source of the mirror transistor T5. The gate of the first power transistor T3 is connected to the output terminal of the first push-pull drive component 111, the source is connected to the power supply VDD, and the drain serves as the first port AT1 and is connected to the input terminal of the first transmission gate TG1. The first input of the second selector MUX2 is connected to the output of the second push-pull drive assembly 112, and the second input is connected to the power supply VDD. The control terminal receives the second control signal iat2_en, and the output is connected to the gate of the second current sampling transistor T2. The source of the second current sampling transistor T2 is connected to the power supply VDD, and the drain is connected to the negative terminal of the operational amplifier AMP and the source of the image transistor T5. The gate of the second power transistor T4 is connected to the output of the second push-pull drive assembly 112, the source is connected to the power supply VDD, and the drain serves as the second port AT2 and is connected to the input of the second transmission gate TG2. The gate of the image transistor T5 is connected to the output of the operational amplifier AMP, and the drain is connected to the first terminal of the first resistor R1, with the second terminal of the first resistor R1 grounded. The output of the first transmission gate TG1 is connected to the positive terminal of the operational amplifier AMP, and the control terminal receives the inverted signal iat1_enn of the first control signal. The output of the second transmission gate TG2 is connected to the positive terminal of the operational amplifier AMP, and the control terminal receives the inverted signal iat2_enn of the second control signal.

[0086] The current sampling to voltage conversion component 11 is a module that converts current signals into voltage signals. Specifically, it can be implemented using a combination of a transistor mirror T5 and an operational amplifier AMP, generating a voltage signal proportional to the input current through the mirrored current. The first selector MUX1 and the second selector MUX2 are electronic switches used to switch signal paths. Specifically, they can be implemented using multiplexers or analog switches, selecting either a push-pull drive signal or the power supply VDD voltage as the output based on the control signal. The transmission gate is a switching circuit that controls the on / off state of the control signal. Specifically, it can be implemented using a CMOS transmission gate structure, determining whether to transmit the port signal to the operational amplifier AMP through the control signal. The push-pull drive component is a circuit that provides high and low level drive capabilities. Specifically, it can be implemented using complementary transistor pairs, used to control the conduction state of the power transistor. The operational amplifier AMP is an integrated circuit used for voltage comparison and signal amplification. Specifically, it can adopt a differential input single-ended output structure to ensure that the source-drain voltages of the sampling transistor and the power transistor are consistent.

[0087] Specifically, in the current sampling to voltage conversion component 11, the ratio between the width-to-length ratio of the first current sampling transistor T1 and the width-to-length ratio of the first power transistor T3 is 1:K, and the ratio between the width-to-length ratio of the second current sampling transistor T2 and the width-to-length ratio of the second power transistor T4 is also 1:K. When the first control signal iat1_en is a first level signal (high level signal in this embodiment) and the second control signal iat2_en is a second level signal (low level signal in this embodiment), the first selector MUX1 outputs the output voltage of the first push-pull drive component 111, which turns on the first current sampling tube T1 and makes it the same as the gate-source voltage of the first power tube T3. The second selector MUX2 outputs the power supply VDD voltage to turn off the second current sampling tube T2. At the same time, the first transmission gate TG1 is turned on and the second transmission gate TG2 is turned off. The positive terminal of the operational amplifier AMP is connected to the output voltage of the first power tube T3, and the negative terminal is connected to the output voltage of the first current sampling tube T1 to ensure that the source-drain voltage is consistent. At this time, the output current of the first power tube T3 is calculated by multiplying the first voltage viat1 of the first terminal of the first resistor R1 by the resistance ratio K. When the control signal state switches, the second current sampling transistor T2 is turned on, and the output current of the second power transistor T4 is calculated in the same way. That is, when the first control signal iat1_en is a second level signal and the second control signal iat2_en is a first level signal, the second selector MUX2 outputs the output voltage of the second push-pull drive component 112, causing the second current sampling transistor T2 to turn on and have the same gate-source voltage as the second power transistor T4. The first selector MUX1 outputs the power supply VDD voltage, causing the first current sampling transistor T1 to turn off. The first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, the positive terminal of the operational amplifier AMP is connected to the output voltage of the second power transistor T4, and the negative terminal of the operational amplifier AMP is connected to the output voltage of the second current sampling transistor T2. The output current of the second power transistor T4 is the ratio of the second voltage viat2 at the first end of the first resistor R1 to the first resistor R1, multiplied by K. In this way, by alternately switching the control signals of the two ports, time-division multiplexing sampling is achieved, while the operational amplifier AMP ensures the accurate correspondence between current and voltage during the sampling process.

[0088] The width-to-length ratio refers to the size ratio between the current sampling transistor and the power transistor. Specifically, it can be achieved using the ratio of the transistor channel width to length in semiconductor manufacturing processes. This ratio directly affects the accuracy of the current mirror. The voltage input to the negative and positive terminals of the operational amplifier (AMP) is controlled by the transmission gate control signal path, which can be implemented using analog switching circuits to maintain the source-drain voltage consistency between the sampling transistor and the power transistor. The level switching of the control signal refers to controlling the conduction state of the selector and transmission gate through digital logic signals. Specifically, it can be implemented using high-low level drive circuits to achieve time-division multiplexing of multi-channel sampling.

[0089] Specifically, during current sampling, when the first control signal iat1_en is high and the second control signal iat2_en is low, the first selector MUX1 transmits the output voltage of the first push-pull drive component 111 to the gate of the first current sampling transistor T1, making it form the same gate-source voltage as the first power transistor T3. At this time, the second selector MUX2 outputs the power supply VDD voltage, keeping the second current sampling transistor T2 in the off state. The first transmission gate TG1 is turned on, connecting the output voltage of the first power transistor T3 to the positive terminal of the operational amplifier AMP, while the second transmission gate TG2 is turned off to isolate the signal of the second power transistor T4. The operational amplifier AMP compares the output voltages of the first current sampling transistor T1 and the first power transistor T3, driving the mirror transistor T5 to adjust its gate voltage, making the source-drain voltages of the two consistent. At this time, the current flowing through the first resistor R1 forms a mirror relationship with the output current of the first power transistor T3. By measuring the voltage across the resistor and combining it with the aspect ratio coefficient K, the output current of the power transistor can be accurately calculated. When the control signal state is reversed, the second current sampling transistor T2 and the second power transistor T4 enter the working state and realize current measurement through the same mechanism.

[0090] This solution introduces a closed-loop feedback structure consisting of a mirror transistor T5 and an operational amplifier AMP, forcing the source-drain voltages of the sampling transistor and the power transistor to be consistent, thus eliminating sampling errors caused by voltage differences. Furthermore, this solution uses a time-division multiplexing control signal to switch sampling channels, combined with real-time adjustment of the source-drain voltage by the operational amplifier AMP, effectively eliminating inter-channel interference and improving current mirror accuracy. Simultaneously, the current calculation method combining the width-to-length ratio parameter with resistance measurement avoids the shortcomings of traditional solutions that rely on complex calibration circuits.

[0091] Through the above technical solution, this invention combines high-precision current sampling with multi-channel time-division multiplexing, effectively eliminating the impact of power transistor operating status on sampling accuracy in dual-port current signal acquisition scenarios. The closed-loop feedback mechanism of the operational amplifier (AMP) ensures the stability of the current mirror ratio, and the coordinated control of the transmission gate and selector enables interference-free alternating sampling between the two ports. This structure is particularly suitable for applications requiring simultaneous monitoring of multiple high-current signals and high sampling accuracy, such as power supply VDD management or multi-channel sensor systems.

[0092] It should be noted that the time-division multiplexing sampling mechanism has adaptive range capability, and can flexibly expand the number of sampling channels and the duration allocation in multi-range mode. When switching to n-range mode, the periodic signal state selector automatically adjusts the sequence length of the control signal, activates multiple voltage and current channels, and the power parameters of each range can be configured independently.

[0093] In multi-level mode, the duration allocation can be dynamically planned based on the differences in power configuration and signal characteristics of different levels. First, for the voltage channels (VAT1 to VATn) and current channels (IAT1 to IATn) of each level, priority is given to allocating longer sampling durations to levels with higher power configurations to ensure the integrity of signal acquisition for high-power levels. Second, a uniform buffer interval can be reserved to avoid crosstalk between adjacent channels. Finally, within a complete sampling cycle, the sampling order of each level channel is coordinated by the periodic signal state selector, prioritizing the sampling of high-priority levels, and allocating the remaining time slots to low-priority levels as needed, ensuring both the timeliness of data acquisition for each level and overall sampling efficiency.

[0094] Specifically, a priority and duration mapping table for power levels can be constructed based on the dynamic control signal generated by the periodic signal state selector. The table presets the basic sampling duration corresponding to different power levels. Then, the initial load resistance value of each power level is collected by ADC3. If the load resistance of a certain power level is higher than the average value by 20%, the sampling duration of that power level is automatically extended by 10% to compensate for the impact of resistance fluctuations on signal acquisition. At the same time, an adaptive buffering mechanism is introduced. When the signal difference between adjacent channels is detected to exceed the threshold (such as voltage difference > 0.3V), the buffer duration between the two channels is increased to 8μs in real time, and vice versa. In addition, a redundant time period pool is set at the end of each sampling period. If a signal abnormality occurs during the sampling process of a certain power level, 5-10μs of supplementary sampling is retrieved from the redundant time period pool to ensure data integrity. Finally, the voltage input selector 22 switches the channels according to the above logic to achieve accurate and dynamic allocation of sampling duration for multiple power levels.

[0095] This design not only eliminates the need for additional ADC3 hardware, but also enables a single ADC3 to accurately capture electrical signals from different channels at different times through a dynamic time-division strategy. This provides comprehensive and synchronous data support for subsequent power calculations, solving the power calculation error problem caused by channel redundancy and data asynchrony in traditional sampling from the source.

[0096] In some embodiments, the transmission gate may include an anti-backflow circuit. Figure 3 This is a schematic diagram of the anti-backflow circuit structure of the present invention, as shown below. Figure 3 As shown, the anti-backflow circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, an NMOS transistor MN, and a current-limiting resistor R. The source of the first PMOS transistor MP1 is connected to the first terminal of the current-limiting resistor R, and the drain of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2 and the drain of the NMOS transistor MN. The source of the second PMOS transistor MP2 is connected to the positive terminal of the operational amplifier AMP. The source of the NMOS transistor MN is grounded. The gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the NMOS transistor MN are used to receive the control signal enn. The control signal enn includes either the inverted signal iat1_enn of the first control signal or the inverted signal iat2_enn of the second control signal. The inverted signal can be implemented by a corresponding inverter. When the control signal is at the first level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off, while the NMOS transistor MN is turned on. The NMOS transistor MN pulls down the drain voltage of the second PMOS transistor MP2 to 0. Simultaneously, the current-limiting resistor R limits the current at the output of the anti-reverse current circuit. Figure 3 The current between the input and output I / O of the anti-backflow circuit is controlled to prevent damage to the TG module from high voltage and high current. When the control signal is the second level signal, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, and the NMOS transistor MN is turned off, so that the output voltage of the first power transistor T3 or the output voltage of the second power transistor T4 is connected to the positive terminal of the operational amplifier AMP. During the current sampling process, both the first power transistor T3 and the second power transistor T4 remain in the on state.

[0097] It should be noted that the first port AT1 and the second port AT2 can actually represent different channels and their corresponding sampling ports, so iat1_enn and iat2_enn are not necessarily related. When acquiring electrical data from the second port AT2, the inverted signal of the first control signal, vat1_enn, is high, and the inverted signal of the second control signal, vat2_enn, is low; however, this does not mean that they must be one high and one low. There may be other situations when sampling simultaneously or not sampling at all, which will not be illustrated here.

[0098] The anti-backflow circuit refers to a circuit structure used to prevent current from flowing in the opposite direction. It can be implemented using a series PMOS transistor and an NMOS transistor MN, with the conduction path switched by a control signal. The current-limiting resistor R is a resistor used to limit the current magnitude, and can be implemented using a metal film resistor or a thick film resistor. It is connected in series in the signal path to reduce the current peak. The first PMOS transistor MP1 and the second PMOS transistor MP2 are P-type metal-oxide-semiconductor field-effect transistors, which can be manufactured using bulk silicon or SOI processes, and their source-drain conduction state is controlled by the gate voltage. The NMOS transistor MN is an N-type metal-oxide-semiconductor field-effect transistor, which can be an enhancement-mode device structure used to implement a voltage pull-down function under a specific control signal.

[0099] Specifically, the backflow prevention circuit switches the on and off states of the transmission gate via a control signal. When the control signal is high, the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off due to the high-level signal, while the gate of the NMOS transistor MN is turned on. At this time, the NMOS transistor MN pulls the drain node voltage of the second PMOS transistor MP2 down to ground potential, forming a low-impedance path. Simultaneously, the current-limiting resistor R limits the output current, preventing the large current output by the power transistor from directly impacting the transmission gate. When the control signal is low, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, and the NMOS transistor MN is turned off. The output voltage of the power transistor is transmitted to the input of the operational amplifier AMP through the two turned-on PMOS transistors. This operating mode keeps the power transistor continuously on during current sampling, avoiding interference to the main power path during the sampling process.

[0100] This solution actively establishes a low-impedance path during turn-off by adding a pull-down path for the NMOS transistor MN and a current-limiting resistor R, effectively eliminating the reverse current path. Existing technologies require an additional reverse cutoff diode, while this solution utilizes existing control signals to achieve dual protection, saving on the number of components and improving reliability.

[0101] Through the above technical solution, the present invention effectively prevents reverse current surges under high current conditions. In the transmission gate off state, a protection mechanism is formed by the current limiting resistor R and the NMOS transistor MN pull-down, which avoids the large current output by the power transistor directly acting on the internal devices of the transmission gate, ensuring the safe operation of the circuit when sampling at a high current of 5A or more, while maintaining the normal working state of the power transistor during the sampling period.

[0102] In some embodiments, the present invention further proposes a sampling sub-circuit 1 including a voltage sampling component. Figure 4 This is a schematic diagram of the circuit structure of the voltage sampling component of the present invention, as shown below. Figure 4As shown, the voltage sampling assembly includes a first voltage sampling transistor T6, a second voltage sampling transistor T7, a second resistor R2, and a third resistor R3; the source of the first voltage sampling transistor T6 is connected to the drain of the first power transistor T3, and the drain of the first voltage sampling transistor T6 is connected to the first terminal of the second resistor R2; the gate of the first voltage sampling transistor T6 is used to receive the inverted signal vat1_enn corresponding to the control signal; the source of the second voltage sampling transistor T7 is connected to the drain of the second power transistor T4, and the drain of the second voltage sampling transistor T7 is connected to the first terminal of the second resistor R2; ... third voltage sampling transistor T6 is connected to the drain of the first power transistor T4, and the third voltage sampling transistor T7 is connected to the first terminal of the second resistor R2; the fourth voltage sampling transistor T6 is connected to the drain of the first power transistor T4, and the third voltage sampling transistor T7 is connected to the drain of the second power transistor T4. The gate of the second voltage sampling transistor T7 is used to receive the inverted signal vat2_enn of the corresponding control signal; the second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3; the second terminal of the third resistor R3 is grounded; when the inverted signal vat1_enn of the corresponding control signal of the first voltage sampling transistor T6 is a first-level signal and the inverted signal vat2_enn of the corresponding control signal of the second voltage sampling transistor T7 is a second-level signal, the first voltage sampling transistor T6 is turned on and the second voltage sampling transistor T7 is turned off; the voltage of the first port AT1 is... When the inverted control signal vat1_enn of the first voltage sampling transistor T6 is a second-level signal and the inverted control signal vat2_enn of the second voltage sampling transistor T7 is a first-level signal, the first voltage sampling transistor T6 is turned off, and the second voltage sampling transistor T7 is turned on. The voltage at the second port AT1 is... In this configuration, the drive signal G1 for the first power transistor T3 comes from the first push-pull drive assembly 111, and the drive signal G2 for the second power transistor T4 comes from the second push-pull drive assembly 112. The ratio of the second resistor R2 to the third resistor R3 is 2.

[0103] The voltage sampling transistor refers to the field-effect transistor used to sample the output voltage of the power transistor. It can be implemented using a PMOS or NMOS transistor MN, and its conduction state is directly controlled by the inverted control signal. The voltage divider circuit is a network formed by the second resistor R2 and the third resistor R3 connected in series. It can be implemented using precision resistors and is used to proportionally reduce the high input voltage to a range suitable for ADC3 sampling. The inverted control signal is the level signal obtained by logically inverting the original control signal. It can be implemented using an inverter circuit and is used to control the alternating conduction of the two voltage sampling transistors.

[0104] Specifically, when the inverted control signal vat1_enn of the first voltage sampling transistor T6 is high and the inverted control signal vat2_enn of the second voltage sampling transistor T7 is low, the gate of the first voltage sampling transistor T6 receives a high-level signal and turns on, while the gate of the second voltage sampling transistor T7 receives a low-level signal and turns off. At this time, the output voltage of the source of the first power transistor T3 enters the voltage divider circuit through the conducting first voltage sampling transistor T6. The voltage value after voltage division is the ratio of the input voltage to the total resistance of the second resistor R2 and the third resistor R3. When the control signal state switches, the second voltage sampling transistor T7 turns on and samples the voltage of the source of the second power transistor T4. The voltage divider circuit reduces this voltage value by the same proportion. By alternately switching the conduction states of the two voltage sampling transistors, time-division sampling of the voltages of two independent ports is achieved, and the voltage divider circuit linearly converts the high voltage signal into a low voltage signal to adapt to the input range of ADC3.

[0105] Compared to existing technologies, traditional voltage sampling circuits typically employ a single sampling channel or a complex multiplexer structure, which suffers from limited input voltage range and sampling accuracy significantly affected by resistor matching. This solution combines a voltage divider circuit with complementary control logic to achieve dual-channel voltage sampling while extending the dynamic range of the input voltage using resistor voltage division. Furthermore, complementary control signals eliminate crosstalk between channels, simplifying the control logic complexity.

[0106] Through the above technical solution, the present invention achieves safe and reliable sampling of high voltage signals, expands the applicable range of the circuit's input voltage, and ensures the independence and accuracy of dual-channel sampling through complementary control logic, reduces the impact of resistor matching accuracy on the sampling results, and provides a stable low-voltage input signal for subsequent ADC3 conversion.

[0107] In some embodiments, the present invention further proposes a circuit for implementing multi-mode output of an ADC, such as... Figure 1 As shown, the time-division multiplexing loop sub-circuit 2 includes a periodic signal state machine 21 and a voltage input selector 22. The periodic signal state machine 21 is electrically connected to the voltage input selector 22. The periodic signal state machine 21 is configured to generate a channel selection command based on each acquisition channel of the electrical data signal and switch the channel selection command according to a set period. The voltage input selector 22 is configured to select the signal corresponding to the current channel selection command from the electrical data signal as the input signal.

[0108] Among them, the periodic signal state machine 21 refers to a logic control module that can generate channel switching instructions according to preset timing rules. Specifically, it can be implemented using a finite state machine or a microprogrammed controller. It drives state transitions through an internal clock signal, automatically cyclically switching the acquisition channels, thus solving the problem of requiring external intervention to control channel switching in traditional multi-channel sampling systems. The voltage input selector 22 refers to a multi-channel analog signal switching device, specifically implemented using a multiplexed switch chip or a gating circuit composed of transmission gates. It dynamically selects the effective signal path according to the instructions output by the state machine, ensuring the orderly input of multi-channel signals and avoiding signal interference problems caused by parallel input of multiple signals. The set period refers to the time interval parameter for channel switching, which can be implemented using a programmable counter or register configuration. It allows adjustment of the channel switching frequency according to sampling rate requirements, solving the problem that a fixed switching period cannot adapt to different application scenarios.

[0109] Specifically, after receiving the start signal, the periodic signal state machine 21 begins generating channel selection instructions in binary code based on its internal clock signal. For example, a 3-bit code can support the cyclic switching of 8 channels. After each clock cycle, the state machine automatically increments the channel code value, resetting to the initial value when the maximum channel number is reached, forming a periodic cycle. After receiving the channel code instruction, the voltage input selector 22 converts the binary code into the corresponding gating signal through its internal decoding circuit, controlling the analog switch array to conduct the signal path of the target channel while simultaneously closing the transmission paths of other channels. The selected electrical data signal is impedance matched and shaped by a buffer before being output to the ADC3 module for analog-to-digital conversion. For example, in a four-channel system, the state machine sequentially generates a preset format code sequence, with the voltage input selector 22 correspondingly conducting the first to fourth channels. The sampling time for each channel can be configured, for example, 250 microseconds, to achieve cyclic sampling of different channels at equal intervals.

[0110] This solution integrates a periodic signal state machine 21 to achieve autonomous control and cyclic sampling of channel switching, reducing the number of external control interfaces. Furthermore, conventional multiplexers rely on an external clock for channel switching intervals, which can lead to clock jitter affecting sampling synchronization. This solution decouples the clock signal from the switching logic by setting a periodic parameter, improving the stability of timing control. Experimental data shows that at the same sampling rate, this structure reduces inter-channel crosstalk by approximately 40dB, effectively improving the signal-to-noise ratio of the multi-channel sampling system.

[0111] Through the above technical solution, this invention achieves high-precision, orderly acquisition of multi-channel signals. Channel switching requires no external controller intervention, reducing overall system power consumption. Configurable period parameters allow the sampling rate to flexibly adapt to different sensor characteristics. For example, in gas flow monitoring scenarios, a shorter sampling period can be set for rapidly changing pressure signals, while a longer sampling period can be set for slowly changing temperature signals. The automatic loop mechanism ensures equal probability acquisition of data from each channel, providing uniformly distributed sample data for subsequent digital signal processing. This is particularly beneficial when calculating average and RMS values, avoiding statistical errors caused by uneven sampling intervals.

[0112] In some embodiments, the present invention further proposes a structure for a voltage input selector 22. Figure 5 This is a schematic diagram of the circuit structure of the voltage input selector of the present invention, as shown below. Figure 5 As shown, the voltage input selector 22 may include a decoder 221, a selection component 222, and a buffer. The input of the decoder 221 is connected to the periodic signal state machine 21, the output of the decoder 221 is connected to the input of the selection component 222, the output of the selection component 222 is connected to the input of the buffer, and the output of the buffer is connected to the ADC3.

[0113] Among them, decoder 221 refers to the logic module that converts the channel selection instruction output by the periodic signal state machine 21 into multiple control signals. Specifically, it can be implemented by a binary decoder or a priority encoder. Its function is to convert the abstract instruction output by the state machine into a physical level signal that can drive the selection component 222.

[0114] Among them, the selection component 222 refers to the electronic switch array that selects a specific channel from multiple inputs according to the control signal output by the decoder 221. Specifically, it can be implemented by a multiplexer or an analog switch matrix, and its function is to realize the time-division switching of multiple analog signals.

[0115] The buffer refers to the amplifier circuit that performs impedance matching and signal conditioning on the signal output by the selection component 222. Specifically, it can be implemented using a voltage follower composed of amplifiers. Its function is to eliminate attenuation during signal transmission and improve driving capability.

[0116] Specifically, the periodic signal state machine 21 generates a binary-coded channel selection instruction according to a preset cycle, represented by ADC_vin_sel<2:0>. This indicates that 3-bit encoding can support cyclic switching of 8 channels. Encoding 001 corresponds to VDD selection, encoding 010 corresponds to VAT1 selection, encoding 011 corresponds to viat1 selection, encoding 100 corresponds to VAT2 selection, encoding 101 corresponds to viat2 selection, and the remaining encodings are left unused or configured as other signals. Encoding 000 corresponds to GND, and other encodings are not shown in the diagram. After receiving this encoding instruction, the decoder 221 converts it into a multiplexed control signal dec<7:0>, for example, converting binary encoding 010 into the third strobe signal dec. <3> Other binary codes are converted into corresponding strobe signals, see details. Figure 4 Examples will not be listed here. Selector component 222, driven by a control signal, activates the physical switch of the target channel, allowing the voltage signal of the target channel to be transmitted to the input of the buffer. The buffer performs voltage following processing on the signal, eliminating signal distortion caused by long-distance transmission or load changes, and finally outputs the stabilized signal to ADC3 for analog-to-digital conversion. The channel switching cycle can be configured through the clock frequency of the state machine; for example, switching the sampling channel every 100 microseconds at a 10kHz clock frequency.

[0117] This solution achieves flexible configuration of channel switching sequence and rate through the collaborative work of digital state machine and programmable selection component 222. At the same time, it uses buffer to solve the impedance mismatch problem in multi-channel signal transmission, so that signal integrity can still be maintained in high-speed switching scenarios.

[0118] Through the above technical solution, the present invention achieves efficient time-division acquisition of multi-channel signals, solves the problem of limited sampling rate caused by mechanical delay in traditional solutions, and supports dynamic channel configuration requirements under different application scenarios through a programmable switching mechanism, providing stable and timing-accurate multi-channel signal input for subsequent digital processing sub-circuits, thereby laying a data foundation for multi-mode output control.

[0119] In some embodiments, such as Figure 1 As shown, the digital processing sub-circuit of the present invention may include a multiplier 41, an accumulator 42, and a comparator 43. The multiplier 41 is connected to the analog-to-digital converter and configured to perform multiplication on the digital signal to obtain a product value. The accumulator 42 is connected to the multiplier 41 and configured to accumulate the product value to obtain an accumulated value. The comparator 43 is connected to the accumulator 42 and configured to compare the accumulated value with a set target value. Based on the comparison result, the signal state corresponding to the pulse width modulation signal to be output is determined according to a preset state flipping strategy, and the pulse width modulation signal is output in the output mode.

[0120] Among them, multiplier 41 refers to the hardware unit that performs numerical multiplication operations, specifically implemented using a fixed-point multiplication unit in a digital signal processor, used to perform squaring, multiplication, or linear operations on voltage or current signals according to the output mode. Accumulator 42 refers to the register circuit that implements numerical accumulation, specifically implemented using an adder structure with a feedback loop, used to accumulate the multiplication results to generate accumulated voltage, square, or power values. Comparator 43 refers to the logic module that performs threshold judgment, specifically implemented using a voltage comparator 43 with hysteresis characteristics, used to compare the real-time calculation result with a preset target value and generate a control signal. The state-flipping strategy refers to the logical rule that dynamically adjusts the output state according to the comparison result, specifically implemented using a finite state machine, used to switch the duty cycle of the pulse width modulation signal when the accumulated value exceeds or falls below the target value.

[0121] Specifically, in the average value mode, the coefficient of multiplier 41 is set to 1. Multiplier 41 multiplies the voltage value corresponding to the digital signal with the coefficient of multiplier 41 to obtain the voltage value. Accumulator 42 performs an addition operation on the voltage value to obtain the accumulated voltage value.

[0122] In RMS mode, multiplier 41 squares the voltage value corresponding to the digital signal to obtain the square value; accumulator 42 adds the square value to obtain the accumulated square value.

[0123] In constant power mode, multiplier 41 multiplies the voltage value and the current value corresponding to the digital signal to obtain the instantaneous power value; accumulator 42 adds the instantaneous power value to obtain the power accumulation value.

[0124] Specifically, in average value mode, the coefficient of multiplier 41 is configured to 1. In this mode, the multiplication operation is equivalent to directly transmitting the voltage signal. Accumulator 42 accumulates the continuously sampled voltage values ​​to obtain an accumulated voltage value, which can be used for subsequent comparisons to generate a PWM wave. In RMS mode, multiplier 41 is configured to perform a squaring operation, converting the voltage signal into a square value. Accumulator 42 accumulates the squared values, thus providing the basic data for calculating the root mean square (RMS) value. In constant power mode, multiplier 41 is configured to perform multiplication on the voltage and current signals to generate an instantaneous power value. Accumulator 42 accumulates the instantaneous power value to obtain a total power accumulated value, which is then used by comparator 43 to achieve constant power control. The configuration of different modes can be switched via external control signals, such as by setting register parameters through MCU 46 to select the operation mode.

[0125] Comparator 43 compares the calculated value with the target configuration value in real time. When the accumulated value exceeds the target value, it triggers a high-level output of the pulse width modulation signal. When the accumulated value is lower than the target value, it switches to a low-level output, thus forming a closed-loop control circuit.

[0126] This solution achieves flexible switching of multi-mode data processing algorithms through the combination of digital multipliers 41 and accumulators 42. At the same time, it adopts a state flip strategy to replace the fixed threshold comparison mechanism, so that the duty cycle of the output signal can be dynamically adjusted according to the real-time error, which significantly improves the control accuracy and mode adaptability.

[0127] Through the above technical solution, the present invention solves the problem of the single output mode and insufficient accuracy of traditional pneumatic sensors, and realizes multi-mode precise control of average value, effective value and power value. The configurable operation mode of the digital processing module enables the same hardware circuit to meet the needs of different application scenarios. The dynamic adjustment mechanism of the state flip strategy effectively reduces the steady-state error of the output signal and improves the control response speed and stability of the gas state monitoring system.

[0128] In some embodiments, such as Figure 1 As shown, in the circuit for implementing multi-mode output of this ADC, the digital processing sub-circuit includes an overflow clearer 44, a period configurator 45, and an MCU 46. The overflow clearer 44 is connected to the accumulator 42 and is configured to trigger an accumulation reset action when the actual accumulation period reaches the preset target accumulation period during the accumulation of the product value of each channel. The period configurator 45 is connected to the overflow clearer 44 and is configured to set the target accumulation period. The MCU 46 is connected to the comparator 43 and is configured to set the target value.

[0129] The overflow clearer 44 is a functional module used to detect whether the accumulation period has reached a preset threshold during the accumulation process. It can be implemented using a combination of a counter and logic gates. When the accumulation period count equals the preset period value, a clear signal is generated and transmitted to the accumulator 42, causing its internal accumulated value to return to zero. The purpose of this module is to prevent data overflow caused by continuous accumulation in the accumulator 42, ensuring the accuracy of the calculation results.

[0130] The period configurator 45 is a programmable module used to set the target accumulation period. It can be implemented using registers or non-volatile memory, and the duration of the accumulation operation is defined by writing different values. This module allows users to flexibly adjust the data acquisition window length according to actual needs, adapting to the varying requirements of different output modes on the data processing period.

[0131] MCU46 refers to a microcontroller unit, which can be implemented using an embedded processor or a programmable logic device. The target reference value for comparator 43 is set via software configuration or a hardware interface. The function of this module is to provide dynamic parameter adjustment capabilities, enabling the target configuration value to match the control requirements of different operating modes in real time.

[0132] Specifically, during digital signal processing, the overflow clearer 44 continuously monitors the operation cycle of the accumulator 42. When it detects that the number of accumulations has reached the target value set by the cycle configurator 45, it immediately sends a reset command to the accumulator 42, forcing it to clear the current accumulated value and restart the accumulation. The cycle configurator 45 saves the user-set cycle parameters through a storage unit. For example, in average value mode, it can be set to trigger clearing after 100 consecutive accumulations, while in RMS mode, it can be set to trigger clearing after 50 accumulations. The MCU 46 writes the corresponding target voltage, RMS value, or power threshold to the comparator 43 according to the output mode selected by the user. Through the coordinated operation of the overflow clearer 44 and the cycle configurator 45, the operation error caused by the overflow of the accumulator 42 can be effectively avoided. At the same time, the dynamic configuration function of the MCU 46 ensures the matching accuracy of the target value in different modes.

[0133] In a specific implementation, the overflow clearer 44 can integrate a period counter and a comparator circuit. When the number of accumulated counts recorded by the counter is equal to the set value output by the period configurator 45, the comparator circuit outputs a high-level signal to trigger the accumulator 42 to reset. The period configurator 45 can contain multiple register groups to store the period parameters corresponding to different output modes, and switch the register outputs through a multiplexer. The MCU 46 can receive external instructions through the I2C or SPI interface to dynamically update the value in the target value register.

[0134] This solution introduces a programmable cycle configurator 45 and a dynamic parameter configuration mechanism from the MCU 46, enabling adaptive adjustment of the accumulation period and target value. This solves the problems of low mode switching efficiency and error accumulation caused by fixed parameters in existing technologies. Furthermore, the addition of the overflow clearer 44 effectively eliminates the risk of data overflow in long-cycle accumulation operations, improving system stability.

[0135] Through the above technical solution, this invention can achieve precise accumulation period control and dynamic target value matching in multi-mode output scenarios, avoiding output deviations caused by data overflow or parameter mismatch. In constant power mode, this solution can ensure that the accumulation process of instantaneous power value is strictly controlled, preventing abnormal PWM wave output caused by calculation overflow; in effective value mode, by flexibly adjusting the accumulation period length, the calculation accuracy of the root mean square value can be optimized, thereby improving the overall control performance of the gas state monitoring system.

[0136] In some embodiments, the present invention further proposes that the ADC3 adopts a 12-bit redundant SADC3 structure; Figure 6 This is a schematic diagram of the circuit structure of the ADC used in this invention, as shown below. Figure 6 As shown, this ADC mainly includes the following devices / modules:

[0137] Redundant digital-to-analog converter 31: Receives reference voltage VREF, ADC3 input ADC_vin, and control signal dac<15:0> from successive approximation logic module 32, and generates analog voltage vdac and common-mode voltage vcm for comparison. It is the core of "voltage generation" in the successive approximation process.

[0138] Successive approximation logic module 32: The control core of the successive approximation ADC3, receives the clock ADC_clk, the enable signal ADC_en, and the sampling control signal ADC_sample, outputs dac<15:0> to control the Rud DAC, processes the result of comparator 43 and outputs ADC_rud_out<15:0> (intermediate approximation result), and outputs sample, so that the redundant digital-to-analog converter 31 and ADC3 comparator 43 can be clock synchronized.

[0139] ADC3 comparator 43: compares the output Vdac of Rud DAC with the common-mode voltage Vcm in real time, and outputs the comparison result yn under the drive of ADC_clk clock, providing a basis for the successive approximation decision of successive approximation logic module 32;

[0140] Redundancy Algorithm Module 34: Performs redundancy algorithm processing on the redundant output ADC_rud_out<15:0> to finally generate an effective and high-precision 12-bit digital output ADC_out<11:0>, and outputs an auxiliary signal ADC_eco (which can be used for error correction, control, etc.).

[0141] This ADC3 uses a 12-bit redundant SADC3 structure, and its workflow is as follows:

[0142] Initialization and enabling: When ADC_en (enable signal) and ADC_sample (sampling control signal) are set to high level, the successive approximation logic module 32 starts to work.

[0143] Successive approximation process:

[0144] The successive approximation logic module 32 first outputs the initial dac<15:0> control signal to drive the redundant digital-to-analog converter 31 to generate the initial analog voltage vdac;

[0145] ADC3 comparator 43 compares the initial analog voltage vdac with the common-mode voltage vcm and outputs the comparison result yn;

[0146] The successive approximation logic module 32 adjusts dac<15:0> according to the output result yn, and drives the redundant digital-to-analog converter 31 again to generate a new analog voltage vdac. The successive approximation process of "generating voltage → comparing → adjusting" is repeated until the approximation accuracy meets the requirements. At this time, the successive approximation logic module 32 outputs the intermediate result ADC_rud_out<15:0>.

[0147] Redundancy algorithm processing: ADC_rud_out<15:0> is sent to the redundancy algorithm module 34. After processing by the redundancy algorithm (used to improve accuracy and reduce error), the final output is a 12-bit digital quantity ADC_out<11:0>, completing the conversion from "analog voltage to digital signal".

[0148] VREF provides an analog reference voltage (configurable to 1.8V) for ADC3, which serves as the reference for the voltage generated by the Rud DAC; ADC_clk provides clock synchronization for the entire ADC3 circuit, ensuring consistent timing across all modules.

[0149] Through the above solution, the present invention effectively improves the accuracy and stability of the ADC3 conversion process, reduces the impact of process, voltage and temperature changes on digital signals, ensures the accuracy of calculation results in average value mode, RMS mode and constant power mode, and enables the output PWM wave to accurately match the target configuration value, thus meeting the requirements of multi-mode output for high-precision digital signals.

[0150] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit for implementing multi-mode output of an ADC, characterized in that, include The sampling sub-circuit is configured to acquire electrical data signals from multiple ports; wherein the electrical data signals include voltage signals and / or current signals. The time-division multiplexing loop sub-circuit is electrically connected to the sampling sub-circuit and is configured to sequentially and cyclically acquire input signals from the electrical data. The ADC, electrically connected to the time-division multiplexing loop sub-circuit, is configured to convert the input signal into a digital signal; A digital processing sub-circuit, electrically connected to the ADC, is configured to process the digital signal according to a set output mode, obtain a calculated value, compare the calculated value with a target configured value, and output a PWM wave corresponding to the output mode; wherein, the output mode includes an average value mode, an RMS value mode, or a constant power mode; The number of ports is two; the sampling sub-circuit includes a current sampling to voltage conversion component; the current sampling to voltage conversion component includes a first current sampling transistor, a first power transistor, a first selector, a second current sampling transistor, a second power transistor, a second selector, a mirror transistor, an operational amplifier, a first transmission gate, a second transmission gate, a first push-pull drive component, a second push-pull drive component, and a first resistor; The first input terminal of the first selector is connected to the output terminal of the first push-pull drive assembly; the second input terminal of the first selector is connected to the power supply; the control terminal of the first selector is used to receive the first control signal; and the output terminal of the first selector is connected to the gate of the first current sampling tube. The source of the first current sampling transistor is connected to the power supply, and the drain of the first current sampling transistor is connected to the negative terminal of the operational amplifier and the source of the image transistor. The gate of the first power transistor is connected to the output terminal of the first push-pull drive assembly, the source of the first power transistor is connected to the power supply, and the drain of the first power transistor serves as the first port and is connected to the input terminal of the first transmission gate. The first input terminal of the second selector is connected to the output terminal of the second push-pull drive assembly; the second input terminal of the second selector is connected to the power supply; the control terminal of the second selector is used to receive the second control signal; and the output terminal of the second selector is connected to the gate of the second current sampling tube. The source of the second current sampling transistor is connected to the power supply, and the drain of the second current sampling transistor is connected to the negative terminal of the operational amplifier and the drain of the image transistor. The gate of the second power transistor is connected to the output terminal of the second push-pull drive assembly, the source of the second power transistor is connected to the power supply, and the drain of the second power transistor serves as a second port and is connected to the input terminal of the second transmission gate. The gate of the image transistor is connected to the output terminal of the operational amplifier, and the drain of the image transistor is connected to the first terminal of the first resistor; the second terminal of the first resistor is grounded. The output terminal of the first transmission gate is connected to the positive terminal of the operational amplifier, and the control terminal of the first transmission gate is used to receive the inverted signal of the first control signal. The output terminal of the second transmission gate is connected to the positive terminal of the operational amplifier, and the control terminal of the second transmission gate is used to receive the inverted signal of the second control signal.

2. The circuit for implementing multi-mode output of the ADC according to claim 1, characterized in that, The ratio of the width-to-length ratio of the first current sampling transistor to the width-to-length ratio of the first power transistor is 1:K; the ratio of the width-to-length ratio of the second current sampling transistor to the width-to-length ratio of the second power transistor is 1:K. When the first control signal is a first-level signal and the second control signal is a second-level signal, the first selector outputs the output voltage of the first push-pull drive component, turning on the first current sampling transistor and making it the same as the gate-source voltage of the first power transistor. The second selector outputs the power supply voltage, turning off the second current sampling transistor. Simultaneously, the first transmission gate opens and the second transmission gate closes. The positive terminal of the operational amplifier is connected to the output voltage of the first power transistor, and the negative terminal of the operational amplifier is connected to the output voltage of the first current sampling transistor. The output current of the first power transistor is the ratio of the first voltage at the first terminal of the first resistor to the first resistor, multiplied by K. When the first control signal is a second-level signal and the second control signal is a first-level signal, the second selector outputs the output voltage of the second push-pull drive component, turning on the second current sampling transistor and making it the same as the gate-source voltage of the second power transistor. The first selector outputs the power supply voltage, turning off the first current sampling transistor. The first transmission gate is closed, the second transmission gate is open, the positive terminal of the operational amplifier is connected to the output voltage of the second power transistor, and the negative terminal of the operational amplifier is connected to the output voltage of the second current sampling transistor. The output current of the second power transistor is the ratio of the second voltage at the first terminal of the first resistor to the first resistor, multiplied by K.

3. The circuit for implementing multi-mode output of the ADC according to claim 1, characterized in that, The first transmission gate and / or the second transmission gate include an anti-backflow circuit, which includes a first PMOS transistor, a second PMOS transistor, an NMOS transistor, and a current-limiting resistor; The source of the first PMOS transistor is connected to the first terminal of the current-limiting resistor, and the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the NMOS transistor. The source of the second PMOS transistor is connected to the positive terminal of the operational amplifier; The source of the NMOS transistor is grounded; The gates of the first PMOS transistor, the second PMOS transistor, and the NMOS transistor are used to receive control signals; wherein the control signals include either the inverted signal of the first control signal or the inverted signal of the second control signal. When the control signal is a first level signal, the first PMOS transistor and the second PMOS transistor are turned off, the NMOS transistor is turned on, the NMOS transistor pulls down the drain voltage of the second PMOS transistor to 0, and the current limiting resistor limits the current at the output terminal of the anti-backflow circuit. When the control signal is a second level signal, the first PMOS transistor and the second PMOS transistor are turned on, and the NMOS transistor is turned off, so that the output voltage of the first power transistor or the output voltage of the second power transistor is connected to the positive terminal of the operational amplifier. During the current sampling process, both the first power transistor and the second power transistor remain in the on state.

4. The circuit for implementing multi-mode output of the ADC according to claim 1, characterized in that, The sampling sub-circuit includes a voltage sampling component; The voltage sampling assembly includes a first voltage sampling tube, a second voltage sampling tube, a second resistor, and a third resistor; The source of the first voltage sampling transistor is connected to the drain of the first power transistor, and the drain of the first voltage sampling transistor is connected to the first terminal of the second resistor. The gate of the first voltage sampling transistor is used to receive the inverted signal of the corresponding control signal of the first voltage sampling transistor; The source of the second voltage sampling transistor is connected to the drain of the second power transistor, and the drain of the second voltage sampling transistor is connected to the first terminal of the second resistor; The gate of the second voltage sampling transistor is used to receive the inverted signal of the corresponding control signal of the second voltage sampling transistor; The second terminal of the second resistor is connected to the first terminal of the third resistor; The second terminal of the third resistor is grounded; When the inverted signal of the corresponding control signal of the first voltage sampling tube is a first level signal and the inverted signal of the corresponding control signal of the second voltage sampling tube is a second level signal, the first voltage sampling tube is turned on and the second voltage sampling tube is turned off. When the inverted signal of the corresponding control signal of the first voltage sampling tube is a second level signal and the inverted signal of the corresponding control signal of the second voltage sampling tube is a first level signal, the first voltage sampling tube is turned off and the second voltage sampling tube is turned on.

5. The circuit for implementing multi-mode output of the ADC according to claim 1, characterized in that, The time-division multiplexing loop sub-circuit includes a periodic signal state machine and a voltage input selector; The periodic signal state machine is electrically connected to the voltage input selector; The periodic signal state machine is configured to: generate a channel selection instruction based on each acquisition channel of the electrical data signal, and switch the channel selection instruction according to a set period; The voltage input selector is configured to select the signal corresponding to the current channel selection command from the electrical data signals as the input signal.

6. The circuit for implementing multi-mode output of the ADC according to claim 5, characterized in that, The voltage input selector includes a decoder, a selection component, and a buffer; The input of the decoder is connected to the periodic signal state machine; The output of the decoder is connected to the input of the selection component; The output of the selection component is connected to the input of the buffer; The output of the buffer is connected to the ADC.

7. The circuit for implementing multi-mode output of the ADC according to any one of claims 1-6, characterized in that, The digital processing sub-circuit includes a multiplier, an accumulator, and a comparator; The multiplier, connected to the ADC, is configured to perform a multiplication operation on the digital signal to obtain the product value corresponding to the digital signal. The accumulator, connected to the multiplier, is configured to accumulate the product values ​​to obtain an accumulated value; The comparator, connected to the accumulator, is configured to compare the accumulated value with a set target value, determine the signal state corresponding to the PWM signal to be output according to the comparison result and a preset state flipping strategy, and output the PWM signal in the output mode.

8. The circuit for implementing multi-mode output of the ADC according to claim 7, characterized in that, The digital processing sub-circuit also includes an overflow clearer, a cycle configurator, and an MCU; The overflow clearer, connected to the accumulator, is configured to trigger an accumulation reset action when the actual accumulation period reaches the preset target accumulation period during the accumulation of the product value of each path. The period configurator, connected to the overflow clearer, is configured to set the target accumulation period; The MCU, connected to the comparator, is configured to set the target value.

9. The circuit for implementing multi-mode output of the ADC according to claim 7, characterized in that, In the average value mode, the coefficient of the multiplier is set to 1. The multiplier multiplies the voltage value corresponding to the digital signal by the coefficient of the multiplier to obtain the voltage value. The accumulator then performs an addition operation on the voltage value to obtain the accumulated voltage value. In the effective value mode, the multiplier squares the voltage value corresponding to the digital signal to obtain a squared value; the accumulator adds the squared value to obtain a cumulative squared value. In the constant power mode, the multiplier performs a multiplication operation on the voltage value and the current value corresponding to the digital signal to obtain the instantaneous power value; the accumulator performs an addition operation on the instantaneous power value to obtain the power accumulation value.

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