Coarse frequency offset estimation method and apparatus

Abstract

This application provides a coarse frequency offset estimation method and apparatus, relating to the fields of wireless communication and coherent optical communication technologies. The method includes: performing a Fourier transform on a time-domain signal to obtain a frequency-domain signal; calculating the power spectrum and performing multiple averaging processes to obtain an average power spectrum; and determining the frequency offset value by iteratively adjusting the frequency shift based on the average power spectrum. The core of this method lies in the fact that the cyclic shift during the iteration process is a logical cyclic shift, implemented by updating the read start address of the memory storing the average power spectrum, thus avoiding physical write-back of the data. Finally, phase compensation is performed on the time-domain signal based on the determined frequency offset value. The apparatus includes corresponding modules for implementing the above method. This application significantly saves hardware resources, reduces power consumption, and improves timing performance by replacing physical shift with logical shift, making the blind frequency offset estimation algorithm easier to implement in hardware, while improving estimation accuracy through power spectrum averaging.

Description

Technical Field

[0001] This invention relates to the fields of wireless communication and coherent optical communication technology, and more specifically, to a coarse frequency offset estimation method and apparatus. Background Technology

[0002] In wireless or coherent optical communication systems, frequency differences exist between the local oscillators of the transmitter and receiver, and the Doppler effect may occur during signal transmission in the channel. This causes a shift in the carrier frequency of the received signal compared to the original transmission frequency, known as frequency offset. If this frequency offset is not effectively corrected, it will cause the demodulated signal constellation points to rotate continuously, and in severe cases, it may even prevent the correct data interpretation, leading to communication interruption.

[0003] To address this issue, a blind frequency offset estimation algorithm without pilots or training sequences has been proposed in the prior art. The basic idea of ​​this algorithm is to utilize the symmetry of the modulated signal's power spectrum. Specifically, the algorithm first performs a Fast Fourier Transform on the received digital signal, converting it from the time domain to the frequency domain, and then calculates its power spectrum. In an ideal, frequency-off condition, the signal's power spectrum should be symmetrical about zero frequency. When a frequency offset exists, the entire power spectrum undergoes a corresponding shift, thus disrupting its symmetry about zero frequency. Therefore, this algorithm sets symmetrical detection windows on both sides of the power spectrum peak, compares the total energy within the two windows, and iteratively shifts the entire power spectrum data cyclically based on the energy difference until the energy in both windows reaches equilibrium. At this point, the total shift accumulated during the entire iteration process is considered the estimated value of the frequency offset. However, this algorithm faces significant challenges in hardware implementation. The cyclic shifting operation during the iteration process requires large-scale data readouts, shifts, and write-backs to the memory storing the entire power spectrum data (typically containing thousands of data points). This physical shifting operation of memory contents not only consumes a great deal of hardware logic resources and power, but also, due to its long operation time, it can easily cause timing convergence difficulties in high-speed systems, which greatly reduces the practicality of the algorithm in chip design. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of this invention is to provide a coarse frequency offset estimation method and apparatus.

[0005] A coarse frequency offset estimation method provided by the present invention includes: Perform a Fourier transform on the received time-domain digital signal to obtain the frequency-domain signal; Calculate the power spectrum of the frequency domain signal; The power spectra from multiple sets of time-domain signals are averaged to obtain an average power spectrum; Based on the average power spectrum, a frequency offset value is determined by iteratively adjusting a frequency shift amount, wherein the iterative adjustment of the frequency shift amount includes performing a logical cyclic shift operation on the average power spectrum, wherein the logical cyclic shift operation is implemented by updating a read start address for accessing a memory storing the average power spectrum; Phase compensation is performed on the time-domain digital signal based on the determined frequency offset value.

[0006] Preferably, the iterative adjustment of the frequency shift further includes: A first detection window and a second detection window are set on the average power spectrum; Calculate the power accumulation value within the first detection window and the second detection window respectively; And based on the difference between the two power accumulation values, determine whether it is necessary to continue adjusting the frequency shift.

[0007] Preferably, when reading data from the memory according to the updated read start address, if the required data block crosses the physical memory word boundary in the memory, the method further includes: Perform a data concatenation operation on data portions read from different physical storage words to form logically contiguous data blocks.

[0008] Preferably, the step of calculating the power accumulation value within the two detection windows includes: By utilizing the address wraparound feature of the memory, a continuous read operation is performed on the data in the first and second detection windows, which are logically located at both ends of the average power spectrum.

[0009] Preferably, the widths of the first detection window and the second detection window are adaptively determined based on the bandwidth of the average power spectrum.

[0010] A coarse frequency offset estimation device according to the present invention includes: The Fourier transform module is used to perform Fourier transform on the received time-domain digital signal to obtain the frequency-domain signal; A power spectrum calculation module is used to calculate the power spectrum of the frequency domain signal; A power spectrum averaging module is used to average the power spectra from multiple sets of time-domain signals to obtain an average power spectrum. The frequency offset determination module is used to determine the frequency offset value by iteratively adjusting a frequency shift based on the average power spectrum. The frequency offset compensation module is used to perform phase compensation on the time-domain digital signal according to the determined frequency offset value; The frequency offset determination module includes: A memory used to store the average power spectrum; The control logic is configured to perform a logical cyclic shift on the average power spectrum by updating the read start address of the memory to iteratively determine the frequency offset value.

[0011] Preferably, the frequency offset determination module is further configured to set a first detection window and a second detection window on the average power spectrum, and calculate the power accumulation value in the first detection window and the second detection window respectively; Furthermore, the control logic is configured to determine whether the frequency shift needs to be adjusted further based on the difference between the two power accumulation values.

[0012] Preferably, the control logic is further configured to: utilize the address wraparound characteristic of the memory to generate a continuous read address sequence, so as to extract data from the first detection window and the second detection window that are logically located at both ends of the average power spectrum at one time.

[0013] Preferably, the control logic is further configured to: when reading data according to the updated read start address, if the required data block crosses the physical storage word boundary in the memory, perform a data splicing operation to reconstruct logically continuous data blocks.

[0014] Preferably, the memory is a ring buffer and is organized into a structure with a depth of 64 and a bit width of 16 power spectrum data points.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention employs an innovative logic shifting scheme, namely, by updating the memory read start address and supplementing it with data concatenation operations, to achieve equivalent cyclic shifting of power spectrum data. This completely avoids the physical data shifting and write-back operations that incur huge resource and power consumption costs in traditional implementations, greatly saving chip area, reducing power consumption, and significantly improving timing performance. This makes the frequency offset estimation algorithm based on power spectrum symmetry efficient, low-cost, and easy to implement in hardware.

[0016] 2. This invention improves estimation accuracy. By accumulating and averaging the power spectra from multiple consecutive sets of time-domain signals, noise interference is effectively suppressed, resulting in a smoother and more reliable power spectrum shape, thereby improving the accuracy of frequency offset estimation in low signal-to-noise ratio environments.

[0017] 3. This invention achieves blind estimation, without the need for any pilots or training sequences, and can directly process the initial received signal, thus having wide applicability and robustness. Attached Figure Description

[0018] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating a coarse frequency offset estimation method based on logical shifting provided in an embodiment of this application; Figure 2 A schematic diagram of a coarse frequency offset estimation device provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the principle of the 16-point radix-4 fast Fourier transform in the embodiments of this application; Figure 4 This is a schematic diagram illustrating the principle of radix-4 butterfly operation in the embodiments of this application; Figure 5 This is a schematic diagram of the power spectrum averaging calculation process in an embodiment of this application; Figure 6 This is a schematic diagram of the power spectrum shape and edge detection window in an embodiment of this application; Figure 7 This is a flowchart illustrating the peak detection algorithm in an embodiment of this application; Figure 8 This is a schematic diagram of an efficient RAM read strategy in an embodiment of this application; Figure 9 This is a schematic diagram of data offset and splicing in the embodiments of this application.

[0019] Explanation of reference numerals in the attached figures: Detailed Implementation

[0020] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0021] Example 1 This invention discloses a coarse frequency offset estimation method and apparatus. It is understood that this solution aims to solve the problems of high hardware resource consumption, high power consumption and complex implementation caused by repeated physical shifting of power spectrum data in the frequency offset estimation process based on power spectrum symmetry in the prior art.

[0022] This invention first performs a 1024-point Fast Fourier Transform (FFT) on the received training sequence, converting it from the time domain to the frequency domain. Next, the complex data output by the FFT is squared to obtain the signal's power spectrum. Multiple rounds of FFT power spectrum superposition and averaging are then performed. This method amplifies and highlights the frequency components with concentrated energy, making the frequency offset more obvious and facilitating edge detection. Finally, edge detection is performed on the power spectrum to align the waveform edges, obtaining the frequency data.

[0023] The coarse frequency offset estimation method disclosed in this invention is as follows: Step S1: Buffer the upstream receiving module and perform address mapping (Note: Base-4 address mapping is done by flipping in 2-bit units. For example, if the current write address is 4'b0001, it is flipped in 2-bit units to get 4'b0100; and so on, it is written sequentially to the following address control X(0), X(4), X(8)..., X(11), X(15)), and written to the mapped address buffer. When a 1024-point buffer is reached, a fast Fourier transform is performed according to the FFT 1024-point base-4.

[0024] Please see Figure 3 This is a data flow graph for a 16-point FFT radix-4, and a 1024-point radix-4 FFT is based on a similar flowchart.

[0025] For a butterfly operation with a minimum radix-4, please refer to [link / reference]. Figure 4 In this embodiment of the invention, 32 radix-4 butterfly operations are performed in parallel based on 1024 points. This requires 8 clock units to complete one round of 1024-point calculation, and a total of 5 rounds of butterfly operations are needed to complete the FFT calculation. Ultimately, it takes 8 clocks * 5 = 40 clocks to achieve full-speed performance with an input parallelism of 16.

[0026] Step S2: Squaring the FFT output value obtained in step S1 yields the power spectrum. (See also...) Figure 5 To facilitate subsequent power spectrum peak detection, this embodiment of the invention caches multiple sets of FFT power spectrum data and finally sends the average value to the next module. For example, 128 sets of FFTs are performed. After each FFT output, the square value is calculated. If it is the first FFT, the square value is stored in RAM. Otherwise, the cached value in RAM is read and summed with the currently calculated FFT power spectrum value until all 128 sets of data are processed. Then, the final accumulated FFT power spectrum value is read from RAM, divided by the number of FFTs (e.g., 128), and the average power spectrum value is sent to the frequency offset detection module.

[0027] Step S3: Based on the average power spectrum obtained in the previous step, its shape should be as follows: Figure 6 As shown, detection windows are set up on both sides, and the detection frequency shift is determined by accumulating the size of the windows.

[0028] Please refer to the detection method. Figure 7 Specifically, according to: Figure 6 Obtain the accumulated values ​​of the minus window and the pluse window (this window can be resized), and compare them. Check if the absolute value of the difference exceeds the comparison threshold. If it exceeds the threshold, ... This indicates that the right-side window is too large, requiring a certain amount of data to be cyclically slid to the left, accumulating the movement to y each time, before sending it to the capture window to extract data for the next round of comparison. If This indicates that the left window is too large, and you need to scroll to the right to retrieve a certain amount of data. If If the absolute value of the difference is less than the threshold, then the current accumulated value y of the mobile data point is considered to be the carrier frequency offset (y / 1024*sampling frequency).

[0029] In chip design, to reduce area and power consumption, RAM is used to cache the 1024 power spectral points, and spectral point shifting is performed. Here's a specific explanation of the innovation: assuming the window size is set to 64 points and the parallelism of the upstream module's input data is 16, then the RAM cache depth is 64, and the bit width is 16 points, which perfectly stores the complete 1024 points. In edge detection, the common method is to detect the accumulated value of the left window (32 points). Then read the right window (32 points). The data is compared and shifted, and then re-detected based on the shifted data. In this embodiment of the invention, please refer to... Figure 8 First, check the right window (32 points). Then check the accumulated value in the left window (32 points). Utilizing the address continuity of RAM (e.g.) Figure 8 Starting at address 60, read 4 lines consecutively and then return to the starting address. Window data (address 64 overflows and returns to address 0), it can be seen that the data is continuous from the right window to the left window, which is convenient for reading and shifting.

[0030] The data read from the window above is as follows: Figure 9 This is because the data read from the starting address after the offset may not be all 16 points valid; it needs to be concatenated with the data from the next address to form a complete set of 16 points. Since the read addresses are continuous, controlling the concatenation of data becomes much easier. The calculation is based on the concatenated data. and The method performs peak detection and offset calculation, and accumulates the offset x into the total offset y until the difference between the data in the two windows is less than the configured threshold, at which point the detection is complete. This method does not require writing the offset data back to RAM; it only needs to update the starting address and the number of valid points within that address in real time.

[0031] Step S4: Perform frequency offset correction (rotation angle) based on the frequency offset y obtained in the previous step. This involves multiplying the received data by the offset / 1024 * sampling frequency. The rotated data is then sent to the next module for processing.

[0032] Example 2 As a more specific implementation method, this invention provides a coarse frequency offset estimation method, such as... Figure 1 As shown, the method first performs a Fourier transform step (S101) on the received continuous time-domain digital signal to obtain a frequency-domain signal, and then performs a power spectrum calculation step (S102) and a power spectrum accumulation and averaging step (S103) to improve the signal-to-noise ratio. The crucial edge detection step (S104) determines the frequency offset value through an iterative process based on logical cyclic shifting. Finally, based on the determined frequency offset value, a frequency offset compensation step (S105) is performed, and the corrected signal is output.

[0033] Figure 2 The schematic diagram illustrates the structure of the coarse frequency offset estimation device for implementing the above method. As an optional implementation, this device can be integrated into the front end of a wireless communication or coherent optical communication receiver. The device includes a Fast Fourier Transform module 10, a power spectrum calculation module 20, a power spectrum averaging module 30, an edge detection module 40, and a frequency offset compensation module 50 connected in sequence. Among them, the edge detection module 40 is a key part for implementing the core technology of this application, and it internally contains a ring memory 41 and corresponding control logic 42.

[0034] The following will combine Figures 1 to 9 The functions of each module in the device and their collaborative working process are described in detail.

[0035] In a specific application scenario, the analog-to-digital converter at the receiver front end converts the received analog signal into a time-domain digital signal sequence, which serves as the input of this device.

[0036] Specifically, the time-domain digital signal is fed into the Fast Fourier Transform module 10 to perform... Figure 1 The Fourier transform step (S101) is described. In this embodiment, the Fast Fourier Transform module 10 is configured to perform a 1024-point Fourier transform. To achieve high-speed processing in hardware, a radix-4 Fast Fourier Transform algorithm is preferably used. Figure 3 The diagram illustrates the data flow of a 16-point radix-4 Fast Fourier Transform, serving as a principle example for a 1024-point transform. A 1024-point radix-4 transform can be decomposed into three levels of butterfly operations. Figure 4This demonstrates the principle of the basic operational unit constituting this transformation, namely the radix-4 butterfly operation. In hardware implementation, the Fast Fourier Transform module 10 can contain 32 parallel radix-4 butterfly operation units, enabling a 1024-point transformation to be completed within, for example, 40 clock cycles, thus meeting the real-time requirements of high-speed communication systems. The module's input consists of 1024 complex time-domain samples, and its output consists of 1024 complex frequency-domain data points, representing the amplitude and phase of the signal at different frequency components.

[0037] Subsequently, the 1024 frequency domain complex data points output by the Fast Fourier Transform module 10 are sent to the power spectrum calculation module 20 to perform... Figure 1 The power spectrum calculation step (S102) is as follows: For each input frequency domain complex point X(k) = I(k) + jQ(k), where k is the frequency index, I(k) and Q(k) are the in-phase component and quadrature component, respectively, the power spectrum calculation module 20 calculates the square of its modulus, i.e., the power spectrum value P(k) = I(k)^2 + Q(k)^2. After this step, a set of 1024 frequency domain complex points is converted into a set of 1024 real values, which is the power spectrum corresponding to the time domain signal.

[0038] Subsequently, the power spectrum data is sent to the power spectrum averaging module 30 to perform... Figure 1 The cumulative averaging step (S103) is described. In wireless communication environments, signals are often subject to noise interference, and the power spectrum calculated in a single instance may have large random fluctuations, which is not conducive to accurate frequency offset estimation. To obtain a smoother power spectrum with a higher signal-to-noise ratio, this embodiment uses a method of cumulative averaging multiple consecutive power spectra. The calculation process for power spectrum averaging can be found in [reference needed]. Figure 5 The power spectrum averaging module 30 internally contains a memory for storing the accumulated sum (in... Figure 5 The system consists of an accumulator Σ and a buffer loop, along with a counter. Whenever a new set of 1024 power spectrum data points is received from the power spectrum calculation module 20, the module adds it point-by-point to the existing accumulated value in memory and updates it. Simultaneously, the counter is incremented. In this embodiment, the preset number of averaging groups is 128. When the counter reaches 128, it indicates that 128 power spectrum groups have been accumulated. At this point, the module divides each point of the 128 sums in memory by 128 (typically implemented as a 7-bit right shift in hardware) to obtain the average power spectrum. Noise in this average power spectrum is effectively suppressed, and the spectral shape characteristics of the signal (such as peaks and edge ramps) are thus more prominent. After the averaging calculation is complete, the average power spectrum is output to the edge detection module 40, and the accumulator and counter are cleared to prepare for the next round of 128 averaging groups.

[0039] Edge detection module 40 is used to perform Figure 1 The edge detection step (S104) is a key module used in this application to determine the frequency offset value. This module receives 1024-point averaged power spectrum data from the power spectrum averaging module 30. Figure 2 As shown, it mainly consists of a ring memory 41 and control logic 42.

[0040] In this embodiment, the ring memory 41 is a random access memory, specifically organized with a depth of 64 and a bit width of 16 data points, for a total capacity of exactly 64 * 16 = 1024 data points. The 1024 points of average power spectrum data are sequentially written into this memory. It is understood that this storage structure is optimized for efficient subsequent data retrieval and logical shift operations.

[0041] Control logic 42 is responsible for implementing the iterative search algorithm based on power spectrum symmetry. For detailed flowcharts, please refer to [link / reference needed]. Figure 7 The specific working process is as follows: 1. Initialization: Control logic 42 clears an internal frequency offset accumulator register y to zero, and sets a read start address pointer for accessing the ring memory 41, which initially points to a logical zero.

[0042] 2. Set the detection window: such as Figure 6 As shown, the algorithm works by symmetrically placing two detection windows on either side of the peak of the average power spectrum: a first detection window (e.g., the Minus window in the figure) and a second detection window (e.g., the Plust window in the figure), and comparing the total energy within the two windows. In this embodiment, the widths of the two windows are fixed; for example, each window contains 32 consecutive power spectrum data points, and the windows are positioned symmetrically relative to the predicted spectrum center.

[0043] 3. Efficient Data Reading: To acquire data from both windows, control logic 42 utilizes the address wraparound characteristic of the ring memory 41 to implement an efficient reading strategy, such as... Figure 8 As shown. Assume the Plus window is located at the high end of the spectrum logic, while the Minus window is located at the low end. For example, the data in the Plus window might be stored at physical addresses 60 to 61, while the data in the Minus window might be stored at physical addresses 0 to 1. Control logic 42 can initiate a continuous read operation starting from address 60. After reading address 63, the memory address counter automatically wraps back to 0. In this way, the controller can read the data in the Plus window first, and then seamlessly read the data in the Minus window within a single continuous read cycle, without initiating two separate read operations, thus greatly improving data access efficiency.

[0044] 4. Power and Calculation and Comparison: The control logic 42 accumulates the data read from the two windows respectively to obtain the first power sum Pm (from the Minus window) and the second power sum Pp (from the Pluse window). Then, it calculates the absolute value of the difference between the two, |Pp - Pm|, and compares it with a preset threshold TH.

[0045] 5. Iterative Decision and Logical Shift: If |Pp - Pm| < TH, it indicates that the power spectrum is approximately symmetric at this position, and the iterative process ends. At this time, the value stored in the frequency offset accumulation register y is the final frequency offset estimation value. If |Pp - Pm| >= TH, the power spectrum needs to be shifted to continue searching for the symmetric point. At this time, the control logic 42 determines the shift direction according to the magnitude relationship between Pp and Pm: if Pp > Pm, it means that the power spectrum energy is biased to the right, and a logical circular left shift is required; if Pm > Pp, a logical circular right shift is required. The shift step size can be a fixed value, such as 4 data points.

[0046] It should be noted that a key feature of this application lies in the implementation method of "logical circular shift". Compared with the huge overhead of physically reading the entire 1024-point data, shifting it, and then writing it back to the memory in the traditional method, the control logic 42 in this application does not perform any data write-back operations, but only updates the read start address for accessing the circular memory 41 in the next iteration. For example, if a logical left shift of 4 points is required, the control logic 42 only needs to add 4 to the internal read start address pointer and accumulate the shift amount (signed) to the frequency offset accumulation register y.

[0047] 6. Data Stitching: Since the shift step size (4) is not an integer multiple of the memory bit width (16), in the next read after updating the start address, logically continuous data blocks (such as a 16-point processing block) are very likely to span two physically adjacent memory words in the circular memory 41. At this time, the data stitching operation is necessary for correctly reconstructing the logically continuous data block. As Figure 9 shown, to construct a logically shifted "valid data block", the control logic 42 reads data from the physical row where the new start address is located (such as address N) and the next row (address N + 1) respectively. Then, its internal data stitching logic intercepts the second half (such as the last 12 points) of the data read from address N and stitches it together with the first half (such as the first 4 points) of the data read from address N + 1, thus perfectly reconstructing the logically continuous data block after circular shift. This process is completely completed on the read and processing path without modifying the memory content.

[0048] 7. Loop: After completing one logical shift, control logic 42 returns to step 3, uses the new read start address and concatenation logic to obtain the window data at the new position, and repeats the above comparison and adjustment process until the termination condition is met.

[0049] Finally, when the edge detection module 40 completes the iteration and outputs the final frequency offset estimate y, this value is sent to the frequency offset compensation module 50 to perform... Figure 1 The frequency offset compensation step (S105) is as follows. The frequency offset compensation module 50 simultaneously receives the original, unprocessed time-domain digital signal y(n). Based on the estimated value y, it performs a complex multiplication operation on each time-domain sampling point y(n) to correct its phase. The compensation formula is: z(n) = y(n) * e^(j * 2 * π * y * ts * n / N), where z(n) is the compensated time-domain signal, ts is the sampling period, N is the number of points in the Fourier transform (1024 in this example), and n is the time index of the sampling point. This formula essentially multiplies the original signal by a rotation factor with a frequency equal to the magnitude of the estimated frequency offset but opposite in direction, thereby canceling the phase rotation caused by the frequency offset. The output signal z(n) is the frequency offset corrected signal, which can be sent to the subsequent synchronization and demodulation modules for processing.

[0050] In this embodiment, the solution utilizes a logical shift mechanism for updating the read start address and concatenating data to efficiently implement a frequency offset estimation algorithm based on power spectrum symmetry, avoiding large-scale data write-back, thereby significantly saving hardware resources, reducing power consumption, and improving timing performance.

[0051] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A coarse frequency offset estimation method, characterized in that, include: Perform a Fourier transform on the received time-domain digital signal to obtain the frequency-domain signal; Calculate the power spectrum of the frequency domain signal; The power spectra from multiple sets of time-domain signals are averaged to obtain an average power spectrum; Based on the average power spectrum, a frequency offset value is determined by iteratively adjusting a frequency shift amount, wherein the iterative adjustment of the frequency shift amount includes performing a logical cyclic shift operation on the average power spectrum, wherein the logical cyclic shift operation is implemented by updating a read start address for accessing a memory storing the average power spectrum; Phase compensation is performed on the time-domain digital signal based on the determined frequency offset value.

2. The coarse frequency offset estimation method according to claim 1, characterized in that, The iterative adjustment of the frequency shift further includes: A first detection window and a second detection window are set on the average power spectrum; Calculate the power accumulation value within the first detection window and the second detection window respectively; And based on the difference between the two power accumulation values, determine whether it is necessary to continue adjusting the frequency shift.

3. The coarse frequency offset estimation method according to claim 1 or 2, characterized in that, When reading data from the memory according to the updated read start address, if the required data block crosses the physical memory word boundary, the method further includes: Perform a data concatenation operation on data portions read from different physical storage words to form logically contiguous data blocks.

4. The coarse frequency offset estimation method according to claim 2, characterized in that, The steps for calculating the power summation value within the two detection windows include: By utilizing the address wraparound feature of the memory, a continuous read operation is performed on the data in the first and second detection windows, which are logically located at both ends of the average power spectrum.

5. The coarse frequency offset estimation method according to claim 2, characterized in that, The widths of the first detection window and the second detection window are adaptively determined based on the bandwidth of the average power spectrum.

6. A coarse frequency offset estimation device, characterized in that, include: The Fourier transform module is used to perform Fourier transform on the received time-domain digital signal to obtain the frequency-domain signal; A power spectrum calculation module is used to calculate the power spectrum of the frequency domain signal; A power spectrum averaging module is used to average the power spectra from multiple sets of time-domain signals to obtain an average power spectrum. The frequency offset determination module is used to determine the frequency offset value by iteratively adjusting a frequency shift based on the average power spectrum. The frequency offset compensation module is used to perform phase compensation on the time-domain digital signal according to the determined frequency offset value; The frequency offset determination module includes: A memory used to store the average power spectrum; The control logic is configured to perform a logical cyclic shift on the average power spectrum by updating the read start address of the memory to iteratively determine the frequency offset value.

7. The coarse frequency offset estimation device according to claim 6, characterized in that, The frequency offset determination module is also used to set a first detection window and a second detection window on the average power spectrum, and to calculate the power accumulation value in the first detection window and the second detection window respectively; Furthermore, the control logic is configured to determine whether the frequency shift needs to be adjusted further based on the difference between the two power accumulation values.

8. The coarse frequency offset estimation device according to claim 7, characterized in that, The control logic is further configured to: utilize the address wraparound characteristic of the memory to generate a continuous read address sequence, so as to extract data from the first detection window and the second detection window that are logically located at both ends of the average power spectrum at one time.

9. The coarse frequency offset estimation device according to claim 6, characterized in that, The control logic is further configured to: when reading data according to the updated read start address, if the required data block crosses the physical storage word boundary in the memory, perform a data splicing operation to reconstruct logically continuous data blocks.

10. The coarse frequency offset estimation device according to claim 6, characterized in that, The memory is a ring buffer and is organized into a structure with a depth of 64 and a bit width of 16 power spectrum data points.

Images