A high-reliability MOS device structure with three buffer layers and its fabrication method

Abstract

This invention relates to power MOSFET devices, and particularly to a high-reliability MOSFET device structure and fabrication method with three buffer layers. The fabrication method includes sequentially growing an N-drift layer and a second buffer layer on an N-substrate; forming a first deep trench in the middle of a cell by etching; implanting ions at the bottom of the first deep trench to form a third buffer layer; depositing an oxide layer in the first deep trench to fill it; then forming a first buffer layer around the first deep trench by implanting ions in the second buffer layer; growing a P-type well region on the surface of the second buffer layer; etching the P-type well region to form a second deep trench; and depositing a first polysilicon layer and a second polysilicon layer in the second deep trench. This invention resolves the contradiction between performance improvement and radiation resistance reliability in current power devices. This structure balances the high performance of shielded gate devices with optimized electric field distribution, while simultaneously improving the device's resistance to single-particle and total dose radiation.

Description

Technical Field

[0001] This invention relates to power MOSFET devices, and in particular to a high-reliability MOSFET device structure and fabrication method with three buffer layers. Background Technology

[0002] Extreme radiation scenarios such as aerospace electronics and nuclear energy control place stringent demands on the reliability of power semiconductor devices. Currently, there are three major bottlenecks in the structure of radiation-hardened devices: First, material limitations: silicon-based devices have a significant radiation hardening ceiling, and SiC / GaN wide-bandgap devices face the challenge of interface defects amplifying radiation damage. Second, structural compromises: planar double epitaxial solutions sacrifice switching speed (Qsv increases by 25%), and the lightly doped drift region of traditional SGTs is susceptible to SEB breakdown, resulting in poor total dose resistance. Third, process conflicts: radiation hardening implantation leads to a decrease in drain-source breakdown voltage (BVdss).

[0003] To address the above challenges, three dimensions of doping techniques are proposed to optimize the radiation resistance reliability of MOS devices. First, the upper layer of the double epitaxial layer is lightly doped to shield against threshold voltage changes caused by total dose (TID), and the lower layer doping concentration is increased to construct a low-resistance hole discharge channel, thereby improving the resistance to single-event burn-out (SEB). Second, SGT localized doping strengthens the field plate, and buried layer injection at the bottom of the Gate Poly reduces the electric field peak. Third, the doping concentration at the bottom of the Source Poly improves the resistance to single-event burn-out. Summary of the Invention

[0004] To enhance the radiation resistance of power MOS devices, this invention proposes a method for fabricating a high-reliability MOS device structure with three buffer layers, specifically including the following steps:

[0005] Step 1: Grow an N-drift layer and a second buffer layer sequentially on the N-substrate layer, with the substrate serving as the drain.

[0006] Step 2: Form a first deep trench in the middle of the cell by etching, and inject ions at the bottom of the first deep trench to form a third buffer layer;

[0007] Step 3: Deposit an oxide layer in the first deep trench to fill the first deep trench, and then form a first buffer layer on both sides of the first deep trench in the second buffer layer by implanting ions.

[0008] Step 4: Grow a P-type well region on the surface of the second buffer layer;

[0009] Step 5: Etch the P-type well region. The etching position is consistent with the position of the first deep trench, and the etching depth is consistent with the thickness of the P-type well region. After etching, remove the oxide layer filling the first deep trench to form the second deep trench.

[0010] Step 6: Deposit an oxide layer with a thickness of 3500 angstroms on the inner surface of the second deep trench, and fill the second deep trench with a first polysilicon layer;

[0011] Step 7: Etch the polysilicon in the second deep trench to make it 0.9um~1.2um below the P-type well region, and fill the etched area with an oxide layer;

[0012] Step 8: Etch the oxide layer in the second deep trench to make it 2um~2.2um below the surface, then deposit a 3000A oxide layer on the sidewall of the second deep trench, and then fill the etched trench with polysilicon to form a second polysilicon layer, which serves as the gate.

[0013] Step 9: Ions are implanted on both sides of the second polysilicon layer to form N-type heavily doped regions. The mesa is symmetrically etched on both sides so that the etched portion occupies half of the width of the mesa. Heavy doping is implanted from the upper surface of the etched area to form P-type heavily doped regions. Finally, an oxide layer is grown on the surface of the second polysilicon layer and the N-type heavily doped regions.

[0014] Step 10: Deposit metal on the upper surface of the device to form the source.

[0015] Compared with existing shielded gate MOS structures, the structure of this invention has higher reliability and stronger single-event immunity, making it applicable to aerospace environments. Specific advantages are as follows:

[0016] 1. The present invention adds a second buffer layer. First, compared with the device containing only the N-type drift layer, the second buffer layer has a lower doping concentration and a larger depletion layer width, which greatly weakens the influence of the positive oxide layer trap charge on the threshold voltage and increases the resistance to total dose. Second, because the doping concentration of the N-type drift region is higher, the parasitic transistor gain β is reduced, the parasitic transistor cannot be effectively turned on, the avalanche positive feedback is interrupted, and the resistance to single-event burn-out is increased.

[0017] 2. The present invention adds a third buffer layer, which firstly optimizes the transient electric field generated by the ionization of high-energy particles below the gate oxide layer, optimizes the peak electric field of the device, and reduces the risk of electro-ion gate breakdown.

[0018] 3. The present invention adds a first buffer layer, which can shield gate oxide interference, reduce electric field peak, and reduce the risk of single-event gate breakdown; secondly, shield the trap charge consistent parasitic leakage current to suppress the total dose effect; and thirdly, reduce the gain of parasitic transistors and alleviate the single-event burn-out effect. Attached Figure Description

[0019] Figure 1 This is the structure formed in step 1 of the fabrication method of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0020] Figure 2This is the structure formed in step 2 of the fabrication method of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0021] Figure 3 This is the structure formed in step 3 of the fabrication method of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0022] Figure 4 This is the structure formed in step 4 of the fabrication method of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0023] Figure 5 This is the structure formed in step 5 of the fabrication method of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0024] Figure 6 This is the structure formed in step 6 of the method for fabricating a high-reliability MOS device structure with three buffer layers according to the present invention;

[0025] Figure 7 This is the structure formed in step 7 of the method for fabricating a high-reliability MOS device structure with three buffer layers according to the present invention;

[0026] Figure 8 This is the structure formed in step 8 of the method for fabricating a high-reliability MOS device structure with three buffer layers according to the present invention;

[0027] Figure 9 This is the structure formed in step 9 of the method for fabricating a high-reliability MOS device structure with three buffer layers according to the present invention;

[0028] Figure 10 This is the structure formed in step 10 of the fabrication method of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0029] Figure 11 This is Embodiment 1 of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0030] Figure 12 This is Embodiment 2 of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0031] Figure 13 This is embodiment 3 of a high-reliability MOS device structure with three buffer layers according to the present invention;

[0032] In the attached figures, 1: substrate layer; 2: N-type drift layer; 3: second buffer layer; 4: third buffer layer; 5: first deep trench; 6: first buffer layer; 7: P-type well region; 8: second deep trench; 9: first polysilicon layer; 10: second polysilicon layer; 11: heavily P-type doped region; 12: heavily N-type doped region; 13: passivation layer; 14: N-type active region. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] This invention proposes a method for fabricating a high-reliability MOS device structure with three buffer layers, specifically including the following steps:

[0035] Step 1: An N-drift layer 2 and a second buffer layer 3 are sequentially grown on the N-substrate layer 1, with the substrate serving as the drain.

[0036] Step 2: Form a first deep trench 5 in the middle of the cell by etching, and inject ions at the bottom of the first deep trench to form a third buffer layer 4;

[0037] Step 3: Deposit an oxide layer in the first deep trench to fill the first deep trench, and then form the first buffer layer 6 by implanting ions on both sides of the first deep trench in the second buffer layer;

[0038] Step 4: Grow a P-type well region 7 on the surface of the second buffer layer;

[0039] Step 5: Etch the P-type well region. The etching position is consistent with the position of the first deep trench, and the etching depth is consistent with the thickness of the P-type well region. After etching, remove the oxide layer filled in the first deep trench to form the second deep trench 8.

[0040] Step 6: Deposit an oxide layer with a thickness of 3500 angstroms on the inner surface of the second deep trench, and fill the second deep trench with the first polysilicon layer 9;

[0041] Step 7: Etch the polysilicon in the second deep trench to make it 0.9um~1.2um below the P-type well region, and fill the etched area with an oxide layer;

[0042] Step 8: Etch the oxide layer in the second deep trench to make it 2um~2.2um below the surface, then deposit a 3000A oxide layer on the sidewall of the second deep trench, and then fill the etched trench with polysilicon to form a second polysilicon layer 10, which serves as the gate.

[0043] Step 9: Ions are implanted on both sides of the second polysilicon layer to form N-type heavily doped regions 12. The mesa is symmetrically etched on both sides so that the etched portion occupies half of the width of the mesa. Heavy doping is implanted from the upper surface of the etched area to form P-type heavily doped regions 11. Finally, an oxide layer 13 is grown on the surface of the second polysilicon layer and the N-type heavily doped regions.

[0044] Step 10: Deposit metal on the upper surface of the device to form an N-type active region 14.

[0045] As an optional implementation, this embodiment provides the following: Figures 1-10 The steps shown specifically include:

[0046] Step 1: Sequentially grow an N-type drift layer and a second buffer layer (N-type) on the N-substrate, wherein the doping concentration of the N-type drift layer is 3 × 10⁻⁶. 16 cm -3 ~5×10 16 cm -3 The thickness of the second buffer layer is 3um to 6um, and the doping concentration is 1×10⁻⁶. 16 cm -3 ~2×10 16 cm -3 Thickness is 1um~2um;

[0047] Step 2: Form the first deep trench in the middle of the cell by etching; input a concentration of 5×10 at the bottom of the first deep trench. 16 cm -3 ~2×10 17 cm -3 The ions form a third buffer layer;

[0048] Step 3: Deposit an oxide layer in the first deep trench to fill the first deep trench, and then inject an oxide layer with a concentration of 1×10⁻⁶ into the second buffer layers on both sides of the first deep trench. 17 cm -3 ~2×10 17 cm -3 The ions form the first buffer layer;

[0049] Step 4: Grow a P-type well region on the surface of the second buffer layer, with a doping concentration of 4 × 10⁻⁶. 12 cm -3 ~8×10 12 cm -3 Thickness requirement: 2µm;

[0050] Step 5: Etch the P-type well region. The etching position and shape are consistent with the first deep trench. Remove the oxide layer filling the first deep trench below to form a second deep trench extending from the P-type well region to the N drift layer.

[0051] Step 6: Deposit an oxide layer (SiO2) with a thickness of 3500 Å on the sidewalls and bottom of the second deep trench, and fill the remaining space with polycrystalline silicon;

[0052] Step 7: Etch the polysilicon to make it 0.9um~1.2um below the P-type well region. This polysilicon is the first polysilicon layer, which serves as a shielding gate. Fill the etched area with an oxide layer (SiO2).

[0053] Step 8: Etch the oxide layer in the second deep trench to make it 2um~2.2um below the surface, deposit a 3000A oxide layer (SiO2) on the sidewall of the etched area, and fill the etched trench with polysilicon;

[0054] Step 9: First, implant a concentration of 5 × 10⁻⁶ in the P-type well region on both sides of the second polysilicon layer. 18 cm -3 ~1×10 19 cm -3 The ions form an N-type heavily doped region; then, the P-type well regions at both ends of the mesa are symmetrically etched, i.e., etching is performed from both ends toward the middle, with the etching thickness consistent with the thickness of the formed N-type heavily doped region. The total etching width is half the overall width of the device, i.e., one-quarter of the overall width of the device is etched at each end; finally, ions with a concentration of 1×10⁻⁶ are implanted from the etched upper surface. 15 cm -3 ~5×10 15 cm -3， The ions form a P-type heavily doped region in the P-type well region, and an oxide layer is generated above the N-type heavily doped region and the second polysilicon layer, which serves as a passivation layer.

[0055] Step 10: On the device surface, i.e. above the P-type heavily doped region and the oxide layer, a metal layer is deposited to form an N-type active region, which serves as the intermediate source.

[0056] As an optional implementation, when forming the first buffer layer in step 3, the depth of the first buffer layer is less than the thickness of the second buffer layer. After steps 1-10 above, the following can be obtained: Figure 11 The diagram shows a high-reliability MOS device structure with three buffer layers.

[0057] As another optional implementation, when forming the first buffer layer in step 3, the depth of the first buffer layer is equal to the thickness of the second buffer layer. After steps 1-10 above, the following can be obtained: Figure 12 The diagram shows a high-reliability MOS device structure with three buffer layers.

[0058] As another optional implementation, in step 2 when forming the third buffer layer, the third buffer layer is brought into contact with the substrate, and in step 3 when forming the first buffer layer, the depth of the first buffer layer is equal to the thickness of the second buffer layer. Through the above steps 1-10, the following can be obtained: Figure 13 The diagram shows a high-reliability MOS device structure with three buffer layers.

[0059] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a high-reliability MOS device structure with three buffer layers, characterized in that, Specifically, the following steps are included: Step 1: Grow an N-type drift layer and a second buffer layer sequentially on the substrate, with the substrate serving as the drain. The doping concentration of the N-type drift layer is 3 × 10⁻⁶. 16 cm -3 ~5×10 16 cm -3 The thickness is 3um to 6um; the doping concentration of the second buffer layer is 1×10⁻⁶. 16 cm -3 ~2×10 16 cm -3 The thickness is 1um to 2um; Step 2: Form a first deep trench in the middle of the cell by etching, and inject ions at the bottom of the first deep trench to form a third buffer layer; Step 3: Deposit an oxide layer in the first deep trench to fill the first deep trench, and then form a first buffer layer on both sides of the first deep trench in the second buffer layer by implanting ions. Step 4: Grow a P-type well region on the surface of the second buffer layer; Step 5: Etch the P-type well region. The etching position is consistent with the position of the first deep trench, and the etching depth is consistent with the thickness of the P-type well region. After etching, remove the oxide layer filling the first deep trench to form the second deep trench. Step 6: Deposit an oxide layer with a thickness of 3500 angstroms on the inner surface of the second deep trench, and fill the second deep trench with a first polysilicon layer, which serves as a buried gate. Step 7: Etch the polysilicon in the second deep trench to make it 0.9um~1.2um below the P-type well region, and fill the etched area with an oxide layer; Step 8: Etch the oxide layer in the second deep trench to make it 2um~2.2um below the surface, then deposit a 3000A oxide layer on the sidewall of the second deep trench, and then fill the etched trench with polysilicon to form a second polysilicon layer, which serves as the gate. Step 9: N-type heavily doped regions are formed on both sides of the second polysilicon layer by implanting ions. The mesa is symmetrically etched on both sides so that the etched portion occupies half of the width of the mesa. P-type heavily doped regions are formed by implanting heavy doping from the upper surface of the etched area. Finally, an oxide layer is grown on the surface of the second polysilicon layer and the N-type heavily doped region. Step 10: Deposit metal on the upper surface of the device to form the source.

2. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, Make the third buffer layer contact the substrate.

3. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, The doping concentration of the third buffer layer is 5×10⁻⁶. 16 cm -3 ~2×10 17 cm -3 .

4. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, The doping concentration of the first buffer layer is 1×10⁻⁶. 17 cm -3 ~2×10 17 cm -3 .

5. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, The doping concentration of the P-type well region is 4 × 10⁻⁶. 12 cm -3 ~8×10 12 cm -3 The thickness of the P-type well region is 2 μm.

6. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, The depth of the first buffer layer is less than or equal to the thickness of the second buffer layer.

7. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, When generating the heavily doped N-type region, the ion implantation concentration is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 In the P-type heavily doped region, the ion implantation concentration is 1×10⁻⁶. 15 cm -3 ~5×10 15 cm -3 .

8. The method for fabricating a high-reliability MOS device structure with three buffer layers according to claim 1, characterized in that, The oxide layer is made of SiO2.

9. A high-reliability MOS device structure with three buffer layers, characterized in that, The high-reliability MOS device structure with three buffer layers is prepared according to any one of claims 1 to 8.

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