FPGA-based parallelized constant false alarm detection method and system

Abstract

The application discloses a kind of parallelization constant false alarm detection method and system based on FPGA, it is related to radar, data processing technology, including, detection area is divided into N subareas on speed dimension, each subarea processes M consecutive speed points, and there is overlap area between adjacent subareas;Receive external input echo data and global parameter, calculate distance gate number and speed gate number for each data sample;Each subarea detection module executes the following operation in parallel: determine whether data belongs to the storage range of this subarea, and store data locally;In local detection area, peak detection is carried out using nine-square method, and candidate peak point is identified;Signal-to-noise ratio calculation is carried out on candidate point to determine effective target;The effective target results output by each subarea are summarized in subarea order, and are combined into global target list output by top control module.The application significantly reduces the overall processing delay of constant false alarm detection within the constraints of radar resources and power consumption through subarea parallel and overlap strategy design.

Description

Technical Field

[0001] This application relates to the fields of radar and data processing technology, and in particular to a parallelized constant false alarm rate (CFAR) detection method and system based on FPGA. Background Technology

[0002] In existing literature and engineering implementations, the ZYNQ architecture is widely used as the mainstream processing scheme for radar. This architecture achieves a balance between processing performance and system integration through the collaborative work of on-chip programmable logic (PL) and processing system (PS). The PL utilizes parallel logic resources to perform real-time processing of high-speed signals, while the PS relies on an embedded processor to perform complex logical operations such as data aggregation and decision control. Common characteristics of this type of scheme include: partitioning the data into segments based on velocity or range dimensions; local buffering of data in each sub-unit and outputting candidate targets using a FIFO; peak discrimination using neighborhood comparison and calculation of the mean or weighted sum of several neighboring units outside the protection unit as the noise floor; and sorting / merging the detection results from each partition before outputting the results. The differences between these schemes lie in the partition size, overlap strategy, noise floor selection path, storage mapping method, and degree of parallelism.

[0003] The existing technology is a partitioned parallel CFAR implementation based on FPGA, but the publicly available solutions usually do not provide complete optimization and implementation details on partition overlap strategy, memory address mapping, RAM depth and parallel tick budget, and engineering constraints on the platform.

[0004] The existing technology has the following problems: 1) Serial or low-level parallel processing leads to latency: If the detection process performs peak and SNR calculations sequentially within a single processing unit, the task execution time increases linearly with the number of detection units. High real-time performance is required, therefore serial processing cannot meet these requirements.

[0005] 2) Noise estimation bias at partition boundaries: If no overlapping or compensation strategy is adopted at the partition boundaries, the neighborhood noise basis sampling will lack real neighborhood information at the boundaries, resulting in the threshold estimation being too low or too high, thus introducing false detections or missed detections.

[0006] 3) RAM read bandwidth / latency limitation: Peak determination requires reading nine neighboring units simultaneously, and SNR estimation requires multiple random reads. If the design does not pipeline the access or does not use dual-port RAM, the concurrent read requirements cannot be met in a single cycle, causing a processing bottleneck.

[0007] 4) Results ordering and cache pressure: Parallel modules generate detection results simultaneously. If the aggregation module does not have an effective caching and reading strategy, output disorder, decreased throughput, or cache overflow problems may occur. Summary of the Invention

[0008] This application provides a parallelized constant false alarm rate (CFAR) detection method and system based on FPGA. Within the resource and power consumption constraints of the radar, the overall processing latency of CFAR detection is significantly reduced through partitioned parallel and overlapping strategies.

[0009] This application provides a parallelized constant false alarm rate (CFAR) detection method based on FPGA, including a top-level control module and several partition detection modules with identical structures. The top-level control module is used for global system control, parameter distribution, and result integration. The partition detection modules are used to receive data from their respective partitions and complete the CFAR detection process in parallel. The CFAR detection method includes: The entire detection area is divided into N partitions along the velocity dimension. Each partition is responsible for processing M consecutive velocity points, and there is an overlapping area between adjacent partitions. The top-level control module receives externally input echo data and global parameters, calculates the distance gate number and velocity gate number for each data sample, and distributes the data and parameters to each partition detection module. Each partition detection module performs the following operations in parallel: Determine whether the data belongs to the storage range of this partition. If so, store the data locally according to the preset address mapping relationship. Within the local detection area, the nine-square grid method is used to detect peaks and identify candidate peak points; The signal-to-noise ratio of candidate points is calculated, and a two-dimensional joint judgment is made using velocity and distance dimensions. If the detection thresholds of both velocity and distance dimensions are met simultaneously, the target is determined to be a valid target. The valid target results output from each partition are summarized in partition order and merged into a global target list output through the top-level control module.

[0010] This application provides an FPGA-based parallelized constant false alarm rate (CFAR) detection system, including a top-level control module and several structurally identical partition detection modules. The top-level control module is used for global system control, parameter distribution, and result integration. The partition detection modules are used to receive data within their respective partitions and complete the CFAR detection process in parallel. The top-level control module and the several structurally identical partition detection modules work together to implement the steps of the aforementioned FPGA-based parallelized CFAR detection method.

[0011] This application provides engineering-implementable hardware details to ensure that this application can be directly implemented on an FPGA and meet application requirements. Within the resource and power consumption constraints of the radar, the overall processing latency of constant false alarm detection is significantly reduced through partitioned parallel and overlapping strategy design.

[0012] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0013] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the overall architecture of the constant false alarm rate (CFAR) detection method according to an embodiment of this application; Figure 2 This is a schematic diagram of the data partitioning strategy for the constant false alarm rate (CFAR) detection method in this application embodiment; Figure 3 This is a schematic diagram of the partition detection process of the constant false alarm rate (CFAR) detection method in this application embodiment; Figure 4 This is a schematic diagram of the nine-grid peak detection method for the constant false alarm rate (CFAR) detection method in this application embodiment; Figure 5 This is a schematic diagram of the signal-to-noise ratio detection process of the constant false alarm rate (CFAR) detection method in this application embodiment. Detailed Implementation

[0014] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0015] CFAR is a type of adaptive threshold detection method, with common variations including cell-averaged CFAR (CA-CFAR) and rank-statistical CFAR (OS-CFAR). Its core idea is to estimate the noise floor of the detection cell using surrounding noise or clutter and set a threshold accordingly, thereby maintaining a constant false alarm rate under different background conditions.

[0016] FPGA / programmable logic implementation features: FPGAs offer high parallelism, customizable memory, and high-speed I / O, making them suitable for real-time parallel processing of radar echo streams. Dual-port RAM, FIFOs, hardware multiply-accumulate units (DSP units), and pipelines are common implementation resources.

[0017] This application addresses several technical shortcomings in the engineering implementation of Constant False Alarm Rate (CFAR) detection in radar by proposing a parallel CFAR detection method based on FPGA. Specific technical issues include: Increased processing time: Existing CFAR processing solutions (especially serial or semi-serial processing architectures) struggle to complete all detections within a very short timescale under limited hardware resources, resulting in significant processing delays and failing to meet stringent real-time requirements; Hardware resource and power consumption conflicts: Many general-purpose FPGA+DSP or multi-chip solutions are bulky and power-intensive, hindering the small size and low power consumption constraints of equipment; Boundary effects leading to noise estimation errors: When the detection area is divided into multiple sub-regions, without proper overlap or boundary processing, noise basis estimation biases will occur at the partition boundaries, affecting constant false alarm threshold calculation and target decision; High peak and basis read overhead: Peak detection (e.g., using a nine-grid approach) and signal-to-noise ratio (SNR) calculation require numerous random RAM read operations. Without parallel design or proper storage organization, this can lead to RAM bandwidth bottlenecks and read delays; Orderliness and delay in result aggregation and output: The orderly merging and output of results after parallel detection of each partition may introduce data sorting and caching pressures.

[0018] A specific parallel constant false alarm rate (CFAR) detection method based on FPGA, such as... Figure 1 , Figure 2 As shown, the system includes a top-level control module and several structurally identical partition detection modules. Subsequent examples in this application use 16 modules as an example; other methods are not listed individually. The top-level control module is responsible for global system control, parameter distribution, and result integration. The partition detection modules are responsible for receiving data within their respective partitions and performing core CFAR detection processes in parallel, including data storage, peak detection, and signal-to-noise ratio calculation.

[0019] The constant false alarm rate (CFAR) detection method includes: In step S100, the entire detection area is divided into N partitions along the velocity dimension. Each partition is responsible for processing M consecutive velocity points, and there is an overlap between adjacent partitions. Correspondingly, in this embodiment, the entire detection area (e.g., 2048 velocity points) is divided into N (e.g., 16) partitions along the velocity dimension. Each partition is responsible for processing M (e.g., 128) consecutive velocity points. Crucially, as... Figure 2 As shown, this application has an overlapping region (e.g., 10 velocity points) between adjacent partitions. This design ensures that each partition can obtain sufficiently continuous signal samples at the boundary when calculating the noise basis, thereby avoiding boundary evaluation errors caused by partitioning and guaranteeing the overall accuracy of CFAR detection.

[0020] In some specific examples of this application, the top-level control module is further composed of three sub-modules: Collaborative parameter calculation submodule: Parses externally input control commands, obtains global parameters such as speed gate-distance gate detection range, CFAR detection threshold, total number of speed points, etc., and broadcasts these parameters to all partition detection modules.

[0021] The positioning parameter calculation submodule calculates the precise coordinates (i.e., distance gate and velocity gate) of each input echo data sample within the entire detection space. Its calculation logic is as follows: The input data stream is cyclically counted; distance gate = count value >> log2(total velocity points); velocity gate = count value & (total velocity points - 1). The calculated coordinates are sent to each partition along with the data.

[0022] The detection result aggregation submodule contains N FIFOs (First-In-First-Out Memory), each corresponding to one of the N partitions. Each partition sends the detected valid target results into its corresponding FIFO. The aggregation module reads all FIFOs sequentially, merges them into a global target list, and then outputs it. Due to the existence of overlapping regions, complex deduplication operations are unnecessary.

[0023] like Figure 3 As shown, in step S101 of the method of this application, the externally input echo data and global parameters are received through the top-level control module, the distance gate number and velocity gate number are calculated for each data sample, and the data and parameters are distributed to each partition detection module.

[0024] In step S102, each partition detection module performs the following operations in parallel: Determine whether the data belongs to the storage range of this partition. If so, store the data locally according to the preset address mapping relationship. In step S103, peak detection is performed using the nine-square grid method within the local detection area to identify candidate peak points; In step S104, the signal-to-noise ratio of the candidate points is calculated, and a two-dimensional joint judgment is made using velocity and distance dimensions. If the detection thresholds of both velocity and distance dimensions are met simultaneously, the target is determined to be a valid target. In step S105, the valid target results output by each partition are summarized in partition order and merged into a global target list output through the top-level control module.

[0025] This application provides engineering-implementable hardware details to ensure that this application can be directly implemented on an FPGA and meet application requirements. Within the resource and power consumption constraints of the radar, the overall processing latency of constant false alarm detection is significantly reduced through partitioned parallel and overlapping strategy design.

[0026] In some embodiments of this application, the process of parallel execution of each partition detection module specifically includes: Each of the partition detection modules receives input data from the top-level control module and determines whether the speed gate number V of the input data is within the storage range (B_i, E_i) of this partition. If not, the data is discarded and the process ends for processing this data.

[0027] If so, the storage address of the data in the local memory (such as dual-port RAM) is calculated according to the predetermined address mapping relationship, and the data is stored in that address.

[0028] The input data includes echo data values, corresponding distance gate R and velocity gate V, and cooperative parameters (such as detection threshold, working mode, etc.).

[0029] In some embodiments of this application, the method further includes determining data attribution and calculation based on data coordinates (distance gate number IR, velocity gate number IV) and global parameters issued from the top layer, wherein: Determining data ownership includes: determining whether the current data belongs to the storage range of this partition; if so, calculating its storage address in local memory (dual-port RAM); otherwise, discarding it.

[0030] Calculate the detection range: Based on the global detection range parameters, calculate the start and end indices of the local velocity gates that actually need to participate in CFAR detection for this partition. The mapping formula for data storage addresses is:

[0031] in, and These represent the distance gate number and speed gate number input from the external system, respectively. Indicates the lower limit of the current partition speed gate detection. Indicates the partition number.

[0032] In some embodiments of this application, when data storage is complete or read on demand, the module scans within a two-dimensional detection area consisting of the effective detection range (D_start_i, D_end_i) and the distance gate range, employing a "nine-grid" method for local peak detection, such as... Figure 4 As shown, it specifically includes: Centered on the current detection unit, obtain the values ​​of its eight neighboring units and itself; Determine whether the value of the central unit is greater than the values ​​of all eight of its adjacent units.

[0033] If not, move the scan index to the next unit and continue the scan.

[0034] If so, the central unit is determined to be a candidate peak point, and its amplitude, local velocity gate number, and distance gate number are stored in the peak first-in-first-out (FIFO) memory. In this application, FIFO is used as an example, and other memory forms are not listed one by one.

[0035] In some embodiments, after peak detection is completed, such as Figure 5 As shown, the method of this application further verifies the signal-to-noise ratio for each candidate peak point in the peak FIFO: Determine if the peak FIFO is empty.

[0036] If so, the process ends.

[0037] If not, read a candidate peak point from the peak FIFO and obtain its information.

[0038] Centered on the peak point, noise reference cells are selected in the distance and velocity dimensions respectively (e.g., 8 cells before and after), and adjacent protection cells are skipped (e.g., 1 cell before and after).

[0039] Calculate the distance-dimensional noise basis and the velocity-dimensional noise basis respectively.

[0040] Calculate the signal-to-noise ratio of the peak point relative to the noise floor in both the distance and velocity dimensions, and determine whether it is simultaneously greater than the preset detection thresholds for both the distance and velocity dimensions.

[0041] If not, discard the candidate point and return to determine if the peak FIFO is empty, then process the next peak point.

[0042] If so, the point is determined to be a valid target point.

[0043] In some embodiments, after determining a valid target point, the method further includes: for a valid target point, calculating its coordinates in the global velocity dimension based on its local velocity gate number and the local partition index i: global velocity gate number = local velocity gate number + i*M, and its distance gate number remains unchanged.

[0044] In some embodiments of this application, peak detection using the nine-grid method further includes: Detection parameter initialization: The distance index and velocity index are set to the detection start position, and the peak value buffer FIFO is cleared; Read and save the data of the "nine-square grid" according to the current detection position: Based on the detection position, deduce the reading address of each position of the nine-square grid, read the specified data from RAM and store it. If the data to be read is outside the boundary, set the value to 0. Determine if the saved "nine-square grid" data points are the maximum value. If they are, output the detection center point and its speed-distance gate number. If the detection result is a peak point, increment the speed index by 2; otherwise, increment the speed index by 1. When the speed index exceeds the speed detection threshold, the speed index is set to the speed detection start position, and the distance index is incremented by 1. If the distance index exceeds the distance detection threshold, it indicates that the peak detection has ended, the detection is exited, and the detection loop continues.

[0045] In some embodiments of this application, the signal-to-noise ratio of candidate points is calculated, and a two-dimensional joint judgment is made using velocity and distance dimensions. If both velocity and distance detection thresholds are met, the target is determined to be a valid target. This further includes: Read a peak data point from the peak detection results and obtain its detection value. and speed gate - distance gate; Based on the peak distance gate number, calculate the cell address of the distance protection unit and the distance noise substrate. If the distance noise reading address is out of bounds, set the reading value to 0; otherwise, calculate the number of distance noise substrates. Add 1; Based on the peak speed threshold, calculate the cell addresses of the speed protection unit and the speed noise substrate. When the cell is identified as noise, count the number of speed noise substrates. Add 1; Calculate the sum of velocity-dimensional noise The sum of distance dimension noise ; Determine whether the current peak value exceeds the speed signal-to-noise ratio detection threshold. and distance detection threshold :

[0046] If the current peak signal-to-noise ratio calculation satisfies both of the above equations, then the current peak value is considered a valid target, and the parameter is output.

[0047] In some embodiments of this application, the output of merging into a global target list by the top-level control module includes: If the current peak signal-to-noise ratio exceeds the threshold, the speed gate number... and distance to door number According to the partition number Converted to actual speed gate number and distance to door number .

[0048] The embodiments of this application describe an architecture based on the velocity dimension, which is divided into 16 partitions for parallel detection. Each partition is responsible for a fixed velocity threshold interval and performs peak value and SNR detection in parallel.

[0049] An overlap strategy that retains a fixed number of overlapping points (e.g., 10 points) between partitions is used to eliminate noise estimation errors at partition boundaries and ensure the stability of the CFAR threshold.

[0050] The partition uses a dual-port RAM with a depth of 2368 as a local cache and a storage mapping method that calculates the mapping address based on (distance gate number, speed gate number), which includes specific address calculation logic.

[0051] The hardware implementation of the nine-grid peak detection algorithm includes details on neighborhood reading, boundary overrun handling (setting to 0), and the implementation of the velocity index jump rule after detection (+2 after peak, +1 after non-peak).

[0052] The velocity-distance two-dimensional joint SNR decision method is a technical solution that simultaneously takes several preceding and following units in both the velocity and distance dimensions as noise bases and excludes protected units, and then determines the effective target based on the dual threshold conditions.

[0053] The mechanism is based on the output of 16 partitions to independent FIFOs, and the results are aggregated and output in an orderly manner by the top layer according to the partition order / timestamp.

[0054] Tick ​​budget and timing guarantee scheme: including peak value determination of about 18 ticks / point, SNR calculation of about 50 ticks / point, and system-level timing constraints and implementation methods with a total estimated time of less than 250μs for a single partition under a 200MHz working clock.

[0055] A fast parsing method for bitmasks and powers (2^n) of threshold and velocity point numbers is used for efficient location and distribution of partition detection parameters.

[0056] The out-of-bounds handling, protection unit strategy, FIFO overflow detection, and fault-tolerant design for fault recovery in this application are the key parts of the method in the engineering implementation of this application.

[0057] The method in this application divides the entire velocity-distance detection space into several parallel partitions, and within each partition, employs dual-port RAM, nine-grid peak detection, and joint velocity-distance SNR judgment to form a CFAR implementation scheme that can operate with high parallelism while ensuring the continuity of boundary noise estimation. The main advantages can be derived as follows: Parallel partitioning and hardware pipelined processing reduce the detection time of a single partition to the sub-millisecond level, with an actual measured value of approximately 238μs, which is far superior to the 4ms level of traditional solutions, significantly reducing processing latency.

[0058] The partitioned overlap strategy and joint SNR decision reduce boundary errors and false alarms, improve the detection rate and false alarm suppression capability of the system in complex electromagnetic environments, and enhance detection robustness and accuracy.

[0059] This application proposes clear RAM depth, clock budget, and interface definitions, which can be directly implemented on the FPGA (or ZYNQ) platform, meeting strict constraints on size, power consumption, and real-time performance. It is engineering-friendly and has great potential for widespread application.

[0060] The number of partitions, overlap width, noise floor size, and threshold can all be flexibly configured in the top-level parameters, making it easy to adapt to the needs of different radar models or different environments, and it has strong scalability and configurability.

[0061] This application also proposes an FPGA-based parallelized constant false alarm rate (CFAR) detection system, including a top-level control module and several structurally identical partition detection modules. The top-level control module is used for global system control, parameter distribution, and result integration. The partition detection modules are used to receive data within their respective partitions and complete the CFAR detection process in parallel. The top-level control module and the several structurally identical partition detection modules work together to implement the steps of the aforementioned FPGA-based parallelized CFAR detection method.

[0062] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0063] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0064] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0065] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A parallelized constant false alarm rate (CFAR) detection method based on FPGA, characterized in that, The system includes a top-level control module and several structurally identical partition detection modules. The top-level control module is used for global system control, parameter distribution, and result integration. The partition detection modules receive data from their respective partitions and complete the CFAR detection process in parallel. The constant false alarm rate (CFAR) detection method includes: The entire detection area is divided into N partitions along the velocity dimension. Each partition is responsible for processing M consecutive velocity points, and there is an overlapping area between adjacent partitions. The top-level control module receives externally input echo data and global parameters, calculates the distance gate number and velocity gate number for each data sample, and distributes the data and parameters to each partition detection module. Each partition detection module performs the following operations in parallel: Determine whether the data belongs to the storage range of this partition. If so, store the data locally according to the preset address mapping relationship. Within the local detection area, the nine-square grid method is used to detect peaks and identify candidate peak points; The signal-to-noise ratio of candidate points is calculated, and a two-dimensional joint judgment is made using velocity and distance dimensions. If the detection thresholds of both velocity and distance dimensions are met simultaneously, the target is determined to be a valid target. The valid target results output from each partition are summarized in partition order and merged into a global target list output through the top-level control module. The process of parallel execution of each partition detection module specifically includes: Each of the partition detection modules receives input data from the top-level control module and determines whether the speed gate number V of the input data is within the storage range of this partition. If so, it calculates the address of the data in the local memory according to the predetermined address mapping relationship and stores it. The input data includes echo data values, corresponding range gate R and velocity gate V, and cooperative parameters; This also includes determining data ownership and performing calculations based on data coordinates and global parameters issued from the top level, including: Determining data ownership includes: determining whether the current data belongs to the storage range of this partition; if so, calculating its storage address in local memory. Calculate the detection range: Based on the global detection range parameters, calculate the start and end indices of the local velocity gates that actually need to participate in CFAR detection for this partition. The mapping formula for data storage addresses is: in, and These represent the distance gate number and speed gate number input from the external system, respectively. Indicates the lower limit of the current partition speed gate detection. Indicates the partition number.

2. The FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in claim 1, characterized in that, Within the local detection area, peak detection is performed using a nine-square grid method, and candidate peak points are identified, including: Centered on the current detection unit, obtain the values ​​of its eight neighboring units and itself; If the value of the central unit is greater than the values ​​of all eight of its adjacent units, the central unit is identified as a candidate peak point, and its amplitude, local velocity gate number, and distance gate number are recorded.

3. The FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in claim 2, characterized in that, Peak detection using the nine-grid method specifically includes: Perform parameter initialization, set the distance and velocity indices to the detection start position, and clear the peak value cache; Based on the current detection position, read and save the data of the nine-square grid. Based on the detection position, deduce the reading address of each position of the nine-square grid, so as to read the specified data according to the reading address and store it. If the data to be read is outside the boundary, the value is set to 0. If the saved 3x3 grid data center point is the maximum value, output the detection center point and its speed-distance threshold. If the detection result is the peak point, increment the speed index by 2; otherwise, increment the speed index by 1. If the speed index exceeds the speed detection threshold, set the speed index to the speed detection start position and increment the distance index by 1. If the distance index exceeds the distance detection threshold, peak detection ends and detection is terminated.

4. The FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in claim 2, characterized in that, After determining the valid target point, the following steps are also included: For the valid target point, its coordinates in the global velocity dimension are calculated based on its local velocity gate number and the local partition index i: global velocity gate number = local velocity gate number + i*M, and its distance gate number remains unchanged.

5. The FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in claim 2, characterized in that, After peak detection is completed, the signal-to-noise ratio of each recorded candidate peak point is verified. After verification, noise reference cells are selected in the distance and velocity dimensions, respectively, with the peak point as the center, and adjacent protection cells are skipped. Calculate the distance-dimensional noise basis and the velocity-dimensional noise basis respectively; Calculate the signal-to-noise ratio of the peak point relative to the noise floor in both the distance and velocity dimensions, and determine if it is greater than both the preset detection thresholds in the distance and velocity dimensions to identify the point as a valid target point.

6. The FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in claim 5, characterized in that, The signal-to-noise ratio of candidate points is calculated, and a two-dimensional joint judgment is made using velocity and distance dimensions. If the detection thresholds of both velocity and distance dimensions are met, the point is considered a valid target. Other targets include: Read a peak data point from the peak detection results and obtain its detection value. and speed gate - distance gate; Based on the peak distance gate number, calculate the cell address of the distance protection unit and the distance noise substrate. If the distance noise reading address is out of bounds, set the reading value to 0; otherwise, calculate the number of distance noise substrates. Add 1; Based on the peak speed threshold, calculate the cell addresses of the speed protection unit and the speed noise substrate. When the cell is identified as noise, count the number of speed noise substrates. Add 1; Calculate the sum of velocity-dimensional noise The sum of distance dimension noise ; Determine whether the current peak value exceeds the speed signal-to-noise ratio detection threshold. and distance detection threshold : If the current peak signal-to-noise ratio calculation satisfies both of the above equations, then the current peak value is considered a valid target, and the parameter is output.

7. The FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in claim 6, characterized in that, The output, merged into a global target list by the top-level control module, includes: If the current peak signal-to-noise ratio exceeds the threshold, the speed gate number... and distance to door number According to the partition number Converted to actual speed gate number and distance to door number .

8. A parallelized constant false alarm rate (CFAR) detection system based on FPGA, characterized in that, The system includes a top-level control module and several structurally identical partition detection modules. The top-level control module is used for global system control, parameter distribution, and result integration. The partition detection modules are used to receive data within the corresponding partitions and complete the CFAR detection process in parallel. The top-level control module and the several structurally identical partition detection modules work together to implement the steps of the FPGA-based parallelized constant false alarm rate (CFAR) detection method as described in any one of claims 1-7.

Images