Method for writing multi-level mapping table of solid state disk and solid state disk
By writing the entry data of the multi-level mapping table and the checkpoint data into the same programming unit in the flash memory chip in the DRAM-less solid-state drive, the write amplification problem is solved, and the lifespan of the hard drive and the yield of the flash memory chip are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MAXIO TECHNOLOGY (HANGZHOU) CO LTD
- Filing Date
- 2025-11-19
- Publication Date
- 2026-07-21
Smart Images
Figure CN121455421B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of memory technology, specifically to a method for writing a multi-level mapping table of a solid-state drive (SSD) and the SSD itself. Background Technology
[0002] With the widespread use of solid-state drives (SSDs), SSDs with DRAM-less architecture have been widely used in personal computers, industrial control, and data center caching layers due to the cost and power consumption advantages brought by eliminating external cache.
[0003] In DRAM-less solid-state drives, due to the limited capacity of cache units, a multi-level mapping table structure is often used. In the multi-level mapping table, the upper-level mapping table stores the physical address of the lower-level mapping table, and the lowest-level mapping table stores the L2P (logic to physical) data of each data unit.
[0004] Taking a three-level mapping table as an example, the three-level mapping table includes a level 1 mapping table L0, a level 2 mapping table L1, and a level 3 mapping table L2. The level 3 mapping table L2 stores 1024 data units of L2P data. Since flash memory chips cannot be overwritten, the updated entries of the level 2 mapping table L1 and the level 3 mapping table L2 are first cached in the controller's cache unit. After accumulating to a threshold, they are sequentially flushed into the flash memory chips. The traditional process is: update the level 3 mapping table L2 in the cache → write the level 3 mapping table L2 to the flash memory chips → update the level 2 mapping table L1 in the cache → write the level 2 mapping table L1 to the flash memory chips → update the entries of the level 1 mapping table L0 in the cache → write the checkpoint data to the flash memory chips. The checkpoint data records the boundary information of this table flushing process.
[0005] The above process needs to be executed serially. At the same time, in continuous write scenarios, the entries or checkpoint data of the third-level mapping table L2 and the second-level mapping table L1 often cannot fill a programming unit (pu), and a large amount of invalid (dummy) data needs to be filled, resulting in write amplification and affecting the lifespan of the flash memory chip. Summary of the Invention
[0006] To address the aforementioned issues, this disclosure proposes a multi-level mapping table writing method for solid-state drives (SSDs) and an SSD itself.
[0007] In a first aspect, embodiments of this disclosure provide a method for writing a multi-level mapping table to a solid-state drive (SSD), the SSD including a controller and a storage medium composed of flash memory chips, the multi-level mapping table writing method being executed by the controller, including:
[0008] Obtain the pre-calculated target physical address, where the target physical address represents the physical address in the storage medium of the data packet of solid size composed of the table entries of the second to Nth level mapping tables that are about to be written in the cache unit of the controller, where N is a positive integer greater than 2;
[0009] Update the corresponding entries in the first-level mapping table to the (N-1)th-level mapping table based on the target physical address;
[0010] Construct checkpoint data and organize the checkpoint data into a data packet. The checkpoint data is used to record the boundary information of this mapping table flush.
[0011] The data packets of the checkpoint data and the data packets of the table entry data are organized into the same programming unit and written to the storage medium in a single programming operation.
[0012] In some embodiments, the method further includes organizing the RAID data packets, the checkpoint data packets, and the table entry data packets into the same programming unit.
[0013] In some embodiments, the method further includes: when the mapping table entry accessed by the read operation has not yet been flushed to the storage medium, by combining the old mapping table entry in the cache unit of the controller with the write cache that records the new mapping table entry, to collaboratively provide the L2P data required for the read operation.
[0014] In some embodiments, the multi-level mapping table flushing method is performed when a triggering condition is met, the triggering condition including that the table entry data of the Nth level mapping table is greater than a set threshold; or, the triggering condition is that the user data written in a continuous write scenario exceeds a set threshold.
[0015] In some embodiments, the checkpoint data is constructed based on the updated Level 1 mapping table.
[0016] In some embodiments, the multi-level mapping table is a 3-level mapping table.
[0017] In some embodiments, the flash memory chip supports multi-plane programming.
[0018] In some embodiments, the solid-state drive is a DRAM-less solid-state drive.
[0019] Secondly, embodiments of this disclosure provide a controller for a solid-state drive, the controller executing any of the multi-level mapping table writing methods described above.
[0020] Thirdly, embodiments of this disclosure provide a solid-state drive, including a controller and a storage medium composed of flash memory chips. The controller executes one or more computer instructions, and when the computer instructions are executed, the multi-level mapping table writing method described above is implemented.
[0021] The multi-level mapping table writing method provided in this embodiment has the following advantages: First, by writing the table entry data and checkpoint data of the multi-level mapping table into the flash memory chip in the same programming unit, invalid data written into the flash memory chip can be reduced, write amplification can be reduced, and the service life of the solid-state drive can be improved. Second, compared with the traditional process of writing multiple mapping tables and checkpoint data into the flash memory chip in multiple steps, this embodiment only requires programming once, so the mapping table writing time is less. Furthermore, this embodiment can also release the physical blocks originally used to store checkpoint data, reduce the occupation of physical blocks, and improve the factory yield of flash memory chips. Attached Figure Description
[0022] The above and other objects, features and advantages of the present disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0023] Figure 1 A schematic diagram of the host system is shown;
[0024] Figure 2 A schematic diagram of a three-level mapping table in a cache unit is given;
[0025] Figure 3 A schematic diagram is given of the three-level mapping table written to DIE 0 and DIE 1 of the flash memory chip according to the traditional process;
[0026] Figure 4 A flowchart of the multi-level mapping table flushing method proposed in the embodiments of this disclosure is provided;
[0027] Figure 5 A schematic diagram of the mapping table written to DIE 0 and DIE 1 of the flash memory chips according to an embodiment of the present disclosure is provided;
[0028] Figure 6 A flowchart illustrating the table lookup process during the flushing of a three-level mapping table is provided. Detailed Implementation
[0029] The following description of embodiments of the present disclosure is based on examples, but the embodiments of the present disclosure are not limited to these embodiments. In the detailed description of the embodiments of the present disclosure below, certain specific details are described in detail. Those skilled in the art can fully understand the embodiments of the present disclosure even without these detailed descriptions. To avoid obscuring the essence of the embodiments of the present disclosure, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.
[0030] The flowcharts and block diagrams in the accompanying drawings illustrate possible system frameworks, functions, and operations of the systems, methods, and apparatuses according to embodiments of this disclosure. The blocks in the flowcharts and block diagrams may represent a module, program segment, or simply a piece of code. These modules, program segments, and code are all executable instructions used to implement a specified logical function. It should also be noted that the executable instructions implementing the specified logical function can be recombined to generate new modules and program segments. Therefore, the blocks and their order in the accompanying drawings are only used to better illustrate the processes and steps of the embodiments and should not be construed as limiting the invention itself.
[0031] Figure 1 A schematic block diagram of a solid-state drive according to an embodiment of the present invention is shown.
[0032] like Figure 1 As shown, the computer system 100 includes a host 110 and a solid-state drive (SSD). The SSD includes a controller 120 and a storage medium 130. The controller 120 connects the host 110 and the storage medium 130, receives read and write commands from the host 110, writes data from the host 110 to the storage medium 130, and returns data read from the storage medium 130 to the host 110.
[0033] The controller 120 includes a host interface 121, a processor 123, a cache unit 124, and a storage media controller 125. The host interface 121 is connected to the host 110 to transmit data and read / write commands. The processor 123 is connected to the host interface 121, the cache unit 124, and the storage media controller 125. The processor 123 parses read / write commands and executes data read / write operations. The cache unit 124 stores a mapping table, and the storage media controller 125 controls data transmission and storage with the storage media 130. The processor 123, based on programs in the flash translation layer (FTL), decodes and executes read / write commands received from the host 110 to complete data read / write operations on the storage media 130. The FTL also includes programs for bad block management, wear leveling, garbage collection, power-off recovery, and write balancing.
[0034] Storage medium 130 is, for example, an array of flash memory chips. Storage medium controller 125 of controller 120 reads and writes to the flash memory chips connected to it via each channel (e.g., CH0 and CH2), with each channel connected to at least one flash memory chip.
[0035] Cache unit 124 can be SRAM and / or DRAM. Comparatively, SRAM offers speed advantages as a cache, but it is more expensive and has a smaller storage capacity per unit space. DRAM-less solid-state drives use only SRAM as cache units; therefore, to improve SRAM utilization efficiency, multi-level mapping tables are typically used for addressing management. Those skilled in the art will understand that a multi-level mapping table refers to a mapping table with three or more levels; however, a three-level mapping table is a superior design that guarantees higher memory addressing efficiency.
[0036] Figure 2 A schematic diagram of a three-level mapping table in a cache unit is provided. (Reference) Figure 2 In cache unit 124, all logical addresses (LAA) are equally divided into (n+1) groups (0 to n). The first-level mapping table can then be viewed as an array L1[n] with (n+1) elements (index starting from 0). Array L1[n] stores (n+1) index addresses, each pointing to a data block of the second-level mapping table L1. Each L1 entry in the second-level mapping table L1 points to a data block of the third-level mapping table L2. Each L2P mapping in the third-level mapping table L2 points to a fixed-size data unit (physical page or 4K cell) in the storage medium 130.
[0037] As user data and mapping table entries accumulate in cache unit 124, when a trigger condition is met, the mapping table flushing procedure is initiated to flush the table entry data of the multi-level mapping table to storage medium 130 and release the corresponding cache space. The trigger condition can be configured. For example, the trigger condition for an N-level mapping table (N is an integer greater than 2) is that the table entry data of the Nth level mapping table exceeds a set threshold, or the trigger condition is that the user data already written to the flash memory chip exceeds a set threshold.
[0038] Figure 3 A schematic diagram is provided illustrating the three-level mapping table written to DIE 0 and DIE 1 of the flash memory chip according to the traditional process. (Reference) Figure 3The flash memory chips DIE 0 and DIE 1 are divided into 8 planes in the column direction. Each plane includes physical pages arranged in the row direction, including page 0, page 1, page 2, etc. Each physical page consists of 4 4K cells. All 4K cells in each row of flash memory chips DIE 0 and DIE 1 correspond to a programming unit. Therefore, a programming unit that organizes 128K data is required each time programming is performed.
[0039] In the traditional process, a programming unit only stores the Level 3 mapping table L2, the Level 2 mapping table L1, or checkpoint data. If a programming unit stores the entire Level 3 mapping table L2, then 128K of Level 3 mapping table L2 corresponds to 128M of user data. In a continuous write scenario, if the user data is less than 128M, the number of entries in Level 3 mapping table L2 will be less than that of a programming unit. In this case, invalid data will be written when writing to the programming unit of Level 3 mapping table L2. The less user data written, the fewer the corresponding entries in Level 3 mapping table L2, and the more invalid data needs to be written. For example, the first to third rows of Die 0 of the flash memory chip in the diagram have a lot of invalid data written. At the same time, the Level 2 mapping table L1 corresponding to the Level 3 mapping table L2 being written only has one or two entries. Therefore, when writing to the programming unit of Level 2 mapping table L1, a lot of invalid data also needs to be written. For example, the first to third rows of Die 1 of the flash memory chip in the diagram.
[0040] To address the aforementioned problems, this disclosure proposes a multi-level mapping table flashing method. This multi-level mapping table flashing method can be formed into a computer program and exist in the solid-state drive in firmware or software form. The specific process is as follows: Figure 4 As shown.
[0041] In step S401, the pre-calculated target physical address is obtained. The target physical address represents the physical address in the storage medium of a fixed-size data packet consisting of entries from the second-level to the Nth-level mapping tables that are about to be flushed in the controller's cache unit, where N is a positive integer greater than 2.
[0042] Specifically, refer to Figure 3 As shown, a dedicated flash memory chip for storing the mapping table is predetermined. The table entries from the second to the Nth level mapping table to be written are grouped into a 4K data packet. Then, free physical blocks are sequentially retrieved from the physical block queue of the flash memory chip. The starting physical address of each page is calculated according to the block size and page size to form a "block-page base address table". Then, four 4K data packets are organized on each physical page address according to the "block-page base address table", and the physical address of each data packet is calculated as the target physical address.
[0043] In step S402, the corresponding entries in the first-level mapping table to the (N-1)th-level mapping table are updated based on the target physical address.
[0044] In step S403, checkpoint data is constructed and grouped into a data packet. Checkpoint data is used to record boundary information for this mapping table write. It is typically a fixed-length metadata segment and serves as an anchor point and consistency check marker for restoring the mapping table after the SSD powers on. This step expands the checkpoint data into the fixed-size data packet mentioned in step S401.
[0045] In step S404, the data packets of checkpoint data and the data packets of table entry data are organized into the same programming unit and written to the storage medium in a single programming operation.
[0046] According to this embodiment, the table entries of the second-level to Nth-level mapping tables to be written are formed into a data packet of solid size. Then, the physical address of each data packet in the storage medium is calculated, and the corresponding table entries in the first-level to N-1th-level mapping tables are updated accordingly. The data packet composed of checkpoint data and the data packet composed of table entry data are organized in the same programming unit and written to the storage medium 130 in a single programming operation, so that the checkpoint data and the second-level to Nth-level mapping tables are written to the storage medium in the same programming unit.
[0047] In some embodiments, checkpoint data is constructed based on the updated Level 1 mapping table to clarify the boundary information of this mapping table write. Moreover, since the Level 1 mapping table resides in the cache unit 124, constructing checkpoint data using the updated Level 1 mapping table facilitates the recovery of the mapping table after the solid-state drive is powered on.
[0048] Figure 5 A schematic diagram of the mapping table written to DIE 0 and DIE 1 of the flash memory chips according to an embodiment of this disclosure is provided. (See reference...) Figure 5 Each programming session requires organizing 128K programming units. In one embodiment, a programming unit can simultaneously store the corresponding Level 3 mapping table L2, Level 2 mapping table L1, checkpoint data, and RAID data. The mapping tables are written in this way. Combined with flash memory chips that support multiple plane programming, as shown in the diagram, each row of the flash memory chip occupies 18 4K cells for the Level 3 mapping table data, 2 4K cells for the Level 2 mapping table data, 4 cells for the checkpoint data, and the remainder is filled with invalid data or RAID data. Compared to… Figure 3 , Figure 5 The proportion of invalid data filling has been significantly reduced.
[0049] The lookup process for a multi-level mapping table is roughly as follows: First, the first-level mapping table is read to obtain the physical address of a second-level mapping table. Then, the physical address in that second-level mapping table is read to obtain the physical address of a third-level mapping table, and so on, until the (N-1)th level mapping table is read. This retrieves L2P data, which is the L2P data required for reading and writing data. Based on this L2P data, the corresponding physical address in the storage medium can be determined. However, considering that during the mapping table flushing process, the target physical addresses in the first to (N-1)th level mapping tables are updated in advance, but the table entry data has not yet been actually written to the storage medium, these updated mapping tables cannot be used to complete the lookup operation. A new lookup process needs to be adapted. Taking a three-level mapping table as an example... Figure 6 A flowchart illustrating the table lookup process during the mapping table flushing is provided.
[0050] As shown in the figure, when the second-level mapping table to be queried is not in the table flushing process, the table flushing does not affect the table lookup (step S606). If the second-level mapping table to be queried is in the table flushing process (step S601), since the table entries of the second-level and third-level mapping tables in the cache unit have been updated in advance, but the updated table entries of the second-level and third-level mapping tables have not yet been actually written to the flash memory, the updated second-level and third-level mapping tables cannot be used for table lookup. Then it is determined whether the old second-level mapping table has been read from the flash memory into the cache unit (step S602). If the old second-level mapping table has been read from the flash memory into the cache unit, since the old second-level mapping table corresponds to the old third-level mapping table, the table lookup result is obtained by using the old third-level mapping table and the write cache that records the new mapping table entries (S603 and S605). If the old second-level mapping table has not been read from the flash memory into the cache unit, the table lookup process must wait for the table flushing to finish before it can continue (S604). This process proposes that during the three-level mapping table flushing process, when the mapping table entry accessed by the read command has not yet been flushed to the storage medium, the correct table entry is obtained by reading the old three-level mapping table and the write cache that records the new mapping table entry, so as to ensure read and write order and maintain read performance during the table flushing process.
[0051] In summary, the multi-level mapping table writing method provided in this embodiment has the following advantages: First, by writing the table entry data and checkpoint data of the multi-level mapping table into the flash memory chip in the same programming unit, invalid data written into the flash memory chip can be reduced, write amplification can be reduced, and the service life of the solid-state drive can be improved. Second, compared with the traditional process of writing the table entry data and checkpoint data of multiple mapping tables into the flash memory chip in multiple steps, this embodiment only requires one programming, so the mapping table writing time is less. Furthermore, this embodiment can also release the physical blocks originally used to store checkpoint data, reduce the occupation of physical blocks, and improve the factory yield of flash memory chips.
[0052] Accordingly, embodiments of this disclosure also provide, for example... Figure 1 The solid-state drive controller and solid-state drive shown have readable computer instructions stored in the cache unit of the controller or the storage medium of the solid-state drive. When these instructions are executed by the processor, they can implement the steps of the multi-level mapping table flushing method described above.
[0053] Accordingly, this disclosure also provides a computer-readable storage medium for storing a computer program consisting of readable computer instructions that, when executed by a processor, can implement the steps of the multi-level mapping table flushing method described above.
[0054] A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium is, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium include: an electrical connection of one or more wires; a portable computer disk drive, hard disk drive, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory); optical fiber; portable compact disk read-only memory (CD-ROM); optical storage; magnetic storage; or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with a processing unit, apparatus, or device.
[0055] Computer-readable signal media may include data signals propagated in baseband or as part of a chopped signal, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in conjunction with an instruction system, apparatus, or device.
[0056] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, and any suitable combination thereof.
[0057] The computer programs described in this article can be written in one or more programming languages or combinations thereof, such as JAVA, C++, or conventional procedural programming languages, such as C. The computer programs can execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.
[0058] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the embodiments of this disclosure. For those skilled in the art, various modifications and variations can be made to the embodiments of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this disclosure should be included within the protection scope of the embodiments of this disclosure.
Claims
1. A method for writing a multi-level mapping table to a solid-state drive (SSD), the SSD comprising a controller and a storage medium composed of flash memory chips, the multi-level mapping table writing method being executed by the controller, comprising: Obtain the pre-calculated target physical address, where the target physical address represents the physical address in the storage medium of the data packet of solid size composed of the table entries of the second to Nth level mapping tables that are about to be written in the cache unit of the controller, where N is a positive integer greater than 2; Update the corresponding entries in the first-level mapping table to the (N-1)th-level mapping table based on the target physical address; Construct checkpoint data and organize the checkpoint data into a data packet. The checkpoint data is used to record the boundary information of this mapping table flush. The data packets of the checkpoint data and the data packets of the table entry data are organized into the same programming unit and written to the storage medium in a single programming operation.
2. The multi-level mapping table flushing method according to claim 1 further includes: The RAID data packets, the checkpoint data packets, and the table entry data packets are organized into the same programming unit.
3. The multi-level mapping table flushing method according to claim 1 further includes: During the execution of the multi-level mapping table flushing method, if the mapping table entry accessed by the read operation has not yet been flushed to the storage medium, the L2P data required for the read operation is provided in coordination by combining the old mapping table entries in the controller's cache unit with the write cache that records the new mapping table entries.
4. The multi-level mapping table flushing method according to claim 1, wherein, The multi-level mapping table flushing method is performed when a triggering condition is met. The triggering condition includes the table entry data of the Nth level mapping table in the cache unit being greater than a set threshold; or the triggering condition is that the user data written in a continuous write scenario exceeds a set threshold.
5. The multi-level mapping table flushing method according to claim 1, wherein, The checkpoint data is constructed based on the corresponding entries in the updated Level 1 mapping table.
6. The multi-level mapping table flushing method according to claim 1, wherein, The multi-level mapping table is a 3-level mapping table.
7. The multi-level mapping table flushing method according to claim 1, wherein, The flash memory chip supports multi-plane programming.
8. The multi-level mapping table flushing method according to any one of claims 1 to 7, wherein, The solid-state drive is a DRAM-less solid-state drive.
9. A controller for a solid-state drive, the controller performing the multi-level mapping table writing method as described in any one of claims 1 to 7.
10. A solid-state drive, comprising a controller and a storage medium composed of flash memory chips, the controller executing one or more computer instructions, wherein the computer instructions, when executed, implement the multi-level mapping table writing method as described in any one of claims 1 to 7.