A semiconductor defect identification method, apparatus, device, medium, and program product.

Abstract

The purpose of this invention is to provide a semiconductor defect identification method, apparatus, device, medium, and program product, comprising: performing a preliminary screening of multiple identified defects on a wafer based on the type of the region where the defects are located and the density of adjacent structures to obtain preliminary screening defects; performing a fine screening of the preliminary screening defects based on the spatial distribution of failed grains around the preliminary screening defects to obtain fine screening defects; inputting the feature data of the fine screening defects into a pre-built identification model to obtain the lethality rate of the fine screening defects, and determining whether the fine screening defects are fatal defects based on the lethality rate. This solution achieves comprehensive identification of fatal defects based on the physical characteristics of the defects themselves, the spatial distribution of the adjacent structures of the defects, and the multi-dimensional screening of the pre-built identification model, significantly improving the efficiency and accuracy of defect detection, and reducing or even avoiding missed or false detections of defects.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of intelligent identification technology, and in particular to a semiconductor defect identification method, apparatus, device, medium and program product. Background Technology

[0002] Killer defects in semiconductors are primarily caused by material defects, process variations (such as uneven deposition / etching), particulate contamination (metallic impurities or organic matter), photolithography alignment errors, or etching residues during the manufacturing process. These defects can directly lead to the failure of critical chip structures, such as transistors and interconnects, reducing wafer yield, increasing costs, and potentially causing reliability issues such as device leakage, short circuits, or signal anomalies.

[0003] Therefore, in the semiconductor manufacturing process, timely detection and location of critical defects is a core step in ensuring chip performance, yield, and reliability, and is crucial for cost control, technological iteration, and market competitiveness. Current technologies generally employ optical inspection techniques or electron beam analysis for defect identification. After identification, the defect morphology is manually observed to determine whether it is a critical defect, or image recognition algorithms are used to distinguish critical defects based on historical data. However, manual judgment is costly and inefficient, while image recognition algorithms can only judge based on the defect morphology. The surface morphology of a defect is not necessarily related to its actual electrical impact on the wafer, leading to a high risk of misjudgment and missed detection if relying solely on image recognition.

[0004] As semiconductor technology expands to below 3nm and incorporates new materials (such as GaN and SiC), existing solutions are struggling to meet mass production demands. Therefore, a highly accurate and efficient method for detecting and identifying critical defects is urgently needed. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor defect identification method, apparatus, device, medium, and program product. This invention achieves comprehensive identification of critical defects based on multi-dimensional screening using the defect's own physical characteristics, the spatial distribution of the defect's adjacent structures, and a pre-built identification model. This significantly improves the efficiency and accuracy of defect detection, reducing or even avoiding missed and false detections.

[0006] To address the aforementioned problems, this invention provides a semiconductor defect identification method, comprising: performing a preliminary screening of multiple identified defects on a wafer based on the type of the region where the defects are located and the density of adjacent structures to obtain preliminary screening defects; performing a fine screening of the preliminary screening defects based on the spatial distribution of failed grains around the preliminary screening defects to obtain fine screening defects; inputting the feature data of the fine screening defects into a pre-built identification model to obtain the lethality rate of the fine screening defects, and determining whether the fine screening defects are fatal defects based on the lethality rate.

[0007] In addition, in some embodiments, the region types described above include: core functional areas and non-core functional areas; the initial screening based on the region type of the defect to be identified and the density of adjacent structures includes: determining whether the defect to be identified meets a first screening condition; and taking the defect to be identified that meets the first screening condition as the defect after initial screening; wherein, the first screening condition is that the region type of the defect is a core functional area and the density of adjacent structures of the defect is greater than a first threshold.

[0008] In addition, in some embodiments, the method described above further includes: determining whether the defects after the initial screening meet the preset fine screening trigger conditions; taking the defects after the initial screening that meet any of the fine screening trigger conditions as the defects after the initial screening to be subjected to the fine screening; wherein the fine screening trigger conditions include at least any one or more of the following conditions: the defect is located in a critical process layer, the defect size is greater than the threshold of the process layer in which the defect is located, the defect shape is a preset shape, and the proportion of the overlap area between the defect and the transistor / interconnect is greater than a second threshold.

[0009] In addition, in some embodiments, the fine screening of the defects after the initial screening, based on the spatial distribution of the failed grains around the defects after the initial screening, as described above, includes: obtaining the positions of the failed grains within a preset radius centered on the defects after the initial screening; calculating the Euclidean distance between the defects after the initial screening and each failed grain within the preset radius, and selecting the smallest Euclidean distance among the calculated results as the target distance; determining whether the target distance satisfies a second screening condition, and selecting the defects after the initial screening that satisfy the second screening condition as the finely screened defects; wherein, the second screening condition is that the target distance is not greater than a third threshold.

[0010] In some embodiments, the feature data described above includes: attribute feature data and performance feature data. The attribute feature data includes at least defect size and defect type, and the performance feature data includes at least: electrical test data and chip probe test data. The step of inputting the feature data of the screened defects into a pre-built recognition model to obtain the lethality rate of the screened defects, and determining whether the screened defects are fatal based on the lethality rate, includes: determining the chip correlation degree of the screened defects based on the chip probe test data, where the chip correlation degree characterizes the impact of the screened defects on the functionality of the chips on the wafer; determining the electrical correlation degree of the screened defects based on the electrical test data, where the electrical correlation degree characterizes the impact of the screened defects on the electrical parameters of the wafer; extracting the defect size and defect type of the screened defects from the attribute feature data, inputting the defect size, defect type, electrical correlation degree, and chip correlation degree into the recognition model to calculate the lethality rate; and identifying screened defects with a lethality rate greater than a fourth threshold as fatal defects.

[0011] In addition, in some embodiments, the method described above further includes: performing FIB-SEM verification on the fatal flaw and storing the verification result, the verification result being used to indicate whether the fatal flaw is a real fatal flaw; when the verification result meets a preset update condition, adaptively updating the first screening condition or the second screening condition, and adaptively updating the identification model.

[0012] In addition, in some embodiments, adaptively updating the first or second screening condition as described above includes: associating the feature data of the fatal defect with the verification result and constructing a mini dataset; inputting the mini dataset into a pre-constructed Hofding tree model corresponding to the first and second screening conditions to automatically update the corresponding thresholds in the first or second screening conditions.

[0013] In addition, in some embodiments, the adaptive update of the recognition model as described above includes: associating the feature data of the fatal flaw with the verification result and constructing a micro dataset; and fine-tuning the model parameters in the recognition model using an online learning algorithm based on the micro dataset.

[0014] In addition, in some embodiments, the defect types described above are represented using one-hot encoding; the method described above also includes: performing FIB-SEM verification on the fatal defects, extracting defects whose verification results are not true fatal defects as misjudged defects; using a density-based clustering algorithm to cluster the defect features of the misjudged defects, and when a new data cluster different from the existing defect types appears in the clustering results, defining the new data cluster as a new defect type; assigning a new one-hot encoding to the new defect type to update the identification model.

[0015] This invention also provides a semiconductor defect identification device, comprising: a preliminary screening module for acquiring multiple identified defects to be identified on a wafer, performing preliminary screening based on the type of the region where the defects to be identified are located and the density of adjacent structures to obtain preliminary-screened defects; a fine screening module for performing fine screening on the preliminary-screened defects based on the spatial distribution of failed grains around the preliminary-screened defects to obtain fine-screened defects; and an identification module for inputting the feature data of the fine-screened defects into a pre-built identification model to obtain the lethality rate of the fine-screened defects, and determining whether the fine-screened defects are fatal defects based on the lethality rate.

[0016] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the semiconductor defect identification method as described above.

[0017] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the semiconductor defect identification method described above.

[0018] This invention also provides a computer program product, including computer instructions, which, when executed by a processor, implement the semiconductor defect identification method described above.

[0019] As described above, this invention provides a semiconductor defect identification method. It achieves comprehensive identification of critical defects through multi-dimensional screening based on defect characteristics, proximity-related structural features, and a pre-built identification model. It creatively constructs a binary screening architecture of coarse and fine screening, resulting in the unexpected effect of rapidly filtering low-risk defects and then quantifying the defect lethality rate through the identification model, significantly improving detection efficiency. In other words, this solution overcomes the limitations of single detection methods through multi-dimensional data correlation identification, and it does not require large-scale labeled data or high-cost hardware support, resulting in lower deployment costs and stronger applicability. By combining binary screening with the identification model, the efficiency and accuracy of critical defect detection and identification can be significantly improved. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0021] Figure 1 This is a flowchart illustrating a semiconductor defect identification method according to the first embodiment of the present invention. Figure 2 This is a specific flowchart of step 102 in the fourth embodiment of the present invention; Figure 3 This is a specific flowchart of step 103 in the fifth embodiment; Figure 4 This is a flowchart illustrating a semiconductor defect identification method according to the sixth embodiment of the present invention. Figure 5 This is a flowchart illustrating a semiconductor defect identification method according to the seventh embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of a semiconductor defect identification device according to the eighth embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the electronic device according to the ninth embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions of this disclosure, and to fully understand and implement the process of how this disclosure applies technical means to solve technical problems and achieve corresponding technical effects, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. The embodiments of this disclosure and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort should fall within the protection scope of this disclosure.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] The first embodiment of the present invention relates to a semiconductor defect identification method, such as... Figure 1 As shown, the specific steps include 101-103: Step 101: For the multiple identified defects on the wafer, perform a preliminary screening based on the type of the region where the defect is located and the density of the adjacent structure to obtain the preliminary screening defects.

[0025] Specifically, this solution involves a series of data preparation tasks before formal implementation, including but not limited to preparing a series of characteristic data required for semiconductor defect identification. These include directly obtainable attribute characteristic data of the defect itself, such as size, shape, type, and coordinate information; as well as relevant performance characteristic data that cannot be directly obtained but is crucial in the chip production stage and can only be obtained through specific tests or reading specific files, such as wafer GDS (Graphic Data System) files, wafer CP (Chip Probing) test data, and electrical test data. This embodiment does not impose specific limitations on these aspects.

[0026] Defects to be identified are all or some key defects already determined on the wafer. These defects can be obtained by scanning the wafer using optical inspection or electron beam inspection equipment. During scanning, the attribute characteristics of all defects to be identified, such as size, shape, type, and coordinate information, can be acquired. Then, the GDS file from the wafer design stage is read, and the boundary coordinates and range of each region type are parsed. By matching the coordinates of each defect to be identified with the region boundaries parsed from the GDS file, the region type of the defect location can be determined. Since the functional positioning of defect regions on the wafer varies, if a defect is located in a region critical to the wafer's functionality, it will likely affect the wafer's functionality.

[0027] Meanwhile, screening defects solely based on their location may lead to false positives. Even if the current area is crucial for wafer functionality, it doesn't necessarily mean that critical functional structures are damaged at the defect location. Therefore, it's necessary to verify whether critical functional structures exist around the current defect location. This embodiment uses a combination of proximity structure density and region type for verification. Specifically, proximity structure density in this embodiment refers to the degree of integration of circuit structures (critical functional structures, such as transistors and interconnects) adjacent to the defect. The determination method is as follows: Based on the circuit structure data in the GDS file, a preset analysis radius is set with each defect to be identified as the center, and the distribution density of circuit structures within the preset analysis radius is calculated as the proximity structure density. If the proximity structure density is high, it indicates that there are many circuit structures (critical functional structures) around the current defect location. In this case, the defect has a high probability of affecting wafer functionality and becoming a fatal defect; conversely, the probability of it having a real impact on wafer functionality is low.

[0028] Step 102: Based on the spatial distribution of failed grains around the defects after the initial screening, the defects after the initial screening are further screened to obtain the defects after fine screening.

[0029] After initial screening based on the type of the region containing the defect and the density of adjacent structures, a batch of defects unlikely to become fatal are eliminated, leaving the remaining defects. For these initially screened defects, the spatial distribution of surrounding failed dies is obtained. This spatial distribution is then used for further fine screening, taking into account the spatial correlation between defects and failed dies. That is, if a defect is the cause of failure of a failed die, its spatial location must be highly proximate to that failed die, situated around it; similarly, if a fatal defect exists at a specific location on the wafer, most of the surrounding dies will be failed dies. Therefore, this embodiment uses the spatial distribution of surrounding failed dies to further refine the initial screening of defects, resulting in finely screened defects. It should be noted that the spatial distribution in this embodiment can refer to a certain spatial parameter relationship between defects and failed grains. For example, the number or distribution density of failed grains within a preset radius centered on a certain defect, or the average distance between the defect and a preset number of failed grains, or the distance between the defect and the nearest failed grain. Setting corresponding thresholds for the above spatial distribution parameters can achieve fine screening.

[0030] Step 103: Input the feature data of the defects after fine screening into the pre-built recognition model to obtain the lethality rate of the defects after fine screening, and determine whether the defects after fine screening are fatal based on the lethality rate.

[0031] Specifically, after initial and fine screening, the remaining defects constitute a high-probability candidate group for fatal defects. This embodiment further quantifies their lethality rate using a pre-built identification model. The pre-built identification model takes the defect's feature data as input, calculates and outputs the lethality rate of the defect. It should be noted that this embodiment does not impose specific limitations on the method of pre-building the identification model. The identification model in this embodiment can be a logistic regression model, or it can be trained using methods such as feature engineering and maximum likelihood estimation. For example, historical wafer defect data can be collected as a training set, with each training sample containing defect feature data and a label (fatal defect or non-fatal defect). The feature data in the training set is standardized to eliminate the influence of dimensional differences on model training. The processed training data is input into the identification model, and the model parameters (weight coefficients and bias terms) are optimized using the maximum likelihood estimation method, so that the model can output the probability (i.e., lethality rate) of a defect being a fatal defect based on the input features. It should be noted that in this embodiment, lethality is essentially a quantification of the probability of a defect affecting wafer yield, so "lethality" can also be called "yield impact factor"; fatal defects refer to defects that have a critical impact on wafer yield, and can also be called "critical defects".

[0032] In summary, compared with related technologies, the embodiments of this invention achieve the identification of fatal defects through initial screening, fine screening, and the calculation of lethality rates using an identification model. An unexpected effect is that low-risk defects are quickly filtered out through dual screening, and the defect lethality rate is quantified through the identification model, significantly improving detection efficiency. That is, this solution overcomes the limitations of single detection methods through multi-dimensional data correlation identification, and it does not require large-scale labeled data or high-cost hardware support. It has lower deployment costs and stronger feasibility. By using a binary screening method combined with an identification model, the efficiency and accuracy of fatal defect detection and identification can be greatly improved, thereby increasing wafer yield.

[0033] The second embodiment of the present invention relates to a semiconductor defect identification method. This embodiment is a supplement to the foregoing embodiment, and the supplement is that step 101 in the foregoing embodiment is described in detail.

[0034] In one example, the types of areas where the defect is located include: core functional areas and non-core functional areas; In this case, the initial screening in step 101 based on the type of the region where the defect to be identified is located and the density of adjacent structures specifically includes the following steps: Determine whether the defect to be identified meets the first screening condition; designate the defect to be identified that meets the first screening condition as the initial screening defect; The first screening criterion is that the area where the defect is located is a core functional area, and the density of the adjacent structures of the defect is greater than a first threshold.

[0035] Specifically, this embodiment divides the wafer surface into a core functional area (pattern area) and a non-core functional area (dummy area) based on function. The core functional area integrates key circuit structures such as transistors, metal interconnects, and vias, and is the core area for realizing chip functions. The non-core functional area can be a pre-reserved area between chips, which only contains test structures for process monitoring and has no actual chip function; it can also be an area where effective circuits are usually not laid out due to differences in process uniformity, and defects located in this area have no substantial impact on chip yield. In actual operation, the boundary coordinates of the core functional area and the non-core functional area are first extracted from the wafer GDS file, and a global coordinate system consistent with the coordinate system of the wafer inspection equipment is established to ensure that the area attribution of each defect to be identified can be determined by coordinate matching.

[0036] Simultaneously, based on the circuit structure data in the GDS file, the proximity structure density of each defect to be identified is calculated. The specific calculation method is as follows: Using the defect as the center, an appropriate analysis radius is set according to the corresponding process node of the wafer as the basis for delineating the proximity calculation region. The analysis radius can be determined based on the process parameters under different processes, ensuring that it covers the critical range where the defect may cause physical interference. After delineating the range, image segmentation algorithms and feature extraction techniques are used to statistically analyze the total area of ​​the core functional area circuit structure within this radius. The core functional area circuit structure can include all functional structures such as transistors, metal lines, and vias. Its projected area is calculated, and the proximity structure density is determined by the quantitative result of the total area of ​​the circuit structure within the region divided by the total area of ​​the analysis region. The higher the proximity structure density, the greater the probability of short circuits, open circuits, or signal interference between the defect and the circuit.

[0037] Finally, a preliminary screening operation based on the first screening condition is performed. The specific process is as follows: For each defect to be identified, it is first compared with the region boundary in the global coordinate system through coordinate matching to determine whether its region type is a core functional area or a non-core functional area. If the determination result is a non-core functional area, it is directly eliminated; if the determination result is a core functional area, the neighboring structure density of the defect is further obtained and compared with a preset first threshold. The setting of the first threshold can be determined in combination with specific process requirements, historical defect data and yield targets, and can be dynamically adjusted according to subsequent process optimization and changes in defect type, such as 30%, 40%, 50%, etc. This embodiment does not impose specific restrictions on this. When a defect in the core functional area meets the condition that its neighboring structure density is greater than the first threshold, it meets the first screening condition and is retained as a defect after preliminary screening to enter the subsequent fine screening stage; if the neighboring structure density of a defect in the core functional area is less than or equal to the first threshold, it is directly eliminated.

[0038] The unexpected effect of this embodiment is that the screening logic is simplified by dividing the region type into two parts. At the same time, the high structural density attribute of the core functional area is combined to screen for fatal defects. While ensuring the accuracy of screening, the sample size of subsequent fine screening and model calculation is greatly reduced, and the overall efficiency of fatal defect identification is improved.

[0039] The third embodiment of the present invention relates to a semiconductor defect identification method. This embodiment is a supplement to the foregoing embodiments, and the supplement is that it performs supplementary screening on the defects after the initial screening before step 102 in the foregoing embodiments, specifically including: Determine whether the defects after the initial screening meet the preset fine screening trigger conditions; Defects that meet any of the fine screening trigger conditions after initial screening are taken as defects after initial screening to be fine screened. The fine screening triggering conditions include at least one or more of the following conditions: the defect is located in a critical process layer, the defect size is greater than the threshold of the process layer in which the defect is located, the defect shape is a preset shape, and the proportion of the overlap area between the defect and the transistor / interconnect is greater than the second threshold.

[0040] Specifically, to further focus on high-risk defects after initial screening and avoid unnecessary fine screening operations on low-risk defects, this embodiment sets fine screening trigger conditions after initial screening and before fine screening. Only defects that meet the fine screening trigger conditions will proceed to the subsequent fine screening steps. The fine screening trigger conditions in this embodiment are set based on the relationship between critical defects and the importance of the process layer, their own physical characteristics, and their degree of circuit relevance. That is, the fine screening trigger conditions include at least one or any combination of the following conditions: the defect is located in a critical process layer, the defect size is greater than the threshold of the process layer in which the defect is located, the defect shape is a preset shape, and the overlap area between the defect and the transistor / interconnect is greater than a second threshold. Among these, defects in critical process layers are more likely to cause core function failures; the size and shape of the defect directly determine its physical destructive ability to the circuit structure; and the degree of overlap between the defect and core components such as transistors and interconnects is directly related to its probability of interfering with circuit conduction and signal transmission.

[0041] Specifically, the process layer information of the defect can be determined through the layer scanning function of the defect detection equipment. This equipment can simultaneously record the process layer attribution of the defect in the vertical direction of the wafer, such as the gate oxide layer, polysilicon layer, metal interconnect layer, and via layer. During the fine screening trigger condition determination, the process layer information of the defect is compared with a preset list of critical process layers. If they match, the trigger condition of the defect being located in a critical process layer is met. Defect size and morphology data are directly output by the detection equipment. Defect size includes length, width, and height, and defect morphology is classified into specific types such as particles and scratches by image recognition algorithms based on the defect images acquired by the equipment. For different process layers, corresponding defect size thresholds are preset. These thresholds can be set based on the minimum feature size of the process layer. When the defect size is close to or exceeds the minimum feature size of the process layer, it will inevitably damage the device structure. During the determination, the key size conditions related to the process layer function in the three-dimensional dimensions of the defect are extracted and compared with the corresponding threshold for that process layer. If the defect size is greater than the threshold, the fine screening trigger condition is met.

[0042] High-risk defect patterns are pre-defined as preset patterns, such as bridging, open circuits, or missing contact holes. During the determination process, the defect pattern type obtained through an image recognition algorithm is matched against the preset pattern list. If they match, the fine screening trigger condition is met. The coordinates and range information of transistors / interconnects can be extracted from the GDS file. A spatial coordinate system relating the circuit device and the defect is established based on the extracted coordinates and physical boundaries. Based on the coordinates and size of the defect, combined with the physical boundaries of the transistors / interconnects in the GDS file, spatial geometric calculations are used to determine the percentage of the overlap area between the defect and one or more core devices relative to the total defect area, and this percentage is compared with a second threshold. The second threshold is set based on the premise that when the overlap percentage reaches a certain level, the interference of the defect on the device function is irreversible; typically, it can be 30%-50%, but this embodiment does not impose a specific limit on this.

[0043] This embodiment takes into account the different impacts of different process layers on chip functionality and sets up a variety of fine screening trigger conditions. The unexpected effect is that the complementary use of multi-dimensional fine screening trigger conditions achieves comprehensive coverage, more comprehensively captures high-risk defects in the initial screening, avoids missed detections caused by single-dimensional judgment, significantly reduces the amount of calculation in the fine screening process, and improves the overall detection efficiency.

[0044] The fourth embodiment of the present invention relates to a semiconductor defect identification method. This embodiment is a supplement to the foregoing embodiments, and the supplement lies in refining step 102, such as... Figure 2 As shown, the specific steps include the following: Step 201: Using the defects after initial screening as the center, obtain the location of the failed grains within a preset radius.

[0045] Specifically, the precise coordinate information of all failed granules is extracted. This coordinate information can be obtained from the wafer map generated by CP testing. Simultaneously, the coordinate data of defects after initial screening is retrieved. This data is synchronously output by optical inspection or electron beam inspection equipment and has been aligned with the global wafer coordinate system. Through coordinate matching, the spatial relationship between the defects after initial screening and all failures is determined. The failed granules and their position coordinates within a preset radius range centered on the defects after initial screening are determined. It should be noted that the preset radius range in this embodiment can be determined based on the influence range of fatal defects on surrounding granules in historical data; this embodiment does not impose specific limitations on this.

[0046] Step 202: Calculate the Euclidean distance between the defect after initial screening and each failed grain within the preset radius range, and select the smallest Euclidean distance in the calculation results as the target distance.

[0047] Specifically, for each defect after initial screening, all failed granules within its preset radius are traversed, and the Euclidean distance between the defect coordinates and the center coordinates of each individual failed granule is calculated. The calculation logic follows the distance formula between two points in a plane. After calculating the distances between all failed granules and the defect, the distance with the smallest value is selected as the target distance for that defect. The core basis for selecting the minimum distance is: if the defect is a fatal defect, it must be the direct cause of the abnormal function of a specific failed granule, and this failed granule is most likely the failed granule closest to the defect in spatial location. For failed granules beyond a certain distance, the cause of failure is more likely to be related to other defects and has no direct causal relationship with the current defect. Therefore, the target distance can maximize the correlation between the defect and the failure event.

[0048] Step 203: Determine whether the target distance meets the second screening condition, and use the defects that meet the second screening condition after initial screening as the defects after fine screening; The second screening criterion is that the target distance is not greater than the third threshold.

[0049] Specifically, after determining the target distance, the target distance is compared with a third threshold. Defects that are initially screened with a target distance less than or equal to the third threshold are identified as defects after fine screening. The setting of the third threshold is determined based on wafer fabrication process, die size, process characteristics, and historical failure data, etc., and this embodiment does not impose specific limitations.

[0050] This embodiment provides a mechanism for quantifying Euclidean distance and screening for minimum target distance, establishing a correlation between defects and failed grains. An unexpected effect is that it avoids missed detections or misjudgments caused by fuzzy spatial correlation judgments. The entire calculation and judgment process has low computational load and high execution efficiency, further narrowing the range of candidate fatal defects while ensuring the relevance and accuracy of subsequent model evaluation.

[0051] The fifth embodiment of the present invention relates to a semiconductor defect identification method. This embodiment is a supplement to the foregoing embodiments, and the supplement lies in refining the aforementioned step 103, such as... Figure 3 As shown, this embodiment specifically includes the following steps: In this embodiment, the feature data includes: attribute feature data and performance feature data. The attribute feature data includes at least defect size and defect type, and the performance feature data includes at least: electrical test data and chip probe test data.

[0052] Specifically, CP (chip probe) test data is obtained at the wafer stage to verify whether the manufactured chip can actually function and whether its basic parameters meet the standards. This data is presented in the form of a wafer map and is the core of yield analysis. By analyzing the spatial distribution patterns of failed chips, problems with the process equipment, process steps, or photomasks can be located. Electrical test data is obtained after packaging, under final application conditions, to verify whether the chip's performance meets design specifications, such as speed and power consumption.

[0053] Based on this, step 301: Determine the chip correlation degree of defects after fine screening based on the chip probe test data of the wafer. The chip correlation degree is used to characterize the impact of defects after fine screening on the function of chips on the wafer.

[0054] Specifically, chip correlation is a core indicator for quantifying the impact of defects on chip functionality. It is determined based on wafer CP test data, which records the functional verification results and all electrical parameters of each die, serving as a direct basis for judging whether a die has failed. Chip correlation can be determined as follows: based on the target distance determined in the fine screening process, identify the failed die most closely associated with the defect; extract the CP test report of this associated failed die to clarify its failure type, such as logic function failure, electrical parameter exceeding limits, I / O interface failure, etc., and comprehensively determine the correlation by combining the physical characteristics and repairability of the defect. This embodiment does not impose specific limitations on this.

[0055] Step 302: Determine the electrical correlation degree of defects after fine screening based on the electrical test data of the wafer. The electrical correlation degree is used to characterize the influence of defects after fine screening on the electrical parameters of the wafer.

[0056] Specifically, electrical correlation is a core indicator for quantifying the impact of defects on wafer electrical parameters. It is determined based on wafer electrical test data, which records key electrical parameters of the test structure in the core functional area of ​​the wafer, such as transistor threshold voltage V. th Saturation drain current I Dsat Interconnection resistance R w Gate leakage current I GSS These parameters are the direct basis for evaluating process stability and device performance.

[0057] Electrical correlation can be obtained through the following process: Match the coordinates of the defect after fine screening with the coordinates of the test structure in the electrical test using the wafer coordinate system to locate the test structure corresponding to the defect area; extract the actual electrical parameter values ​​of the correlated test structure, and simultaneously retrieve the average electrical parameter value of the test structure corresponding to the defect-free area in the same batch of wafers as the benchmark value; for each correlated electrical parameter, calculate the parameter deviation between the actual value and the benchmark value, and then, according to the influence weight of each parameter on chip performance, perform a weighted sum of all parameter deviations to obtain the electrical correlation of the defect. The larger the electrical correlation value, the greater the influence of the defect on the electrical parameter.

[0058] It should be noted that there is no strict order of execution logic or timing between steps 301 and 302 in this embodiment. They can be performed sequentially or simultaneously. This embodiment does not impose any specific restrictions.

[0059] Step 303: Extract the defect size and defect type of the finely screened defects from the attribute feature data, input the defect size, defect type, electrical correlation degree and chip correlation degree into the recognition model, and calculate the lethality rate.

[0060] Specifically, considering that the essence of a fatal defect is that its physical characteristics are sufficient to damage the circuit structure and actually affect the chip's electrical properties and functions, it is necessary to combine the physical attributes of the defect itself with the actual impact reflected in the test data to avoid misjudgment or missed judgment caused by a single physical feature. The pre-built recognition model has been trained using historical defect data, and the core parameters of the model are the weight coefficients and bias terms of each input feature. Among them, the magnitude of the weight coefficient reflects the degree of influence of the feature on the fatality rate. The four feature data of normalized defect size, encoded defect type, electrical correlation, and chip correlation are simultaneously input into the pre-trained recognition model. The recognition model performs corresponding calculations according to the preset weight coefficients and calculation formulas, and maps the results to the [0,1] interval through the recognition's Sigmoid function. The final output value is the fatality rate of the refined defect.

[0061] Step 304: Defects with a lethality rate greater than the fourth threshold after fine screening are identified as fatal defects.

[0062] Specifically, in application, a fourth threshold can be set according to the yield target and process tolerance requirements; this embodiment does not impose specific limitations. If the lethality rate of defects after fine screening is greater than the fourth threshold, it is determined to be a fatal defect; if it is less than or equal to the threshold, it is determined to be a non-fatal defect. This embodiment does not impose specific limitations.

[0063] In one example, the recognition model is represented by the following formula: KPI = α × (S size )+β×(T type )+γ×(Eimpact )+δ×(C cp ); Specifically, the KPI is the lethality rate, S size T represents the influence value of defect size. type E represents the impact value of the defect type. impact For electrical correlation degree, C cp The chip correlation coefficient is represented by α, β, γ, and δ, which are preset weighting coefficients.

[0064] Among them, S size = min (|d′|) p , 1), d′=[d x ,d y ,d z ] / d critical , [d x ,d y ,d z ] is the size vector of defect d in three-dimensional space, d x The maximum length or equivalent diameter of defect d in the X direction (typically a horizontal direction in the wafer plane); d y Let d be the maximum length or equivalent diameter of the defect in the Y direction (another horizontal direction perpendicular to X on the wafer plane). z Let d be the depth of the defect in the Z direction (the height direction perpendicular to the wafer surface); d critical The critical size refers to the smallest defect size at a given location that can cause circuit malfunction. A defect of the same size will have different critical sizes depending on whether it falls within the core functional area of ​​a dense pattern or a sparse pattern. Therefore, this embodiment can dynamically calculate the critical size (d) at different locations based on GDS layout information. critical 。 ‖·‖ p Read as "p-norm," it is a mathematical operation that converts a vector into a scalar, measuring the "size" or "length" of the vector. For example, for an n-dimensional vector x = (x1, x2, ..., x... n Its p-norm is defined as: ||x|| p = (|x1| p +|x2| p +…+|x n | p ) ^ (1 / p), where p≥1, |x i | represents the absolute value of each component of the vector (i∈[1,n]). In this embodiment, p=2, that is, this embodiment uses the 2-norm (Euclidean norm) to calculate ‖d′‖. p ;

[0065] min(‖d′‖ p,1) is the minimum value function, used to reduce S size The result is restricted to the interval [0,1], if ||d′|| p If S is greater than 1 size Take 1, if ‖d′‖ p If S is less than or equal to 1, then size Take |d′| p (Actual value).

[0066] T type = ;in, For defect types represented using one-hot encoding, a method that converts discrete categorical variables into binary vector representations, one-hot encoding uses a binary vector of length n (where each element is either 0 or 1) to represent the category to which the current sample belongs. In this vector: only one element is 1, representing the current category; all other elements are 0. In this embodiment, W... type ∈{0,1}^n, that is, if the defect belongs to the i-th type (i ranges from 1 to n), then W type The i-th component is 1, and all other components are 0. Assume there are 4 defect types (n=4): type 1, 2, 3, and 4. Their one-hot encodings are as follows: Type 1: [1,0,0,0]; Type 2: [0,1,0,0]; Type 3: [0,0,1,0]; Type 4: [0,0,0,1]; Let k represent the vector representation of the defect type corresponding to the i-th type of defect; k is the influence rate (influence rate on yield) corresponding to each defect type, represented as an n-dimensional vector, where the value of n is the same as the number of defect types. For example, k = [a, b, c, d], where each component corresponds to the influence rate of a defect type: a is the influence rate of the first type of defect, b is the influence rate of the second type of defect, c is the influence rate of the third type of defect, and d is the influence rate of the fourth type of defect. It should be noted that the influence rates corresponding to each defect type in this embodiment are obtained in advance through experiments, and this embodiment does not impose specific limitations on them.

[0067] In another example, the electrical correlation degree is calculated using the following formula:

[0068] Where, ΔP i Let ΔT be the influence value of the defects after fine screening on the i-th electrical parameter. i The maximum allowable tolerance for the i-th electrical parameter is defined by the design specifications; f i Let ΔP be the weight of the i-th electrical parameter; if ΔP i >ΔT i , champ[0,1] takes 1, otherwise it takes 0.

[0069] Here, champ is a comparison logic (ΔP) i >ΔT i The generated binary status code: champ set to 1 indicates ΔP i >ΔT i The condition is met; champ being 0 indicates ΔP i >ΔT i The conditions are not met.

[0070] Specifically, ΔP i The essence is to quantify the "degree of damage" a defect causes to a certain electrical parameter. It is a systems engineering approach that combines field measurements, simulations, and knowledge bases. Its determination method is as follows: Method 1: Spatial comparison method based on measured data.

[0071] When the chip containing the defect or a neighboring chip has corresponding CP test data, the comparison is performed directly.

[0072] For example, considering the effects of parameter drift, such as threshold voltage and quiescent supply current (IDDQ), calculate: ΔP i =|P measured -P nominal |,P measured This refers to the actual measured value of the chip's parameters; P nominal This refers to the design standard value for the product or the average parameter value of all normal chips on the wafer. For example, if the chip containing defect A has an IDDQ of 20nA, while the specification limit is 2nA, then ΔP... i =18nA.

[0073] Method 2: Prediction method based on simulation model Simulation prediction is used when defects are located on chips that are not completely failed, or when it is necessary to assess their potential risks.

[0074] Electrical modeling of defects: Transforming physical defects into components in circuit simulation models.

[0075] 1. Perform simulation: Insert the defect model into the SPICE (Simulation Program with Integrated Circuit Emphasis) circuit netlist or parasitic parameter extraction file for that region, and rerun the circuit simulation (such as transient analysis or DC analysis).

[0076] 2. Obtain ΔP i : ΔP i =|P defect -P normal|, where P defect P represents the actual measured value of the parameter. normal These are simulation values.

[0077] For example, in a simulation, a 5kΩ bridging resistor might increase the path delay from 1.0ns to 1.15ns, then ΔP i =0.15ns.

[0078] Method 3: Matching method based on historical knowledge base A "defect-impact" knowledge base is built based on historical data. When a new defect is encountered, the system searches the knowledge base for historical defects with similar characteristics (same level, same type, similar size). The average ΔP calculated from these historical defects is then directly used. i As an estimate of new defects.

[0079] In another example, chip correlation C cp It is calculated using the following formula: C cp =(S physical S logical ) (1 R redundancy ) Among them, S physical The physical relevance score is determined based on whether the defects, after screening, are located within the critical path layout area, and takes a value of 0 or 1; S logical The logical relevance score is determined based on whether the defects after screening cause the critical path logic to fail, and the value is either 0 or 1; R redundancy The redundancy design repair probability is set to a value between 0 and 1, determined based on the chip-based physical design information.

[0080] Specifically, S physical With S logical Both can be determined based on the GDS file and information from the CP test. redundancy The probability value represents the likelihood that the current defect can be successfully bypassed or repaired by the existing redundancy design mechanisms on the chip. The higher the probability, the lower the actual "fatal" risk of this defect.

[0081] The probability of redundancy design repair R redundancy A comprehensive evaluation is performed based on the chip's physical design information and the specific context of its defects. Its computational core relies on two aspects: 1. Redundancy capacity assessment: Based on the test history, calculate the proportion of remaining available redundant resources in the redundancy domain where the defect is located.

[0082] 2. Defect repairability assessment: Based on the physical location and type of the defect, determine whether it falls within the replaceable range of the redundancy mechanism.

[0083] The built-in rule engine maps the above evaluation results to probability values ​​between 0 and 1. A higher value indicates a higher probability that the defect will be successfully repaired, and its correlation C with the current electrical failure is also higher. cp Then it will decrease accordingly.

[0084] This embodiment achieves a comprehensive evaluation of physical and electrical screening by fusing four multi-dimensional features. The unexpected effect is that it greatly improves the accuracy of lethality calculation and can adapt to the wafer inspection requirements of different processes, further improving the accuracy and reliability of fatal defect identification.

[0085] The sixth embodiment of the present invention relates to a semiconductor defect identification method. This embodiment is a supplement to the foregoing embodiments, and the supplement lies in expanding the content after identifying fatal defects, such as... Figure 4 As shown, it specifically includes: Step 401: Perform FIB-SEM verification on the fatal flaw and store the verification results. The verification results are used to indicate whether the fatal flaw is a true fatal flaw.

[0086] Step 402: When the verification result meets the preset update conditions, adaptively update the first screening condition or the second screening condition, and adaptively update the recognition model.

[0087] Among them, focused ion beam scanning electron microscopy (FIB-SEM) is a core device in the semiconductor field for verifying the physical morphology of defects and circuit damage. It can directly confirm whether a defect actually causes damage to the circuit structure, i.e., whether it is a true fatal defect. The system continuously accumulates verification results and adaptively updates the first or second screening conditions and the identification model when the verification results meet preset update conditions. The preset update conditions can be: 1. Deviation rate threshold condition: statistically analyzing the false positive rate or false negative rate of N consecutive verification samples; 2. When the number of newly added valid samples in the verification result database reaches a preset threshold (e.g., 200), an update is triggered. This embodiment does not impose specific limitations on the specific preset update conditions.

[0088] In one example, adaptive updates to either the first or second filter criterion include: The feature data of the fatal flaws are correlated with the verification results to construct a mini dataset; the mini dataset is then input into the Hofding tree algorithm to automatically update the corresponding thresholds in the first or second screening criteria.

[0089] Specifically, a dedicated micro-dataset for verification is established based on the FIB-SEM verification results. This micro-dataset encompasses feature information directly related to the screening criteria and model parameters, including defect feature data (attribute feature data and performance feature data), parameters associated with each screening (such as neighboring structure density and distance to the second target), the results of each screening, the lethality rate output by the identification model, the FIB-SEM verification results (true fatal defects / non-true fatal defects), and associated electrical test data and CP test data. The FIB-SEM verification results are then converted into labels recognizable by the algorithm: true fatal defects are labeled as 1, and falsely identified fatal defects (non-true fatal defects) are labeled as 0.

[0090] For each of the first and second screening criteria, an independent Hoeffding Tree model is constructed. The completed mini-dataset is then input into the corresponding Hoeffding Tree model one by one, according to the order in which the samples were generated. The algorithm dynamically finds the optimal decision boundary by calculating the information gain under different threshold divisions. For example, for the neighboring structure density feature, the algorithm iterates through all values ​​of this feature in the mini-dataset, calculates the information gain for each value as a threshold, and the value with the largest information gain is selected as the candidate threshold. The final updated threshold is determined by combining manually set constraints on the candidate thresholds.

[0091] It should be noted that the solution in this embodiment is also applicable when the first and second screening conditions are determined for the first time. Historical data can be used as a mini dataset to optimize the initialized Hoeffding Tree model.

[0092] In another example, adaptive updates to the recognition model include: Correlate the feature data of fatal defects with the verification results and construct a mini dataset; Based on a miniature dataset, an online learning algorithm is used to fine-tune the model parameters in the recognition model.

[0093] Specifically, the model parameters in this embodiment identify the preset weight coefficients of the identification model. This refers to using the defect size weight α, defect type weight β, electrical correlation weight γ, and chip correlation weight δ of the currently used identification model as initial parameters for online learning. Samples from the micro-dataset are input into the online learning algorithm in a random order, and the weight coefficients are iteratively optimized item by item. Similarly, this embodiment also applies to the process of initially determining the preset weight coefficients. Historical data is used as the micro-dataset input into the initialized identification model, and the preset weight coefficients are obtained through optimization by the online learning algorithm.

[0094] An unexpected effect of this embodiment is that the identification results are verified, and the threshold and weight are updated and fine-tuned based on the verification results. No manual intervention is required throughout the process, and the adaptive update of the entire process is achieved, which greatly improves the adaptability of the solution to different process technologies.

[0095] The seventh embodiment of this invention relates to a semiconductor defect identification method. This embodiment supplements the foregoing embodiments by providing a mechanism for identifying and updating novel defect types hidden within falsely identified defects, such as... Figure 5 As shown, it includes the following steps: Step 501: Perform FIB-SEM verification on fatal defects and extract defects that are not true fatal defects as false defects.

[0096] Specifically, FIB-SEM verification is performed on critical defects to obtain verification results. Defects that are not considered true critical defects are identified, and full-dimensional feature data is extracted for each misjudged defect, ensuring that the features cover the defect's physical attributes, spatial attributes, and associated test data. The extracted feature data is then standardized to adapt it to the input requirements of density-based clustering algorithms.

[0097] Step 502: Use a density-based clustering algorithm to cluster the defect features of misjudged defects. When a new data cluster that is different from the existing preset defect type appears in the clustering results, the new data cluster is defined as a new defect type.

[0098] Specifically, the preprocessed misjudged defect feature data is input into a density-based clustering algorithm. After performing the clustering operation, the data clusters in the clustering results are analyzed in detail. In this embodiment, the density-based clustering algorithm can be the DBSCAN (Density-Based Spatial Clustering of Application with Noise) algorithm. First, the feature similarity between each cluster and the original preset defect types is calculated: using the cosine similarity formula, the similarity between the feature center of the new cluster (the mean vector of all sample features within the cluster) and the feature center of each preset defect type is calculated, and a similarity threshold is set; if the feature similarity between a cluster and all existing defect types is less than the similarity threshold, then the cluster is determined to be a "new data cluster different from the existing defect types" and is defined as a new defect type.

[0099] Step 503: Assign a new one-hot code to the new defect type to update the identification model.

[0100] Specifically, based on the commonalities of cluster features and FIB-SEM verification images, new defect types are given clear names and attribute descriptions. For example, "metal layer micro-void cluster" is defined as "size 0.4-0.6nm, located in metal interconnect layer M2 / M3, with a circular depression shape and no risk of circuit structure damage," ensuring that process engineers can intuitively understand its physical characteristics and risk level. One-hot encoding allocation: The defect type input item of the identification model is updated using one-hot encoding. For example, if there are N preset defect types, the corresponding one-hot encoding is an N-dimensional vector (such as type A as [1,0,0,...,0], type B as [0,1,0,...,0]). A (N+1)-dimensional one-hot vector is assigned to the new defect type, where only the dimension corresponding to the new type is 1, and the other dimensions are 0, encoded as [0,0,...,1]. The input layer feature dimension of the identification model is updated synchronously, expanding the input dimension of the defect type feature from N dimensions to (N+1) dimensions, ensuring that the model can receive the new encoding and perform effective calculations.

[0101] In addition, the defect data corresponding to the new defect type can be used as an updated dataset. This updated dataset is then input into the Hoeffding Tree model to update the first and / or second selection criteria. Specifically, the update process is as follows: all samples within the cluster corresponding to the new defect type are used as the updated dataset, with each sample associated with complete information. The updated dataset is then input separately into the Hoeffding Tree model corresponding to the first selection criterion, or separately into the Hoeffding Tree model corresponding to the second selection criterion; or simultaneously, the updated dataset is input separately into the Hoeffding Tree model corresponding to either the first or second selection criterion to update the first or second selection criteria. The process of updating the first or second selection criteria using the Hoeffding Tree algorithm is similar to that described in the fifth embodiment above, and will not be repeated here.

[0102] This embodiment incorporates the adaptation of new defect types into the update logic. An unexpected effect is that the entire fatal defect identification method can not only fine-tune parameters to adapt to changes in the characteristics of existing defects, but also actively expand the coverage of defect types, greatly improving the stability and accuracy of the method in long-term process iteration, and realizing real-time protection and preventive control of wafer yield.

[0103] The eighth embodiment of the present invention relates to a semiconductor defect identification device, such as... Figure 6 As shown, it includes: The initial screening module 601 is used to acquire multiple identified defects on the wafer, and to perform initial screening based on the type of the region where the defect is located and the density of the adjacent structure to obtain the defects after initial screening. The fine screening module 602 is used to fine screen the defects after the initial screening based on the spatial distribution of the failed grains around the defects after the initial screening, and obtain the fine-screened defects. The identification module 603 is used to input the feature data of the defects after fine screening into the pre-built identification model, obtain the lethality rate of the defects after fine screening, and determine whether the defects after fine screening are fatal based on the lethality rate.

[0104] Specifically, the initial screening module 601 acquires multiple defects to be identified and performs initial screening based on the type of the region where the defect is located and the density of adjacent structures, resulting in pre-screened defects. The relevant data of the pre-screened defects is then transmitted to the fine screening module 602. The fine screening module 602 performs fine screening based on the spatial distribution of failed grains around the pre-screened defects, resulting in finely screened defects, and transmits the information of these finely screened defects to the identification module 603. The identification module 603 inputs the feature data of the finely screened defects into a pre-built identification model and further determines whether the defect is a fatal defect based on the lethality rate result output by the model.

[0105] In addition, the semiconductor defect identification device of this embodiment also includes a data acquisition module, which is used to acquire all defects to be identified and their characteristic data, wafer GDS (Graphic Data System) files and wafer CP (Chip Probing) test data, thereby providing data support for the subsequent preliminary screening module 601.

[0106] The semiconductor defect identification device of this embodiment also includes an adaptive update module, which is used to perform FIB-SEM verification on the fatal defects determined by the identification module 603 and store the verification results. The verification results are used to indicate whether the fatal defect is a real fatal defect. When the verification results meet the preset update conditions, the first screening condition or the second screening condition is adaptively updated, and the identification model is adaptively updated.

[0107] In this embodiment, the adaptive update module is also used to perform FIB-SEM verification on the fatal defects determined by the identification module 603, extract defects that are not true fatal defects as misjudged defects; use the DBSCAN algorithm to cluster the defect features of misjudged defects, and when a new data cluster with a different defect type appears in the clustering result, the new data cluster is defined as a new defect type; and a new one-hot code is assigned to the new defect type to update the identification model.

[0108] In summary, it is not difficult to see that this embodiment is a device embodiment corresponding to the aforementioned method embodiments. The steps and implementation details described in the above method embodiments are still applicable in this embodiment, and will not be repeated here.

[0109] The ninth embodiment of the present invention relates to an electronic device, such as... Figure 7 As shown, it includes at least one processor 702; and a memory 701 communicatively connected to at least one processor 702; wherein the memory 701 stores instructions executable by at least one processor 702, the instructions being executed by at least one processor 702 to enable at least one processor 702 to perform any of the above method embodiments.

[0110] The memory 701 and processor 702 are connected via a bus, which can include any number of interconnecting buses and bridges. The bus connects various circuits of one or more processors 702 and memory 701. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 702 is transmitted over a wireless medium via an antenna, which further receives data and transmits it to processor 702.

[0111] The processor 702 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory 701 can be used to store data used by the processor 702 during operation.

[0112] The tenth embodiment of the present invention relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements any of the above-described method embodiments.

[0113] The eleventh embodiment of the present invention relates to a computer program product, including computer instructions that, when executed by a processor, implement any of the above-described method embodiments.

[0114] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0115] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0116] While the embodiments disclosed herein are as described above, the foregoing content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope of this disclosure; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor defect identification method, characterized in that, The method includes: For multiple identified defects on the wafer, a preliminary screening is performed based on the type of the region where each defect is located and the density of the adjacent structures to obtain the preliminary screening defects. Based on the spatial distribution of the failed grains around the defects after the initial screening, the defects after the initial screening are further screened to obtain the finely screened defects. The defect size and defect type of the defects after fine screening are obtained as attribute feature data, and the chip probe test data and electrical test data of the defects after fine screening are obtained as performance feature data. The chip correlation degree of the defects after screening is determined based on the chip probe test data of the wafer, and the chip correlation degree is used to characterize the impact of the defects after screening on the function of the chips on the wafer; the electrical correlation degree of the defects after screening is determined based on the electrical test data of the wafer, and the electrical correlation degree is used to characterize the impact of the defects after screening on the electrical parameters of the wafer. The defect size, defect type, electrical correlation degree, and chip correlation degree are input into the identification model to calculate the lethality rate; the finely screened defects with a lethality rate greater than the fourth threshold are identified as fatal defects. The lethality rate is the probability of a defect affecting wafer yield; the fatal defect refers to a defect that has a critical impact on wafer yield.

2. The method according to claim 1, characterized in that, The area types include: core functional areas and non-core functional areas; The initial screening based on the type of the region where the defect to be identified is located and the density of adjacent structures includes: Determine whether the defect to be identified meets the first screening condition; The defects to be identified that meet the first screening criteria are taken as the initial screening defects. The first screening condition is that the area where the defect is located is a core functional area, and the density of the adjacent structures of the defect is greater than a first threshold.

3. The method according to claim 1, characterized in that, The method further includes: Determine whether the defects after the initial screening meet the preset fine screening trigger conditions; The defects after the initial screening that satisfy any of the fine screening trigger conditions are taken as the defects after the initial screening to be subjected to the fine screening. The fine screening triggering conditions include at least one or more of the following conditions: the defect is located in a critical process layer, the defect size is greater than the threshold of the process layer in which the defect is located, the defect shape is a preset shape, and the proportion of the overlap area between the defect and the transistor / interconnect is greater than a second threshold.

4. The method according to claim 1, characterized in that, The process of refining the defects after the initial screening based on the spatial distribution of the failed grains around the defects includes: Using the initial screening defect as the center, obtain the location of the failed grains within a preset radius; Calculate the Euclidean distance between the initial screening defect and each failed grain within the preset radius range, and select the smallest Euclidean distance in the calculation results as the target distance; Determine whether the target distance meets the second screening condition, and use the initial screening defect that meets the second screening condition as the fine screening defect; The second filtering condition is that the target distance is not greater than a third threshold.

5. The method according to claim 2 or 4, characterized in that, The method further includes: The fatal flaw is verified by FIB-SEM and the verification result is stored. The verification result is used to indicate whether the fatal flaw is a true fatal flaw. When the verification result meets the preset update conditions, the first screening condition or the second screening condition is adaptively updated, and the recognition model is also adaptively updated.

6. The method according to claim 5, characterized in that, Adaptive updates to the first or second filtering criteria include: The feature data of the fatal flaw and the verification results are correlated to construct a mini dataset; The micro dataset is input into a pre-built Hofdinger tree model corresponding to the first and second screening conditions to automatically update the corresponding thresholds in the first or second screening conditions.

7. The method according to claim 5, characterized in that, Adaptive updating of the recognition model includes: The feature data of the fatal flaw and the verification results are correlated to construct a mini dataset; Based on the aforementioned micro dataset, online learning algorithms are used to fine-tune the model parameters in the recognition model.

8. The method according to claim 5, characterized in that, The defect type is represented using one-hot encoding. The method further includes: The fatal defects are verified by FIB-SEM, and defects whose verification results are not true fatal defects are extracted as false defects. A density-based clustering algorithm is used to cluster the defect features of the misjudged defects. When a new data cluster that is different from the existing defect types appears in the clustering results, the new data cluster is defined as a new defect type. A new one-hot code is assigned to the new defect type to update the identification model.

9. A semiconductor defect identification device, characterized in that, include: The initial screening module is used to acquire multiple identified defects on the wafer, and to perform initial screening based on the type of the region where each defect is located and the density of the adjacent structures to obtain the defects after initial screening. The fine screening module is used to perform fine screening on the defects after the initial screening based on the spatial distribution of the failed grains around the defects after the initial screening, so as to obtain the finely screened defects. The identification module is used to acquire the defect size and defect type of the finely screened defects as attribute feature data, and to acquire the chip probe test data and electrical test data of the finely screened defects as performance feature data; and to determine the chip correlation degree of the finely screened defects based on the chip probe test data of the wafer, wherein the chip correlation degree is used to characterize the impact of the finely screened defects on the function of the chips on the wafer. The electrical correlation degree of the defects after fine screening is determined based on the electrical test data of the wafer, and the electrical correlation degree is used to characterize the influence of the defects after fine screening on the electrical parameters of the wafer. The defect size, defect type, electrical correlation degree, and chip correlation degree are input into the identification model to calculate the lethality rate; the finely screened defects with a lethality rate greater than the fourth threshold are identified as fatal defects. The lethality rate is the probability of a defect affecting wafer yield; the fatal defect refers to a defect that has a critical impact on wafer yield.

10. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the semiconductor defect identification method as described in any one of claims 1 to 8.

11. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the semiconductor defect identification method as described in any one of claims 1 to 8.

12. A computer program product, characterized in that, It includes computer instructions that, when executed by a processor, implement the semiconductor defect identification method as described in any one of claims 1 to 8.

Images