In-vehicle computing system and vehicle

Abstract

The application relates to the technical field of vehicles, in particular to a vehicle-mounted computing system and a vehicle, wherein the system comprises: at least one main computing module, which is used for executing a target computing task; a pre-fault prediction module, the pre-fault prediction module comprising a pre-fault prediction model, the pre-fault prediction model being used for predicting a fault time interval of the main computing module; and a scheduling module, which is used for triggering a corresponding fault-tolerant strategy according to the fault time interval and executing the fault-tolerant strategy. Therefore, the problems of long fault response time and the like in the prior art are solved.

Description

Technical Field

[0001] This application relates to the field of vehicle technology, and in particular to an in-vehicle computing system and a vehicle. Background Technology

[0002] As autonomous driving advances to Level 4 and above, the demands for real-time perception, multi-sensor fusion, and dynamic decision-making in vehicle computing have increased significantly. Neuromorphic chips, with their brain-like architecture, low power consumption, and real-time processing advantages, have been widely adopted. Since autonomous driving is directly related to driver and passenger safety, and neuromorphic chips are the core for processing multi-source sensor data, their stability and reliability directly affect the accuracy of decision-making. Failures could lead to serious accidents such as collisions and loss of control. Therefore, accurate and timely fault monitoring of in-vehicle neuromorphic chips is essential.

[0003] However, the fault detection of neural chips in related technologies mainly relies on passive detection mechanisms such as hardware CRC (Cyclic Redundancy Check) verification. That is, the verification and processing of anomalies can only be carried out when erroneous data is generated during a fault, resulting in a long fault response time, which cannot meet the requirements of fault response speed in emergency scenarios of autonomous driving. Summary of the Invention This application provides an in-vehicle computing system and a vehicle to solve problems such as long fault response time in related technologies.

[0004] The first aspect of this application provides an in-vehicle computing system, including: at least one main computing module for executing a target computing task; a pre-fault prediction module, which includes a pre-fault prediction model and predicts the fault time interval of the main computing module based on the pre-fault prediction model; and a scheduling module for triggering a corresponding fault tolerance strategy according to the fault time interval and executing the fault tolerance strategy.

[0005] Optionally, in one embodiment of this application, the main computing module is composed of multiple biomimetic synapses, wherein the biomimetic synapse includes: a substrate; a graphene bottom gate disposed on the substrate, and a top gate covering the graphene bottom gate, wherein a biosynaptic interface is disposed on the outer side of the top gate for receiving input voltage from an external sensor; a molybdenum disulfide channel layer disposed on the top gate, and an ion gel layer covering the molybdenum disulfide channel layer.

[0006] Optionally, in one embodiment of this application, the top gate and the graphene bottom gate form a dual-gate control structure to simulate calcium ion channels and adjust the conductivity of the molybdenum disulfide channel layer according to the synaptic dynamics equation; the molybdenum disulfide channel layer and the ion gel layer constitute a heterojunction to adjust the weights through changes in conductivity and realize the analog domain multiplication and addition operation of the input voltage pulse and the weights.

[0007] Optionally, in one embodiment of this application, the synaptic dynamics equation is: ; in, The change in weight. The calcium ion diffusion coefficient is... This refers to the calcium ion concentration. Input voltage, This is the output voltage after biomimetic synapse processing.

[0008] Optionally, in one embodiment of this application, the bionic synapse is further used to: adjust the short-term enhancement factor based on the computational load of the target computing task.

[0009] Optionally, in one embodiment of this application, the pre-fault prediction module is further configured to: obtain the equivalent series resistance value, thermal noise spectrum and temperature change rate of the electrolytic capacitor of the main calculation module; input the equivalent series resistance value, thermal noise spectrum and temperature change rate of the electrolytic capacitor into the pre-fault prediction model, and the pre-fault prediction model outputs the predicted fault time interval.

[0010] Optionally, in one embodiment of this application, the in-vehicle computing system further includes: at least one backup computing module, wherein the backup computing module is composed of a plurality of bionic synapses.

[0011] Optionally, in one embodiment of this application, the scheduling module is further configured to: if the fault time interval is greater than a first preset duration, then the fault tolerance strategy is the first strategy; if the fault time interval is greater than a second preset duration and less than or equal to the first preset duration, then the fault tolerance strategy is the second strategy; if the fault time interval is less than or equal to the second preset duration, then the fault tolerance strategy is the third strategy.

[0012] Optionally, in one embodiment of this application, the first strategy is to save the bionic synaptic state difference at target intervals; the second strategy is to copy the target computing task to the backup computing module, and the main computing module and the backup computing module execute the target computing task synchronously; the third strategy is to use the target hardware hot-swap protocol to switch the hardware interface connected to the main computing module to the backup computing module, wherein the backup computing module executes the target computing task and the main computing module is disabled.

[0013] A second aspect of this application provides a vehicle including an on-board computing system as described in the above embodiments.

[0014] Therefore, this application has at least the following beneficial effects: This application provides an in-vehicle computing system comprising a main computing module, a fault prediction module, and a scheduling module. The fault prediction module can predict the fault interval of the main computing module based on a fault prediction model. The scheduling module triggers corresponding fault-tolerant strategies based on the fault interval, proactively implementing fault prevention and fault-tolerant processing, reducing fault response time, improving fault handling efficiency, and avoiding task interruption caused by sudden failure of the main computing module. This solves the technical problems of long fault response times in related technologies.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of an in-vehicle computing system provided according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a bionic synapse provided according to an embodiment of this application; Figure 3 This is a flowchart of a pre-fault prediction method provided according to an embodiment of this application; Figure 4 A timing diagram for providing a dynamic fault-tolerant mechanism according to embodiments of this application. Detailed Implementation

[0017] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0018] Before describing the solution of this application, let me first introduce the relevant technologies and existing problems of this application.

[0019] 1. Energy efficiency bottleneck.

[0020] Neuromorphic chips in related technologies (such as Intel Loihi) still consume more than 5W per core, which cannot meet the energy efficiency requirements of automotive sensor fusion scenarios. 2. Passive fault-tolerant delay.

[0021] In related technologies, fault detection relies on hardware CRC check, and the fault response time is >10ms (ASIL-D requires ≤1ms). 3. Insufficient utilization of biological characteristics.

[0022] The related technologies do not simulate the STP (Short-Term Plasticity) characteristics of biological synapses, and therefore cannot dynamically adapt to sudden computational loads.

[0023] Furthermore, the relevant technologies lack hardware-level simulation of biological neural calcium ion channel mechanisms; no pre-fault prediction model has been established; and the coordinated control of dynamic voltage regulation and synaptic weight update is missing.

[0024] To this end, this application provides an in-vehicle computing system, including a main computing module, a pre-fault prediction module, and a scheduling module. The pre-fault prediction module can predict the fault time interval of the main computing module based on the pre-fault prediction model. The scheduling module triggers the corresponding fault tolerance strategy based on the fault time interval, actively realizes fault prevention and fault tolerance processing, reduces fault response time, improves fault handling efficiency, and avoids task interruption caused by sudden failure of the main computing module.

[0025] Specifically, Figure 1 This is a schematic diagram of an in-vehicle computing system provided in an embodiment of this application.

[0026] like Figure 1 As shown, the vehicle-mounted computing system 10 includes at least one main computing module 11, a pre-fault prediction module 12, and a scheduling module 13.

[0027] The main computing module 11 is used to execute the target computing task; the pre-fault prediction module 12 includes a pre-fault prediction model, which predicts the fault time interval of the main computing module 11 based on the pre-fault prediction model; the scheduling module 13 is used to trigger the corresponding fault tolerance strategy according to the fault time interval and execute the fault tolerance strategy.

[0028] The main computing module in this embodiment is the core computing unit of the vehicle computing system and the main carrier for performing target computing tasks. The target computing tasks can be sensor data fusion, target tracking, path planning, etc. in autonomous driving scenarios. The pre-fault prediction model can be an LSTM (Long Short-Term Memory) prediction model. The fault time interval is the time difference from the current moment to the time when the main computing module predicts the occurrence of a fault.

[0029] It is understood that the embodiments of this application construct an in-vehicle computing system 10, including a main computing module 11, a pre-fault prediction module 12 and a scheduling module 13. The pre-fault prediction module 12 can predict the fault time interval of the main computing module based on the pre-fault prediction model. The scheduling module 13 triggers the corresponding fault tolerance strategy based on the fault time interval, actively realizes fault prevention and performs fault tolerance processing, reduces fault response time, improves fault handling efficiency, and avoids task interruption caused by sudden failure of the main computing module 11.

[0030] Furthermore, in one embodiment of this application, the main computing module 11 is composed of a plurality of biomimetic synapses, wherein the biomimetic synapse includes: a substrate; a graphene bottom gate disposed on the substrate, and a top gate covering the graphene bottom gate, wherein a biosynaptic interface is disposed on the outer side of the top gate for receiving input voltage from an external sensor; a molybdenum disulfide channel layer disposed on the top gate, and an ion gel layer covering the molybdenum disulfide channel layer.

[0031] It is understood that the main computing module 11 in this embodiment is composed of multiple bionic synapses, and the specific structure of the bionic synapses is as follows: Figure 2 As shown, it includes: a substrate; a graphene bottom gate disposed on the substrate, and a top gate covering the graphene bottom gate, wherein a biosynaptic interface is disposed on the outer side of the top gate for receiving input voltage from an external sensor; a molybdenum disulfide channel (MoS2) layer disposed on the top gate, and an ion gel layer covering the molybdenum disulfide channel layer.

[0032] The biomimetic synapse of this application has a synapse density of 10⁹ cells / cm², a weight update delay of ≤5ns, and a single synapse energy consumption of 0.05fJ / bit.

[0033] This application uses biomimetic synapses as computing units and adopts a MoS2 / ion gel heterojunction structure. This material has extremely high charge retention capability and extremely low leakage current, which fundamentally reduces static power consumption.

[0034] Furthermore, in one embodiment of this application, the top gate and the graphene bottom gate form a dual-gate control structure to simulate calcium ion channels and adjust the conductivity of the molybdenum disulfide channel layer according to the synaptic dynamics equation; the molybdenum disulfide channel layer and the ion gel layer constitute a heterojunction to adjust the weights through changes in conductivity and realize the analog domain multiplication and addition operation of the input voltage pulse and the weights.

[0035] The dual-gate control structure is a synergistic control structure composed of a top gate and a graphene bottom gate. By applying different voltages to the top and bottom gates, it simulates the voltage-gated characteristics of calcium ion channels in biological nerves, achieving precise and dynamic adjustment of the conductivity of the MoS2 channel layer. The simulated calcium ion channel simulates the transmembrane flow of calcium ions in biological nerve cells through voltage changes in the dual-gate control structure. The calcium ion concentration is simulated by the gate voltage, thereby regulating the plasticity (weight change) of the synapse and restoring the signal transmission mechanism of biological synapses. The heterojunction is a heterostructure composed of a MoS2 channel layer (semiconductor) and an ion gel layer (electrolyte). It combines the tunable conductivity of MoS2 with the low leakage current characteristics of ion gel, and is the core structure for achieving low power consumption, high stability weight adjustment and analog domain operation. The analog domain multiply-add operation uses the input voltage pulse (analog signal) and the conductivity (weight) of the MoS2 channel layer for multiplication. The output currents of multiple synapses are superimposed to achieve the addition operation, and finally the current signal is output.

[0036] The dual-gate control structure of this application simulates calcium ion channels and, combined with the weight adjustment capability of heterojunctions, enables the biomimetic synapse to possess plasticity similar to biological nerves. It can dynamically adjust the weights according to the input signal strength (voltage pulse amplitude) and frequency, and can adapt to sudden computing loads (such as the need for rapid decision-making when obstacles suddenly appear in autonomous driving). It can increase computing power by 3-5 times within 100μs. Moreover, the analog domain multiplication and addition operations do not require analog-to-digital conversion, clock synchronization and other links in traditional digital computing, reducing conversion loss and synchronization overhead. At the same time, the synaptic dynamics equation guides the weight adjustment, so that the change of conductivity (weight) can be quantitatively controlled and avoids excessive weight drift.

[0037] Furthermore, in one embodiment of this application, the synaptic dynamics equation is: ; in, The change in weight. The calcium ion diffusion coefficient is... The calcium ion concentration is simulated by the gate voltage. Input voltage, This is the output voltage after biomimetic synapse processing.

[0038] Furthermore, in one embodiment of this application, the bionic synapse is further used to: adjust the short-term enhancement factor based on the computational load of the target computing task.

[0039] Among them, the short-term enhancement factor is a parameter that simulates the short-term plasticity of biological synapses. It is used to adjust the instantaneous computing power of bionic synapses. The larger the value of the short-term enhancement factor, the higher the signal transmission efficiency of the synapse per unit time and the stronger the computational load that can be handled.

[0040] It is understood that the bionic synapse in this application embodiment can adjust the short-term enhancement factor based on the computational load of the target computing task to enhance the computational stability of the vehicle computing system under sudden loads.

[0041] Specifically, the biomimetic synapse implemented in this application includes a material layer, a structural layer, and a circuit layer. The material layer adopts a two-dimensional MoS2 and ion gel heterojunction, which can achieve an ion migration energy consumption of 0.05 fJ / bit compared to the traditional CMOS (Complementary Metal Oxide Semiconductor) which has a power consumption of >1 fJ. The structural layer is based on a dual-gate transistor that simulates a calcium ion channel, with a weight update speed of ≤5 ns, which is 20 times faster than related technologies. The circuit layer is an STP characteristic analog circuit, and the short-term synaptic enhancement factor β can be set to 0.8 and can be dynamically adjusted.

[0042] Furthermore, in one embodiment of this application, the pre-fault prediction module 12 is further configured to: obtain the equivalent series resistance value of the electrolytic capacitor, the thermal noise spectrum, and the temperature change rate of the main calculation module 11; input the equivalent series resistance value of the electrolytic capacitor, the thermal noise spectrum, and the temperature change rate into the pre-fault prediction model, and the pre-fault prediction model outputs the predicted fault time interval.

[0043] It is understood that the embodiments of this application can monitor the main computing module, namely the equivalent series resistance value, thermal noise spectrum and temperature change rate of the electrolytic capacitor of the bionic synapse, and input the equivalent series resistance value, thermal noise spectrum and temperature change rate of the electrolytic capacitor into the pre-fault prediction model. The pre-fault prediction model outputs the predicted fault time interval, thereby realizing the early prediction of faults and completing the fault prediction before the hardware completely fails, reserving sufficient time for the scheduling module to trigger the fault tolerance strategy.

[0044] The formula for calculating the fault time interval in this application embodiment can be: T_fault = f (ESR, dT / dt, Noise_PSD); Where T_fault is the fault time interval, ESR is the equivalent series resistance of the electrolytic capacitor, dT / dt is the temperature change rate, and Noise_PSD is the thermal noise spectrum.

[0045] Furthermore, in one embodiment of this application, the in-vehicle computing system 10 further includes at least one backup computing module, wherein the backup computing module is composed of a plurality of bionic synapses.

[0046] It is understood that the vehicle computing system 10 in this application embodiment also includes a backup computing module. The backup computing module has the same structure as the main computing module, so that when the main computing module fails, the backup computing module is used to reduce the impact of the failure and improve the reliability of the vehicle computing system.

[0047] Furthermore, in one embodiment of this application, the scheduling module 13 is further configured to: if the fault time interval is greater than a first preset duration, then the fault tolerance strategy is the first strategy; if the fault time interval is greater than a second preset duration and less than or equal to the first preset duration, then the fault tolerance strategy is the second strategy; if the fault time interval is less than or equal to the second preset duration, then the fault tolerance strategy is the third strategy.

[0048] The first preset duration and the second preset duration can be set according to specific circumstances, without any specific limitations. For example, the first preset duration can be set to 5ms or 6ms, and the second preset duration can be set to 1ms or 2ms.

[0049] It is understood that the embodiments of this application can determine different fault tolerance strategies based on the predicted fault time interval, match differentiated strategies for different risk levels, and balance the problems of excessive fault tolerance and insufficient fault tolerance.

[0050] Furthermore, in one embodiment of this application, the first strategy is to save the bionic synaptic state difference at target intervals; the second strategy is to copy the target computing task to the backup computing module, and the main computing module 11 and the backup computing module execute the target computing task synchronously; the third strategy is to use the target hardware hot-swap protocol to switch the hardware interface connected to the main computing module 11 to the backup computing module, wherein the backup computing module executes the target computing task and the main computing module 11 is disabled.

[0051] The target duration can be set according to specific circumstances, and there is no specific limitation on the comparison, such as setting it to 1ms or 2ms; the state difference is divided into the part of the total change between the current bionic synapse state and the last saved state; the target hardware hot-swap protocol can be PCIe Gen5.

[0052] It is understood that in this embodiment of the application, when the fault time interval is greater than the first preset time, the bionic synaptic state difference is saved at a target time interval, which can significantly reduce storage overhead by 70%. If the main computing module fails later, the most recent state difference can be read from the cache and combined with historical data to quickly restore the synaptic state. When the fault interval is greater than the second preset duration and less than or equal to the first preset duration, task cloning can be performed to copy the target computing task to the backup computing module. The main computing module and the backup computing module run in parallel, executing the target computing task at the same time, ensuring that the backup computing module can take over immediately without waiting for task migration or status recovery when the main computing module fails. When the fault interval is less than or equal to the second preset duration, hardware switching can be completed quickly through PCIe Gen5, immediately stopping the main computing module, cutting off the signal connection with sensors and actuators, with a switching delay of ≤100ns, and the backup computing module executes the target computing task.

[0053] This application enables hardware switching to be completed within 82ns using PCIe Gen5. Based on the atomic operation protocol of PCIe Gen5, it can avoid the scheduling overhead of traditional operating systems. Furthermore, it adopts a pre-synchronization mechanism to ensure that the backup NPU (Neural Processing Unit) (i.e., backup computing module) is always synchronized with the main NPU (i.e., main computing module). During switching, only the difference data needs to be transmitted. At the same time, charge preservation technology is used to ensure that the synaptic state is not lost during the switching process.

[0054] The embodiments of this application can also achieve energy efficiency compensation and reduce energy efficiency fluctuations through adaptive adjustment of synaptic voltage.

[0055] Furthermore, it should be noted that, in addition to using the LSTM prediction model to output the fault time interval to trigger the corresponding fault tolerance strategy, the embodiments of this application can also use the probability output by the fault probability model to trigger the corresponding fault tolerance strategy. For example, the resistance change rate, thermal noise spectrum and temperature change rate are input into the fault probability model, the fault probability model outputs the corresponding fault probability, and the corresponding fault tolerance strategy is matched based on the fault probability. For example, if the fault probability is greater than the first preset probability, the fault tolerance strategy is the first strategy; if the fault probability is greater than the second preset probability and less than or equal to the first preset probability, the fault tolerance strategy is the second strategy; if the on-balance-sheet probability is less than or equal to the second preset probability, the fault tolerance strategy is the third strategy.

[0056] The failure probability model can be: P_fault = 1 / (1 + exp(-z)); Where P_fault is the failure probability, z is the log odds output by the linear regression, z = ∑(w_i · x_i) + b, w_i and b are model parameters, w_i is the weight, b is the bias term, and x_i is the input feature, x = [dR / dt, f_c, d 2 T / dt 2 ], dR / dt is the rate of change of resistance, dT / dt is the rate of change of temperature, and f_c is the characteristic frequency of the thermal noise spectrum.

[0057] Specifically, the dynamic fault tolerance strategy of this application embodiment is shown in Table 1.

[0058]

[0059] Specifically, the implementation of the vehicle computing system in this application mainly includes three parts: biomimetic synapses as computing units, a pre-fault prediction algorithm, and a dynamic fault tolerance mechanism.

[0060] I. Bionic synapse.

[0061] The specific structure of a bionic synapse is as follows: Figure 2 As shown, a MoS2 / ion gel heterojunction structure is adopted. This material has extremely high charge retention capability and extremely low leakage current, which fundamentally reduces static power consumption. It simulates the voltage gating characteristics of biological neural calcium ion channels and achieves precise charge injection control through dual-gate regulation, avoiding the switching power loss of traditional CMOS devices. Utilizing the STP characteristic, it automatically enters the subthreshold working state when there is no computing task, reducing power consumption to the nW level.

[0062] Each bionic synapse is equivalent to a MAC (multiply-accumulate) unit in a traditional AI accelerator, but it has the ability to dynamically adjust weights. The weights are represented by the conductivity of the MoS2 channel. The input voltage pulse and the weights are multiplied and added in the analog domain, and the output current signal is generated. Event-driven calculation is used, and the synapse is activated only when the input signal arrives, thus avoiding the power loss caused by clock synchronization.

[0063] Furthermore, this application can dynamically adjust the weights and enhancement factors of the biomimetic synapse, achieving adaptability to the biological nervous system. The weights determine the strength of information transmission, corresponding to long-term memory and learning ability, while the enhancement factors simulate calcium ion-dependent short-term plasticity, enabling instantaneous computational power enhancement under burst loads. When the system detects a sudden computational demand, it simultaneously increases the enhancement factor and adjusts the weights, increasing computational power by 3-5 times within 100μs.

[0064] The dynamic equation of a synapse is as follows: ; in, The change in weight. The calcium ion diffusion coefficient determines the weight update rate. =0.03, The calcium ion concentration is determined by the gate voltage V. ecc Simulate and control synaptic plasticity. Input voltage, This is the output voltage after biomimetic synapse processing.

[0065] II. PFP (Pre-Fault Prediction) algorithm, the overall process is as follows: Figure 3 As shown.

[0066] The goal of the fault prediction algorithm in this application is to predict faults more than 10ms before complete hardware failure, thus providing a time window for fault-tolerant switching.

[0067] 2.1 Fault feature extraction.

[0068] The electrolytic capacitance ESR value (threshold > 50 mΩ), thermal noise spectrum (1 / f noise inflection point detection), and temperature change rate of the biomimetic synapse were monitored online. Among them, the increase in ESR value indicates ion gel aging, and the 1 / f noise inflection point indicates the generation of MoS2 channel defects.

[0069] 2.2 Prediction Model.

[0070] Fault time prediction based on LSTM prediction model: T_fault=f(ESR,dT / dt, Noise_PSD), prediction accuracy>92%, false alarm rate<0.1%.

[0071] Specifically, the LSTM prediction model takes multiple time-series monitoring data as input, including ESR, temperature change rate, and 128 frequency domain features of thermal noise spectrum, and outputs the predicted time interval Δt from the current moment to the occurrence of the fault, with an accuracy of milliseconds.

[0072] III. Dynamic fault tolerance mechanism, as shown in Table 1 and Figure 4 As shown, Figure 4 The timing diagram for dynamic fault-tolerant scheduling is provided, and a 100ns-level switching process is implemented.

[0073] The main advantages of this application compared to NVIDIA Orin in related technologies are shown in Table 2.

[0074]

[0075] In summary, this application can break through the power consumption barrier of neuromorphic computing (target ≤0.5μW / synapse, related technologies ≥2μW); achieve pre-fault detection (predicting faults 10ms in advance) and fault-tolerant switching latency ≤100ns; and improve computing stability under burst loads (task completion rate >99.999%).

[0076] The implementation process of the vehicle-mounted computing system of this application embodiment is described below through specific embodiments.

[0077] Example 1: Bionic synaptic computation.

[0078] 1. Input: 4D millimeter-wave radar point cloud (100,000 points / frame); 2. Processing: The synaptic array performs 3D convolution (using STP characteristics to dynamically allocate weights); 3. Output: Target tracking trajectory (delay ≤ 800μs).

[0079] Example 2: Pre-fault response.

[0080] 1. Detection: Capacitor ESR value rises to 55mΩ (predicted fault countdown 8.2ms); 2. Migration: Clone the planned task to the backup NPU (takes 75ns); 3. Recovery: The faulty node enters ion rebalancing mode (power consumption drops to 0.1μW).

[0081] The vehicle-mounted computing system proposed in the embodiments of this application includes a main computing module, a pre-fault prediction module, and a scheduling module. The pre-fault prediction module can predict the fault time interval of the main computing module based on the pre-fault prediction model. The scheduling module triggers the corresponding fault tolerance strategy based on the fault time interval, actively realizes fault prevention and performs fault tolerance processing, reduces fault response time, improves fault handling efficiency, and avoids task interruption caused by sudden failure of the main computing module.

[0082] Embodiments of this application also provide a vehicle including the on-board computing system described above.

[0083] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0085] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0086] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or more of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (FPGAs), field-programmable gate arrays (FPGAs), etc.

[0087] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

Claims

1. An in-vehicle computing system, characterized in that, include: At least one main computing module is used to execute the target computing task; The main computing module is composed of multiple biomimetic synapses, each biomimetic synapse comprising: a substrate; a graphene bottom gate disposed on the substrate, and a top gate covering the graphene bottom gate, wherein a biosynaptic interface is disposed on the outer side of the top gate for receiving input voltage from an external sensor; a molybdenum disulfide channel layer disposed on the top gate, and an ion gel layer covering the molybdenum disulfide channel layer; the top gate and the graphene bottom gate form a dual-gate control structure for simulating calcium ion channels and adjusting the conductivity of the molybdenum disulfide channel layer according to the synaptic dynamics equation; the molybdenum disulfide channel layer and the ion gel layer form a heterojunction for adjusting weights through conductivity changes and realizing analog domain multiplication and addition operations of input voltage pulses and weights; the synaptic dynamics equation is: ； in, The change in weight. Let be the calcium ion diffusion coefficient, [ [This represents the calcium ion concentration.] Input voltage, The output voltage after biomimetic synapse processing; A fault prediction module, comprising a fault prediction model, for predicting the fault time interval of the main computing module based on the fault prediction model; The scheduling module is used to trigger the corresponding fault tolerance strategy according to the fault time interval and execute the fault tolerance strategy.

2. The vehicle-mounted computing system according to claim 1, characterized in that, The bionic synapse is further used to: adjust the short-term enhancement factor based on the computational load of the target computing task.

3. The vehicle-mounted computing system according to claim 1, characterized in that, The fault prediction module is further used for: Obtain the equivalent series resistance value of the electrolytic capacitor, the thermal noise spectrum, and the temperature change rate of the main computing module; The equivalent series resistance of the electrolytic capacitor, the thermal noise spectrum, and the temperature change rate are input into the pre-fault prediction model, and the pre-fault prediction model outputs the predicted fault time interval.

4. The vehicle-mounted computing system according to claim 1, characterized in that, The in-vehicle computing system further includes at least one backup computing module, wherein the backup computing module is composed of multiple bionic synapses.

5. The vehicle-mounted computing system according to claim 4, characterized in that, The scheduling module is further used for: If the fault time interval is greater than the first preset duration, then the fault tolerance strategy is the first strategy; If the fault time interval is greater than the second preset duration and less than or equal to the first preset duration, then the fault tolerance strategy is the second strategy. If the fault time interval is less than or equal to the second preset duration, then the fault tolerance strategy is the third strategy.

6. The vehicle-mounted computing system according to claim 5, characterized in that, The first strategy is to save the biomimetic synaptic state difference at intervals of the target duration; The second strategy is to copy the target computing task to the backup computing module, and the main computing module and the backup computing module execute the target computing task synchronously. The third strategy involves using a target hardware hot-swappable protocol to switch the hardware interface connected to the main computing module to the backup computing module, wherein the backup computing module executes the target computing task, and the main computing module is disabled.

7. A vehicle, characterized in that, Including the in-vehicle computing system as described in any one of claims 1-6.

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