Laser chip cleaving method and laser chip

Abstract

The embodiment of the application discloses a laser chip cleaving method and a laser chip. The laser chip cleaving method comprises the following steps: forming a first cleaving channel on a first surface of a wafer, forming a second cleaving channel on a second surface, and then applying stress to the second cleaving channel, so that the wafer is cleaved into a plurality of laser chips. In combination with the second cleaving channel along the height direction of the wafer, the outer edge profile of the cross section of the second cleaving channel gradually decreases in width in the direction from the second surface to the first surface, so that the width of the tip of the second cleaving channel is very small, and a notch tip is formed. In the case that the second cleaving channel is stressed, in combination with the fact that a crack always tends to expand along the path with the highest energy and the smallest resistance, the path of the crack is facilitated to be controlled, the randomness of crack expansion is reduced, the cavity surface perpendicularity of the chip can be improved, the cleaving surface roughness is reduced, and the utilization rate of the wafer is improved.

Description

Technical Field

[0001] This application relates to the field of optoelectronic communication technology, and in particular to a laser chip cleavage method and a laser chip. Background Technology

[0002] In the field of modern optical communication technology, InP (indium phosphide) and GaAs (gallium arsenide) substrates, due to their excellent optoelectronic properties, have become core materials for fabricating high-performance laser chips, and are widely used in key scenarios such as fiber optic communication, data center interconnection, and 5G / 6G wireless communication. As optical communication systems rapidly evolve towards higher speeds, higher integration, and lower power consumption, more stringent requirements are being placed on the performance indicators and fabrication costs of laser chips. Chip cleaving technology, as a crucial step in the laser fabrication process, directly determines the final performance and economic viability of the chip.

[0003] In existing laser chip fabrication processes, the core objective of cleaving is to form a flat, smooth optical interface on the chip's end face to ensure efficient laser reflection and transmission within the cavity and reduce optical loss. However, current mainstream cleaving techniques (such as mechanical scribing-splitting) facets face challenges in controlling the roughness of the cleaved end facets in practical applications. This roughness not only significantly increases the light scattering loss of the laser cavity and reduces the laser's electro-optical conversion efficiency, but also accelerates the oxidation and aging of the end facets. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This part of the invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0006] Therefore, a first aspect of the present invention provides a laser chip cleavage method.

[0007] A second aspect of the present invention provides a laser chip.

[0008] In view of this, a laser chip cleavage method is proposed according to a first aspect of the embodiments of this application, comprising:

[0009] A wafer with a laser pattern fabricated is provided, wherein the patterned side of the wafer is a first side and the substrate side of the wafer is a second side;

[0010] A first cleaving channel is formed on the first surface, and a second cleaving channel is formed on the second surface. Along the wafer height direction, the outer edge profile of the cross-section of the second cleaving channel gradually decreases in width in the direction from the second surface to the first surface.

[0011] Stress is applied to the second cleaving path to cleave the wafer and obtain multiple laser chips.

[0012] In one feasible implementation, the step of providing a wafer with a patterned laser, wherein the patterned side of the wafer is a first side and the substrate side of the wafer is a second side, includes:

[0013] The wafer provided completes the laser pattern fabrication;

[0014] The wafer is thinned to a thickness of 50 μm to 150 μm.

[0015] In one feasible implementation, the steps of forming a first cleavage path on the first surface and forming a second cleavage path on the second surface include:

[0016] A portion of the insulating film on the first surface of the wafer is etched using a BOE solution to form multiple first cleavage paths;

[0017] Multiple second cleavage paths are formed on the second surface of the wafer by deep reactive ion etching, and the multiple second cleavage paths are arranged opposite to the first cleavage path.

[0018] In one feasible implementation, the step of forming a plurality of second cleavage paths on the second surface of the wafer by deep reactive ion etching, wherein the plurality of second cleavage paths are arranged opposite to the first cleavage path, includes:

[0019] First, use the first power to etch to the target depth;

[0020] Then, a second power is used to continue etching so that the second cleavage path reaches the designed depth.

[0021] Wherein, the second power is less than the first power, and the difference between the design depth and the target depth is greater than or equal to 3 μm.

[0022] In one feasible implementation, along the wafer height direction, the outer edge profile of the cross-section of the second cleaving channel is V-shaped, with the tip of the V-shape facing the first cleaving channel.

[0023] In one feasible implementation, the ratio of the etching depth of the second cleaving path to the thickness of the wafer is 30% to 40%.

[0024] The groove angle of the second cleavage path is 53.7° to 55.7°;

[0025] The radius of curvature of the groove tip of the second cleavage channel is ≤100nm.

[0026] In one feasible implementation, the step of applying stress to the second cleaving track to cleave the wafer and obtain a plurality of laser chips includes:

[0027] The wafer is fixed by vacuum adsorption;

[0028] Stress is applied to the second cleaving path to cleave the wafer and obtain multiple laser chips;

[0029] Among them, the area where the first cleavage channel is located is the groove area, and the area on the first surface other than the groove area is the non-groove area. The vacuum adsorption pressure increases from the groove area to the non-groove area.

[0030] The adsorption pressure formed by vacuum adsorption on the first surface is 0.1 MPa to 0.01 MPa.

[0031] In one feasible implementation, the step of applying stress to the second cleaving track to cleave the wafer further includes:

[0032] A laser is used to ablate and form cracks in the groove tip region of the second cleaving path to cleave the wafer and obtain multiple laser chips.

[0033] In one feasible implementation, the step of using a laser to ablate and form cracks in the groove tip region of the second cleaving path to cleave the wafer and obtain multiple laser chips includes:

[0034] An initial pulse laser is emitted, and a micron-sized initial pit is formed in the groove tip region with the first energy, which serves as the crack initiation point;

[0035] A subsequent pulsed laser is emitted, and a continuous ablation line is formed in the direction of the groove tip extension using a progressively increasing second energy to create cracks, thereby cleaving the wafer and obtaining multiple laser chips;

[0036] The second energy is greater than the first energy.

[0037] According to a second aspect of the embodiments of this application, a laser chip is provided.

[0038] The laser chip is prepared by laser chip cleaving method as described in any of the above technical solutions;

[0039] The perpendicularity of the cavity surface of the laser chip is less than 0.5°.

[0040] Compared with the prior art, the present invention has at least the following beneficial effects:

[0041] The laser chip cleaving method provided in this application forms a first cleaving channel on a first surface of a wafer and a second cleaving channel on a second surface. Stress is then applied to the second cleaving channel, causing the wafer to be cleaved into multiple laser chips. Combined with the structure where the outer edge of the cross-section of the second cleaving channel gradually decreases in width along the direction from the second surface to the first surface, the tip of the second cleaving channel has a very small width, forming a groove tip. Under stress on the second cleaving channel, the crack tends to propagate along the path with the highest energy and least resistance, which facilitates control of the crack path and reduces the randomness of crack propagation. This can improve the perpendicularity of the chip cavity surface, reduce the roughness of the cleaved surface, and improve the utilization rate of the wafer.

[0042] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0043] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0044] Figure 1 A schematic flowchart illustrating the steps of a laser chip cleavage method according to an embodiment of this application;

[0045] Figure 2 This is a schematic structural diagram of the wafer to be cleaved in a laser chip cleaving method according to an embodiment of this application.

[0046] in, Figure 1 The correspondence between the reference numerals and component names in the attached drawings is as follows:

[0047] 110 wafer, 120 first cleaving channel, 130 second cleaving channel;

[0048] 111 First page, 112 Second page. Detailed Implementation

[0049] The following description provides numerous specific details to offer a more thorough understanding of the technical solutions provided by this invention. However, it will be apparent to those skilled in the art that the technical solutions provided by this invention can be implemented without one or more of these details.

[0050] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0051] Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the invention is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0052] like Figure 1 As shown, a laser chip cleavage method is proposed according to a first aspect of the embodiments of this application, comprising:

[0053] Step 101: Provide a wafer with the laser pattern fabricated, wherein the side of the wafer with the pattern is the first side and the side of the wafer on the substrate side is the second side;

[0054] Step 102: Form a first cleavage path on the first surface and a second cleavage path on the second surface. Along the wafer height direction, the outer edge profile of the cross section of the second cleavage path gradually decreases in width in the direction from the second surface to the first surface.

[0055] Step 103: Apply stress to the second cleaving path to cleave the wafer and obtain multiple laser chips.

[0056] like Figure 1 and Figure 2As shown, the laser chip cleaving method provided in this application embodiment forms a first cleaving channel 120 on the first surface 111 of the wafer 110 and a second cleaving channel 130 on the second surface 112. Then, stress is applied to the second cleaving channel 130, causing the wafer 110 to be cleaved into multiple laser chips. Combined with the structure where the outer edge contour of the cross section of the second cleaving channel 130 gradually decreases in width along the direction from the second surface 112 to the first surface 111 along the height direction of the wafer 110, the tip of the second cleaving channel 130 has a very small width, forming a groove tip. Under stress on the second cleaving channel 130, the crack always tends to propagate along the path with the highest energy and the least resistance, which makes it easier to control the crack path and reduce the randomness of crack propagation. This can improve the cavity surface perpendicularity of the chip, reduce the roughness of the cleaving surface, and improve the utilization rate of the wafer 110.

[0057] The laser chip cleaving method provided in this application provides a laser chip with a cavity surface perpendicularity of <0.5° and an angle deviation reduced by 75%; a cleaving surface roughness Ra <1nm: improving the cavity surface reflectivity uniformity to within ±3%; and improving wafer 110 utilization: increasing the edge chip yield from 65% to 92%.

[0058] The laser chip cleavage method provided in this application, in the field of fracture mechanics, clarifies the core condition for crack propagation according to Griffith's theory: a crack will only continue to propagate when the stress intensity factor applied to the crack tip exceeds the inherent fracture toughness of the material. The stress intensity factor reflects the stress concentration at the crack tip, while fracture toughness is an inherent property of the material; for example, the fracture toughness of InP is approximately 0.45 MPa·m^(1 / 2), while that of GaAs is approximately 0.35 MPa·m^(1 / 2), meaning that GaAs has relatively weaker resistance to crack propagation. Combined with the groove-shaped second cleavage channel 130 provided in this application, its tip can be considered a pre-set "guide crack." When analyzing the stress intensity factor, three key factors need to be considered: first, the geometric factor related to the crack shape; second, the external stress applied to wafer 110; and third, the equivalent length of the crack (i.e., the distance from the tip of the slot to the first cleavage path 120). In traditional cleavage processes, the geometric factor of the tip of a conventional cleavage path formed by mechanical scribing is relatively large, typically around 1.9; while the slot-tip structure of this scheme, calculated through finite element analysis, has a geometric factor of only 1.2-1.5. This difference brings significant advantages: under the same external stress, the stress intensity factor of this scheme is lower, which can effectively avoid the burst propagation of cracks due to excessive stress concentration—such uncontrolled propagation is often the core cause of crack displacement and end-face defects.

[0059] Furthermore, according to the fundamental laws of thermodynamics, crack propagation always follows the principle of minimum energy, meaning that cracks will spontaneously extend along the direction of maximum strain energy release. Here, strain energy release refers to the strain energy released per unit area of ​​crack during propagation. It is directly related to the stress intensity factor and is also affected by the material's elastic modulus—InP has an elastic modulus of approximately 10³ GPa, and GaAs approximately 85 GPa. The higher the elastic modulus, the higher the strain energy release rate under the same stress intensity factor. This scheme constructs a double-sided pre-set path by setting a first cleavage path 120 on the first surface 111 of wafer 110 and machining a groove-tipped second cleavage path 130 on the second surface 112. When directional stress is applied to the second cleavage path 130, the strain energy is highly concentrated in the straight line direction "groove tip → first cleavage path 120," and the strain energy release rate in this direction is 30%-50% higher than in any other direction. Taking InP wafer 110 as an example, when an external stress of 50 MPa is applied, the strain energy release rate along the preset path is approximately 0.21 J / m. 2 The strain energy release rate perpendicular to the preset path direction is only 0.14 J / m. 2 This significant energy difference is sufficient to "lock" the crack onto a predetermined path, ensuring its stable propagation in a straight line.

[0060] Furthermore, the working principle of a laser relies on the reflection of the cavity surface to create stable oscillations within the chip. If there is a perpendicularity deviation in the cavity surface, it will cause an additional optical path difference during reflection—that is, the actual optical path of the laser propagation differs from the optical path under ideal perpendicularity to the cavity surface. The magnitude of this additional optical path difference is mainly related to two factors: the chip thickness (typically 100-200 μm) and the perpendicularity deviation angle—the larger the deviation angle and the thicker the chip, the greater the additional optical path difference. This solution, through precise control of the crack propagation path, can strictly limit the perpendicularity deviation of the cavity surface to within 0.5°. Calculated with a 200 μm thick chip, the additional optical path difference is approximately 3.49 μm, only 2.25 times that of a 1550 nm wavelength. The multi-beam interference effect is significantly weakened, and the optical power fluctuation amplitude is reduced to 2%-3%. Combining the Fresnel reflection principle in optics, the stability of the cavity surface reflectivity was improved by 15%-20% after the verticality was optimized. The stability of the reflectivity directly reduced the unexpected loss of laser in the cavity, and ultimately boosted the photoelectric conversion efficiency of the laser by 3%-8%. This clearly quantifies the value of verticality improvement to device performance from the perspective of optical theory.

[0061] like Figure 2As shown, in one feasible embodiment, the step of providing a wafer 110 with a patterned laser, wherein the patterned side of the wafer 110 is a first side 111 and the substrate side of the wafer 110 is a second side 112 includes: providing a wafer 110 with a patterned laser; and thinning the wafer 110 to a thickness of 50 μm to 150 μm.

[0062] This technical solution further provides a specific structure for wafer 110. Mechanical grinding combined with chemical mechanical polishing (CMP) can be used to thin wafer 110 from its initial thickness (300-500 μm) to 50-150 μm, ensuring a thickness uniformity error of ≤±2 μm. After thinning, surface cleaning can be performed: ultrasonic cleaning with a sulfuric acid-hydrogen peroxide mixture (volume ratio 3:1) for 10 minutes, rinsing with deionized water for 5 minutes, and drying with nitrogen to remove residual grinding particles and oxide layers. This setup results in two advantages: firstly, a lower cleavage stress threshold after thinning (e.g., stress on InP wafer 110 decreases from 80 MPa to 45 MPa), more uniform stress distribution, shorter crack paths, and reduced risk of displacement; secondly, reduced thermal resistance (InP chip thermal resistance decreases from 25 K / W to 12 K / W), improved heat dissipation, wavelength drift ≤±0.2 nm, and volume absorption loss decreases from 2.5% to 0.75%, improving electro-optical conversion efficiency by 5%-8%, thus enhancing the performance of the laser chip.

[0063] like Figure 2 As shown, in one feasible embodiment, the steps of forming a first cleavage path 120 on a first surface 111 and a second cleavage path 130 on a second surface 112 include: etching a portion of the insulating film on the first surface 111 of the wafer 110 with a BOE solution to form a plurality of first cleavage paths 120; and forming a plurality of second cleavage paths 130 on the second surface 112 of the wafer 110 by deep reactive ion etching, wherein the plurality of second cleavage paths 130 are disposed opposite to the first cleavage paths 120.

[0064] This technical solution further provides a method for forming the first cleavage channel 120 and the second cleavage channel 130. The first cleavage channel 120 is formed by BOE solution etching, making the first cleavage channel 120 planar. The second cleavage channel 130 is formed by deep reactive ion etching. On the one hand, the first cleavage channel 120 etched by BOE and the second cleavage channel 130 etched by deep reactive ion etching form a stress focusing area, and the cracks propagate along a preset path, greatly reducing the risk of displacement. On the other hand, the edge of the etched second cleavage channel 130 is flat, which, together with the etched first cleavage channel 120, reduces the roughness of the cleavage surface and reduces light scattering loss. Furthermore, the relative setting is adapted to subsequent stress application and is compatible with InP / GaAs substrates, meeting the requirements of high-density packaging and improving chip sorting yield.

[0065] In one feasible implementation, a plurality of second cleavage paths 130 are formed on the second surface 112 of wafer 110 by deep reactive ion etching, wherein the plurality of second cleavage paths 130 are arranged opposite to the first cleavage path 120. The steps include: first etching to a target depth using a first power; and then continuing etching using a second power to make the second cleavage paths 130 reach the designed depth; wherein the second power is less than the first power, and the difference between the designed depth and the target depth is greater than or equal to 3 μm.

[0066] This technical solution further provides a specific process for deep reactive ion etching, which can be performed by etching twice with different intensities, using a method of etching from weak to strong, which can ensure etching accuracy, especially the etching accuracy of the 130 groove tip of the second cleavage channel.

[0067] In some examples, the specific process steps of deep reactive ion etching may include using a mixture of CH4, H2, and Ar as the etching gas with a flow rate ratio of 3:10:20, maintaining an operating pressure of 20-30 mTorr, setting the RF power to 200-250 W, and controlling the etching rate at 1-2 μm / min. A periodic alternating plasma etching / passivation process is introduced to precisely control the trench depth using a real-time endpoint detection system, ensuring that the trench wall verticality deviation is ≤0.5°. A two-step etching method is employed: first, etching at a higher power to near the target depth, then switching to a lower power (e.g., 100 W) for fine etching at the final 3 μm depth. The trench tip curvature radius can be monitored online using an atomic force microscope (AFM) to ensure it is ≤100 nm, avoiding cleavage shift due to insufficient stress concentration.

[0068] like Figure 2 As shown, in one feasible embodiment, along the height direction of wafer 110, the outer edge profile of the cross-section of the second cleaving path 130 is V-shaped, with the tip of the V-shape facing the first cleaving path 120. This arrangement facilitates precise control of the cleaving path and improves cleaving accuracy.

[0069] In one feasible implementation, the ratio of the etching depth of the second cleaving channel 130 to the thickness of the wafer 110 is 30% to 40%; the groove angle of the second cleaving channel 130 is 53.7° to 55.7°; and the groove tip curvature radius of the second cleaving channel 130 is ≤100nm.

[0070] This technical solution further provides specific specifications for the second cleaving channel 130. The depth ratio of 30%-40% is adapted to the thickness of the wafer 110, ensuring effective stress transfer while avoiding excessive etching that could damage the wafer 110. A 53.7°-55.7° trench angle, preferably 54.7°, forms a stable stress focusing structure. Combined with a trench tip curvature radius of ≤100nm, stress concentration is more precise, and crack propagation along a preset path reaches 99%. Simultaneously, the narrow curvature radius reduces trench tip defects, and combined with trench angle optimization, the cleavage surface roughness is further reduced to 2-3nm. Sidewall perpendicularity is stabilized at over 98%, making it compatible with InP / GaAs substrates and meeting the precision requirements of high-density packaging, thereby improving chip yield.

[0071] like Figure 2 As shown, in one feasible embodiment, the step of applying stress to the second cleaving channel 130 to cleave the wafer 110 and obtain multiple laser chips includes: fixing the wafer 110 by vacuum adsorption; applying stress to the second cleaving channel 130 to cleave the wafer 110 and obtain multiple laser chips; wherein, the area where the first cleaving channel 120 is located is the trench area, and the area on the first surface 111 other than the trench area is the non-trench area, and the adsorption pressure of vacuum adsorption increases from the trench area to the non-trench area; wherein, the adsorption pressure formed by vacuum adsorption on the first surface 111 is 0.1 MPa to 0.01 MPa.

[0072] This technical solution further provides specific steps for applying stress to the second cleaving channel 130 to cleave the wafer 110 and obtain multiple laser chips. Vacuum adsorption with a pressure of 0.01-0.1 MPa, increasing from the trench area to the non-trench area, effectively secures the wafer 110 while preventing excessive local pressure from damaging the chips. The increasing pressure ensures more uniform stress on the wafer 110, and combined with the parameters of the second cleaving channel 130, the stress is precisely applied to the cleaving path, making crack propagation more controllable and improving the cleaving success rate. Simultaneously, stable adsorption reduces wafer 110 offset, improving the perpendicularity of the cleaving surface. The process is compatible with InP / GaAs substrates, meeting packaging requirements.

[0073] In one feasible implementation, the step of applying stress to the second cleaving channel 130 to cleave the wafer 110 further includes: using a laser to ablate and form cracks in the groove tip region of the second cleaving channel 130 to cleave the wafer 110 and obtain multiple laser chips. This configuration, using laser ablation to form cracks, facilitates precise control of the crack initiation point, ensuring the crack initiation point occurs in the groove tip region, thereby facilitating control of the crack propagation direction.

[0074] In one feasible implementation, the step of using a laser to ablate and form cracks in the groove tip region of the second cleaving channel 130 to cleave the wafer 110 and obtain multiple laser chips includes: emitting an initial pulse laser to form a micron-sized initial pit in the groove tip region with a first energy as a crack initiation point; emitting subsequent pulse lasers to form continuous ablation lines in the groove tip extension direction with progressively increasing second energy to form cracks, thereby cleaving the wafer 110 and obtaining multiple laser chips; wherein the second energy is greater than the first energy.

[0075] This technical solution further provides specific steps for the cleavage process. An initial pulsed laser, with a lower first energy, forms a micron-sized pit, precisely locating the crack initiation point and preventing random cracking from the source. Subsequent pulsed lasers, with progressively increasing second energy, form continuous ablation lines, effectively guiding the crack to propagate along a predetermined direction, significantly improving cleavage controllability. This incremental energy design ensures stable crack extension while preventing damage to the chip from excessive energy. Combined with a 130-groove tip structure for the second cleavage path, it optimizes the roughness and perpendicularity of the cleavage surface, is compatible with InP / GaAs substrates, improves cleavage success rate and chip yield, meets packaging precision requirements, and is suitable for mass production scenarios.

[0076] In some examples, the specific process steps of laser cleavage may include: an initial pulse with a low first energy of 1.2-1.5 J / cm. 2 A micron-sized initial pit is formed in the groove tip region, serving as a crack initiation point; subsequent pulses gradually increase the energy to 2.0-2.5 J / cm². 2 A continuous ablation line is formed along the direction of the groove tip.

[0077] According to a second aspect of the embodiments of this application, a laser chip is provided, which is prepared by a laser chip cleaving method as described in any of the above technical solutions; wherein the cavity surface perpendicularity of the laser chip is less than 0.5°.

[0078] The laser chip provided in this application embodiment is prepared using the laser chip cleaving method of any of the above technical solutions. Therefore, the laser chip has all the beneficial effects of the laser chip cleaving method of the above technical solutions, which will not be elaborated here.

[0079] The laser chip provided in this application, fabricated using a laser chip cleaving method, has a cavity surface perpendicularity of less than 0.5°. When the laser is reflected within the cavity, this reduces unexpected optical path differences, avoids power fluctuations caused by multi-beam interference, and ensures stable output optical signals, meeting the signal quality requirements of optical communication. Simultaneously, it reduces light scattering losses caused by cavity surface tilt, improves electro-optical conversion efficiency, and reduces energy waste. Furthermore, the regular cavity surface facilitates uniform coverage of the subsequent anti-oxidation coating, enhancing the device's damage resistance and extending its lifespan. It also meets the precise docking requirements of high-density packaging, reducing positioning deviations during packaging, improving packaging yield, and contributing to stable mass production of the device.

[0080] In this invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise explicitly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0081] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0082] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0083] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A laser chip cleavage method, characterized in that, include: A wafer with a laser pattern fabricated is provided, wherein the patterned side of the wafer is a first side and the substrate side of the wafer is a second side; A first cleaving channel is formed on the first surface, and a second cleaving channel is formed on the second surface. Along the wafer height direction, the outer edge profile of the cross-section of the second cleaving channel gradually decreases in width in the direction from the second surface to the first surface. Stress is applied to the second cleaving path to cleave the wafer and obtain multiple laser chips; The step of providing a wafer with a patterned laser, wherein the patterned side of the wafer is a first side and the substrate side of the wafer is a second side, includes: The wafer provided completes the laser pattern fabrication; The wafer is thinned to a thickness of 50 μm to 150 μm; Along the wafer height direction, the outer edge profile of the cross-section of the second cleaving channel is V-shaped, and the tip of the V-shape is oriented toward the first cleaving channel; The ratio of the etching depth of the second cleavage path to the thickness of the wafer is 30% to 40%; The groove angle of the second cleavage path is 53.7° to 55.7°; The radius of curvature of the groove tip of the second cleavage channel is ≤100nm.

2. The laser chip cleavage method according to claim 1, characterized in that, The steps of forming a first cleavage path on the first surface and forming a second cleavage path on the second surface include: A portion of the insulating film on the first surface of the wafer is etched using a BOE solution to form multiple first cleavage paths; Multiple second cleavage paths are formed on the second surface of the wafer by deep reactive ion etching, and the multiple second cleavage paths are arranged opposite to the first cleavage path.

3. The laser chip cleavage method according to claim 2, characterized in that, The step of forming a plurality of second cleavage paths on the second surface of the wafer by deep reactive ion etching, wherein the plurality of second cleavage paths are arranged opposite to the first cleavage path, includes: First, use the first power to etch to the target depth; Then, a second power is used to continue etching so that the second cleavage path reaches the designed depth. Wherein, the second power is less than the first power, and the difference between the design depth and the target depth is greater than or equal to 3 μm.

4. The laser chip cleavage method according to any one of claims 1 to 3, characterized in that, The step of applying stress to the second cleaving track to cleave the wafer and obtain multiple laser chips includes: The wafer is fixed by vacuum adsorption; Stress is applied to the second cleaving path to cleave the wafer and obtain multiple laser chips; Among them, the area where the first cleavage channel is located is the groove area, and the area on the first surface other than the groove area is the non-groove area. The vacuum adsorption pressure increases from the groove area to the non-groove area. The adsorption pressure formed by vacuum adsorption on the first surface is 0.1 MPa to 0.01 MPa.

5. The laser chip cleavage method according to claim 4, characterized in that, The step of applying stress to the second cleaving track to cleave the wafer further includes: A laser is used to ablate and form cracks in the groove tip region of the second cleaving path to cleave the wafer and obtain multiple laser chips.

6. The laser chip cleavage method according to claim 5, characterized in that, The step of using a laser to ablate and form cracks in the groove tip region of the second cleaving path to cleave the wafer and obtain multiple laser chips includes: An initial pulse laser is emitted, and a micron-sized initial pit is formed in the groove tip region with the first energy, which serves as the crack initiation point; A subsequent pulsed laser is emitted, and a continuous ablation line is formed in the direction of the groove tip extension using a progressively increasing second energy to create cracks, thereby cleaving the wafer and obtaining multiple laser chips; The second energy is greater than the first energy.

7. A laser chip, characterized in that, The laser chip is fabricated by the laser chip cleaving method as described in any one of claims 1 to 6; The perpendicularity of the cavity surface of the laser chip is less than 0.5°.

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