A programmable filtering device

Abstract

The application discloses a programmable filtering device, which comprises at least one filtering basic unit, the unit contains a control component, a current calculation component and a history calculation component, and the two calculation components are decoupled. The control component comprises a first control module and a second control module. The first control module receives a filtering starting signal and triggers the current calculation component to start. The current calculation component generates a first ending signal and transmits the signal to the second control module after completing the calculation at the current moment based on a preset filtering algorithm according to current input data and a history calculation cumulative result. The second control module receives the signal and triggers the history calculation component to start. The history calculation component outputs a second ending signal after completing the calculation task related to the history result in the algorithm. The application can reduce the calculation load of an MCU, and can realize complex filtering functions and complex control loop algorithms through simple configuration.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of application control, and in particular to a programmable filtering device. Background Technology

[0002] In motor control or digital power supply control applications, the feedback loop design of the control algorithm involves the use of FIR or IIR filters, and the use of these filters is implemented in the interrupt function of the MCU. In order to obtain better control performance, the interrupt control frequency of the loop is often increased (loop calculation frequency above 100KHz), which places extremely high demands on the computing power of the MCU. Ordinary MCUs are difficult to meet the real-time calculation requirements at this frequency.

[0003] In the industry, filter calculations are typically performed using the CPU, meaning the filtering algorithm for the control loop is calculated purely in software. This approach is limited by the performance of the CPU and SRAM. As the demand for higher control loop frequencies becomes increasingly urgent, issues may arise regarding the loop's timely execution, thus failing to achieve optimal control performance. Furthermore, in most advanced control applications, a single-stage filter unit is insufficient; multiple cascaded filter units are often required. Multi-stage filtering calculations place a greater burden on the CPU. In recent years, some controller peripherals have emerged that implement filter algorithms in hardware; however, these suffer from slower computation speeds and less flexibility in use. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The programmable filtering device provided in this application embodiment can reduce the computational load of the MCU, and at the same time, it can realize complex filtering functions through simple configuration, thereby realizing complex control loop algorithms.

[0006] This application provides a method including at least one filtering basic unit; the filtering basic unit includes a control component, a current calculation component, and a historical calculation component; the current calculation component and the historical calculation component are decoupled; the control component includes a first control module and a second control module; wherein, the first control module receives a filtering start signal and triggers the current calculation component to start calculation based on the filtering start signal; the current calculation component generates a first end signal after completing the calculation at the current moment based on the current input data and the cumulative results of historical calculations according to a preset filtering algorithm, and transmits the first end signal to the second control module; the second control module, after receiving the first end signal, triggers the historical calculation component to start calculation based on the first end signal; the historical calculation component outputs a second end signal after completing the calculation tasks related to historical results in the preset filtering algorithm.

[0007] In one embodiment of this application, when multiple filtering basic units are cascaded, the current computing component of the previous filtering basic unit transmits the first end signal generated to the first control module of the next filtering basic unit, and the first end signal serves as the trigger signal for the current computing component of the next filtering basic unit.

[0008] In one embodiment of this application, when multiple filtering basic units are connected in parallel, the historical calculation component of the subsequent filtering basic unit is connected to the historical calculation component of the first-level filtering basic unit to form a merged historical calculation structure.

[0009] In one embodiment of this application, both the current calculation component and the historical calculation component are provided with parameter configuration ports, which are used to adjust the filter order parameter.

[0010] In one embodiment of this application, the filtering order of the basic filtering unit is 4th order.

[0011] In one embodiment of this application, when the three filtering basic units are connected in parallel, the resulting merged history calculation structure supports 12th-order filtering calculation.

[0012] In one embodiment of this application, the current calculation component is provided with a result output terminal, which is used to output the current calculation result after the current calculation component completes the calculation.

[0013] In one embodiment of this application, the basic filtering unit is provided with a hardware configuration interface, which is used to adjust the input-output relationship of the basic filtering unit.

[0014] In one embodiment of this application, when multiple filtering basic units are connected in parallel, the hardware configuration interface is used to bypass the current computing components of the remaining subsequent filtering basic units except for the first stage.

[0015] In one embodiment of this application, the preset filtering algorithm is an FIR filtering algorithm or an IIR filtering algorithm.

[0016] This application provides a programmable filtering device, including at least one basic filtering unit. This basic unit includes a control component, a current calculation component, and a historical calculation component, wherein the current calculation component and the historical calculation component are decoupled. The control component includes a first control module and a second control module. The first control module receives a filtering start signal and triggers the current calculation component to start calculation based on the filtering start signal. The current calculation component generates a first end signal after completing the calculation at the current moment based on a preset filtering algorithm, according to the current input data and the accumulated results of historical calculations, and transmits the first end signal to the second control module. After receiving the first end signal, the second control module triggers the historical calculation component to start calculation based on the first end signal. The historical calculation component outputs a second end signal after completing the calculation tasks related to historical results in the preset filtering algorithm. This application implements the filter algorithm in pure hardware and decouples the current calculation and historical calculation, thereby reducing the computational load of the MCU and helping to increase the calculation frequency of the loop. Simultaneously, the basic filtering units can be flexibly cascaded or connected in parallel, and complex filter functions can be implemented through simple configuration, thereby realizing complex control loop algorithms. Attached Figure Description

[0017] Figure 1 This is a structural diagram of the basic filtering unit provided in the embodiments of this application; Figure 2 This is a schematic diagram of a portion of a three-stage cascaded basic filtering unit provided in an embodiment of this application; Figure 3 This is another schematic diagram of the cascaded three-stage basic filtering unit provided in the embodiments of this application; Figure 4 This is a schematic diagram of a portion of the three-stage parallel connection of the basic filtering unit provided in this application embodiment; Figure 5 This is a schematic diagram of another part of the three-stage parallel connection of the basic filtering unit provided in the embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] It should be noted that although the flowchart shows a logical order, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., used in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the structures, proportions, sizes, etc., depicted in the drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application. Similarly, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are only for clarity of description and are not used to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] In motor control or digital power supply control applications, the feedback loop design of the control algorithm involves the use of FIR or IIR filters, and the use of these filters is implemented in the interrupt function of the MCU. In order to obtain better control performance, the interrupt control frequency of the loop is often increased (loop calculation frequency above 100KHz), which places extremely high demands on the computing power of the MCU. Ordinary MCUs are difficult to meet the real-time calculation requirements at this frequency.

[0022] The industry typically uses CPUs to calculate filters, meaning the filtering algorithm for the control loop is calculated purely in software. This approach has significant drawbacks: performance is limited by CPU computing power and SRAM read / write speed. As the demand for higher loop control frequencies increases, loop execution becomes more untimely, compromising control effectiveness. In most advanced control scenarios, single-stage filtering units are insufficient, requiring cascaded multi-stage filtering units. However, multi-stage filtering calculations further burden the CPU, exacerbating real-time performance issues. In recent years, some controllers with integrated hardware peripherals have emerged that can directly implement filter algorithms. However, these still suffer from two major problems: slow calculation speed, making it difficult to meet high-frequency control requirements above 100kHz; and insufficient flexibility, unable to flexibly support the stacking of multiple filters, limiting their applicability to various scenarios.

[0023] In view of this, embodiments of this application provide a programmable filtering device, including at least one basic filtering unit. This basic unit includes a control component, a current calculation component, and a historical calculation component, wherein the current calculation component and the historical calculation component are decoupled. The control component includes a first control module and a second control module. The first control module receives a filtering start signal and triggers the current calculation component to start calculation based on the filtering start signal. The current calculation component generates a first end signal after completing the calculation at the current moment based on a preset filtering algorithm, according to the current input data and the accumulated results of historical calculations, and transmits the first end signal to the second control module. After receiving the first end signal, the second control module triggers the historical calculation component to start calculation based on the first end signal. The historical calculation component outputs a second end signal after completing the calculation tasks related to historical results in the preset filtering algorithm. Embodiments of this application implement the filter algorithm in pure hardware and decouple the current calculation and historical calculation, thereby reducing the computational load on the MCU and helping to increase the calculation frequency of the loop. Simultaneously, the basic filtering units can be flexibly cascaded or connected in parallel, and complex filter functions can be implemented through simple configuration, thereby realizing complex control loop algorithms.

[0024] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0025] Reference Figure 1 , Figure 1 This is a structural diagram of a basic filtering unit provided in an embodiment of this application. The device includes at least one programmable basic filtering unit, each of which supports up to 4th-order FIR or IIR filtering calculations (the filtering order can be flexibly adjusted through parameter configuration). The basic filtering unit includes a control component, a current calculation component (Block A), and a historical calculation component (Block B). The control component is used to trigger the working sequence of the current calculation component and the historical calculation component to realize pipelined asynchronous calculation.

[0026] In one feasible embodiment, both the current calculation component and the historical calculation component are equipped with parameter configuration ports, which are used to adjust the filter order parameter. Specifically, both Block A and Block B are equipped with parameter configuration ports for loading filter coefficients (such as B[k], A[k]) and adjusting the filter order parameter. By configuring different coefficients (B[k] is the numerator coefficient of FIR / IIR, and A[k] is the denominator coefficient of IIR), it is possible to adapt to FIR or IIR filtering algorithms and flexibly adjust the actual working filter order (for example, when only the 2nd order is used, the higher-order coefficients can be set to 0).

[0027] In one feasible embodiment, the current computing component is provided with a result output terminal, which is used to output the current calculation result in real time after the current computing component completes the calculation, so as to ensure the real-time performance of the control loop.

[0028] In one feasible embodiment, the workflow of these components includes: the current calculation component receives the current input data (FLTRn_XIN), the FLTRn_Zsrc and FLTRn_Ysrc signals related to the historical calculation cumulative results, and completes the core calculation at the current moment based on a preset filtering algorithm (FIR filtering algorithm or IIR filtering algorithm), outputting the result FLTRn_YOUT; the historical calculation component executes the preset filtering algorithm related to historical results (such as historical delays). The computational tasks related to historical coefficient weighting (multiplication operations of A[1]-A[4], B[1]-B[4], etc.) involve updating historical signals such as FLTRn_ZIN and FLTRn_YIN (FLTRn represents the nth basic filtering unit) to maintain the cumulative results of historical calculations. In particular, BlockA and BlockB are decoupled in terms of timing and function: the calculation and output of BlockA do not depend on the completion state of BlockB, and the calculation of BlockB does not block the output of BlockA, thereby improving real-time performance.

[0029] Furthermore, the control components include a first control module (Phase 1) and a second control module (Phase 2). Phase 1 receives the filter start signal FLTRn_START and triggers Block A to start calculation based on this signal. After Block A completes the calculation, it outputs the calculation result FLTRn_YOUT and generates a first end signal FLTRn_PH1_DNE, which is then transmitted to Phase 2. After receiving the FLTRn_PH1_DNE signal, Phase 2 triggers Block B to start calculation. After Block B completes the calculation, it outputs a second end signal FLTRn_PH2_DNE and updates the cumulative results of historical calculations (involving the processing of historical signals such as FLTRn_ZIN and FLTRn_YIN, and related to the signal sources and historical iteration logic of FLTRn_Zsrc and FLTRn_Ysrc).

[0030] It should be noted that BlockA, as the latest data calculation module, takes the current data FLTRn_XIN and the historical cumulative result FLTRn_Zsrc as input. After completing the calculation, it can immediately output FLTRn_YOUT (and simultaneously generate FLTRn_PH1_DNE) without waiting for BlockB's calculation to complete, thus achieving rapid output of the current result and avoiding hardware waiting. BlockB, as the historical result calculation module, starts automatically after BlockA completes its calculation, and its calculation process does not affect the real-time output of FLTRn_YOUT. This decoupling design of BlockA and BlockB is key to realizing high-frequency filtering calculations.

[0031] In one feasible embodiment, the basic filtering unit is provided with a hardware configuration interface, which is used to adjust the input-output relationship of the basic filtering unit and supports topologies such as cascade and parallel connection to adapt to complex filtering scenarios.

[0032] In a feasible embodiment, the calculations performed by these four modules (Phase 1, Phase 2, Block A, and Block B) are as follows:

[0033] Where N is the order of the filter, and the maximum value of N is 4: In terms of hardware, only the values ​​of A[k] (IIR denominator coefficient) and B[k] (FIR / IIR numerator coefficient) need to be modified to adapt to the filtering requirements of different application scenarios.

[0034] In one feasible embodiment, when multiple filter basic units are cascaded, the Block A of the preceding filter basic unit transmits the generated FLTRn_PH1_DNE (first end signal) to the Phase 1 of the following filter basic unit as the start trigger signal for the following Block A; simultaneously, the FLTRn_YOUT of the preceding unit serves as the FLTRn_XIN of the following unit. Figure 2 , 3 As shown, using Figure 1 The basic unit can realize multi-stage cascaded filters (taking a 3-stage cascade as an example). Thanks to the decoupling characteristic of Block A and Block B, efficient timing can still be maintained during cascading. Specifically: the first-stage basic unit Block A is completed → triggering the second-stage basic unit Block A; the second-stage is completed → triggering the third-stage basic unit Block A. After each Block A is completed, the result of this stage can be output quickly without waiting for the calculation of Block B or all subsequent stages. This pipelined cascading calculation can significantly reduce the overall latency of multi-stage filtering, and the hardware only needs to trigger multiple stages of operation once. It is particularly suitable for complex scenarios such as multi-band segmented filtering and cascaded IIR filtering, and can support higher control frequencies compared to pure software calculation.

[0035] In one feasible embodiment, when multiple filter basic units are connected in parallel, the Block B of the later-stage filter basic unit is connected to the Block B of the first-stage filter basic unit to form a merged historical calculation structure to expand the filter order.

[0036] In one feasible embodiment, when the three basic filtering units are connected in parallel, since the basic filtering units perform filter calculations up to the 4th order, the resulting merged historical calculation structure supports filter calculations of the 12th order, that is, the value of N is expanded to 4×3=12th order.

[0037] It should be noted that the embodiments of this application do not limit the number of cascaded filter basic units, and can be flexibly configured according to actual needs; at the same time, the embodiments of this application do not limit the number of parallel filter basic units, and can be flexibly set as needed.

[0038] In one feasible embodiment, when multiple basic filtering units are connected in parallel, the hardware configuration interface can be used to bypass the Block A of all subsequent basic filtering units except the first stage (i.e., skip the Block A calculations of the second, third, etc. stages, and directly reuse the output of the first-stage Block A as the input of the subsequent Block B). With this design, the first-stage Block A can output the result immediately after completion of its calculation, and all parallel Block Bs asynchronously process historical calculations (without affecting real-time output). This retains the advantage of Block A's fast output while enabling higher-order filtering through multiple parallel Block Bs. Figure 4 and 5 As shown, in the parallel configuration, the second and third stage filtering units need to bypass the Phase 1 calculations. This means skipping the Block A calculations of the second and third stage filtering units and directly merging their Block B modules into the first stage's Block B module. Furthermore, with parallel operation, the calculation result can be output directly as soon as the first stage filtering unit's Block A calculation is complete, without waiting for the historical calculations of Block B to be finished. This also leverages the advantage of fast output results resulting from the decoupling of Block A and Block B.

[0039] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A programmable filter device, characterized in that, It includes at least one basic filtering unit; the basic filtering unit includes a control component, a current calculation component, and a historical calculation component; the current calculation component and the historical calculation component are decoupled in terms of timing and function; the control component includes a first control module and a second control module; The filtering basic unit is provided with a hardware configuration interface, which is used to adjust the input-output relationship of the filtering basic unit; both the current calculation component and the historical calculation component are provided with parameter configuration ports, which are used to adjust the filtering order parameter; the current calculation component is provided with a result output terminal, which is used to output the current calculation result after the current calculation component completes the calculation. The first control module receives a filtering start signal and triggers the current computing component to start computing based on the filtering start signal; the current computing component outputs the current computing result after completing the current calculation based on the current input data and the cumulative results of historical calculations using a preset filtering algorithm, and at the same time generates a first end signal and transmits the first end signal to the second control module; the calculation and output of the current computing component do not depend on the completion status of the historical computing components. After receiving the first end signal, the second control module triggers the historical calculation component to start calculation based on the first end signal; after completing the calculation tasks related to historical results in the preset filtering algorithm, the historical calculation component outputs a second end signal and updates the cumulative results of historical calculation; the calculation of the historical calculation component does not block the result output of the current calculation component.

2. The programmable filter device according to claim 1, characterized in that, When multiple filtering basic units are cascaded, the first end signal generated by the current computing component of the previous filtering basic unit is transmitted to the first control module of the next filtering basic unit. The first end signal serves as the trigger signal for the current computing component of the next filtering basic unit.

3. The programmable filter device according to claim 1, characterized in that, When multiple filtering basic units are connected in parallel, the historical calculation component of the subsequent filtering basic unit is connected to the historical calculation component of the first-level filtering basic unit to form a merged historical calculation structure.

4. The programmable filter device according to claim 1, characterized in that, The filtering order of the basic filtering unit is 4.

5. The programmable filter device according to claim 4, characterized in that, When the three basic filtering units are connected in parallel, the resulting merged history calculation structure supports 12th-order filtering calculations.

6. The programmable filter device according to claim 1, characterized in that, When multiple filtering basic units are connected in parallel, the hardware configuration interface is used to bypass the current calculation components of the remaining subsequent filtering basic units, except for the first stage.

7. The programmable filter device according to claim 1, characterized in that, The preset filtering algorithm is either an FIR filtering algorithm or an IIR filtering algorithm.

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